產品資訊

Features Document Support

Core: Arm^® 32-bit Cortex^®-M3 CPU
- 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance
- 64 Byte cache for instruction and data bus support 0 wait state memory access
- Single-cycle multiplication and hardware division
Memories
- 96 or 128Kbytes of Flash memory
- 28 Kbytes of SRAM
Clock, reset and supply management
- 2.0 to 3.6 V application supply and I/Os
- POR, PDR, and programmable voltage detector (PVD)
- 4-to-16 MHz crystal oscillator
- Internal 8 MHz factory-trimmed RC
- Internal 48 MHz factory-trimmed RC
- Internal 32 KHz RC
- PLL for CPU clock
- 32 KHz oscillator for RTC with calibration
Low power
- Sleep, Stop and Standby modes
- VBAT supply for RTC and backup registers
- Run mode: ~160uA/MHz
- Stop mode: ~18.5uA @3.3V
- Standby mode: ~4.5uA @3.3V
- VBAT with RTC: ~1.1uA @3.3V
12-bit mode ADC
- Max convert rate: 1Msps
- Up to 16 A/D channels
- Flexible sample and converter modes
- Temperature sensor
Comparator
- 2 independent comparators
- Each with 4 positive and 4 negative input channels
LED driver unit
- Capable of drive 56 LEDs or 8 Seven-segment LEDs
Up to 51 fast I/O ports
- 37/51 I/Os, all mappable on 16 external interrupt vectors
Debug mode
- Serial wire debug (SWD) interface
7 timers
- Three 20-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
- 20-bit, motor control PWM timer with dead-time generation and emergency stop
- 2 watchdog timers (Independent and Window)
- SysTick timer: a 24-bit downcounter
Up to 11 communication interfaces
- 2 x I2C interfaces (SMBus/PMBus)
- 3 UARTs (IrDA capability, modem control)
- 3 SPI interfaces, 1 QSPI interface
- I2S interface
- USB 2.0 full-speed device interface
2 DMA controller, triggered by Timers, ADC, SPIs, I2Cs, UARTs
CRC calculation unit, 96-bit unique ID
RNG generate Random number
Packages are ECOPACK ®