產品資訊

Features Document Support

Core: Arm^® 32‐bit Cortex^®‐M3 CPU
- 96 MHz maximum frequency
- Single‐cycle multiplication and hardware division
Memories
- 256 K‐byte Flash memory, 0 wait state from 0 to 48 MHz and 1 wait states above.
- 64 K‐byte SRAM, performance at 0 wait state memory access.
Reset and supply management
- VDD:2V
- Power On Reset(POR),Power Down Reset(PDR), Programmable Voltage Detector(PVD)
Clock
- External 4 ~ 24 MHz high speed clock(HSE)
- Internal 8 MHz high speed clock (HSI)
- External 32 KHz Low speed clock (LSE)
- Internal 40 KHz Low speed clock (LSI)
Operation temperature
- ‐40°C~+105°C
Low power
- Sleep, Stop and Standby modes
- VBAT power supply mode (RTC and backup register)
Up to 80 fast I/O ports
- All mappable on 16 external interrupt vectors，and most are compatible with 5V
Debug mode
- SWD/Trace interface
3 x 12‐bit, A/D converters , up to 18 channels(Contains built‐in temperature sensor and internal reference voltage two channels)
2 x 12‐bit D/A converters
Up to 15 communication interfaces
- Up to 2 I2C interface
- Up to 5 USARTs (ISO 7816 interface, LIN, IrDA capability, maximum rate is 4.5Mbit/s , MODEM control，low power monitoring function and can wake MCU)
- 3 SPI interfaces, 1 QSPI interface
- 1 CAN, 1 USB, 1 SDIO
Up to 11 timers
- 4 general timers (32 bit)
- 2 advanced timer (32‐bit)
- 2 IWDG
- 1 SysTick timer:
- 2 basic timers(32‐bit)
CRC calculation unit
128‐bit unique ID
Advanced Encryption Standard (AES)
ESD (±5KV) HBM, Latch‐Up (±800mA)
TRNG generate true Random number
Built‐in ISP Bootloader , supports program upgrade through USART
3 high speed rail to rail operational amplifiers