產品資訊
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- 產品資訊
- Value Line
- MG32F02D SERIES
- MG32F02D032
MG32F02D SERIES
MG32F02D032
CPU Core
ARM 32-bit Cortex-M0 CPU- Operation frequency up to 24MHz
- Built-in one NVIC for 32 external interrupt inputs with 4-level priority
- Built-in one 24-bit system tick timer
- Built-in one single-cycle 32-bit multiplier
- Built-in one SWD serial wire debugger with 2 watch points and 4 breakpoints
- Flash Memory
- Built-in embedded 32K bytes flash memory for application code
- Built-in embedded 6K bytes flash memory for ISP code and IAP data
- Support ISP (In-system program) for application code update
Support programmable ISP flash memory size for ISP boot code
- Support IAP (In-application program) for application data update
- Support programmable IAP flash memory size
- Support ICP (In-circuit program) for ISP boot code update through SWD interface
- Support flash memory page erase in 512 bytes
- SRAM Memory
- Built-in embedded 2K+128 bytes SRAM
- Power
- Built-in one embedded regulator for core logic power
- Built-in brown-out detectors
- BOD1 detect by selected level 4.2V/3.6V/2.4V/2.0V
- Built-in a power management controller with power-down and wakeup control
- Support three power operation modes
- ON(Normal) mode and SLEEP , STOP power down modes
- Support wake-up from SLEEP/STOP modes via multiple sources
- Reset
- Built-in embedded POR (power-on reset) circuit
- Built-in one reset source controller
- Programmable chip cold reset and warm reset for reset source
- Independent software reset control for internal modules
- Provide multiple reset source
- POR/BOD/External reset pin input/Software force reset
- IWDT
- Illegal address error reset/Flash access protect error reset
- Missing clock detect (MCD) reset
- Clock
- Built-in embedded ILRCO (internal low frequency RC oscillator) by 32KHz
- Built-in embedded IHRCO (internal high frequency RC oscillator)
- Trimmed to 24MHz ±1% at +25℃
- Support external clock input up to 24MHz
- Built in a clock source controller with independent clock enable control for modules
- GPIO
- Support general purpose IO pins for application
- Maximum 13 GPIO pins for QFN20 package
- Provide selectable IO modes by pin independent
- Push-Pull output
- Quasi bidirectional (PC pins only)
- Open-drain output
- Digital Input with high impedance
- Analog IO
- Flexible pin alternate function selection
- Support programmable drive strength by pin independent
- Support IO deglitch filter by pin independent
- Support input inverse selection by pin independent
- Support pull-high option by pin independent
- Support high speed option by pin independent except RSTN, XIN
- GPIO pin state and IO mode setting keep optional after reset
- Interrupt Support
- Built-in one EXIC (external interrupt controller) for NVIC connection
- Independent high/low level and rising/falling edge trigger selection
- Built-in one WIC (wakeup interrupt controller) for wakeup event control
- All GPIO pins can be configured as interrupt source and key pad input
- Support port OR logic for interrupt function
- Support external pins for CPU NMI function
- Timer
- Provide six timers/counters : TM00,TM01,TM36
- Timer module common functions
- Selectable Full-counter, Cascade, Separate timer operation modes
- Multiple internal and external signals as timer clock source or trigger source
- Support timer reset, trigger start and clock gating for trigger source function
- Timer overflow as clock output to external pin output
- Auto-stop mode by main counter counting
- Provide TM36 timer module
- 16-bit timer with 16-bit prescaler
- 2 CCP (input Capture/output Compare/PWM) channels
- 2 CCP channels with OCN (complementary output compare)
- PWM function with center/edge-align, dead time control and break control
- Extra repetition counter for auto-stop mode
- Support duty capture function
- Up to 96MHz clock source for PWM output
- Provide TM0x timer modules (TM00,TM01)
- 8-bit timer with 8-bit prescaler
- Watchdog Timer
- Built-in one IWDT (Independent Watch Dog Timer)
- 8-bit down counter with 12-bit prescaler and clocked by ILRCO clock
- Operating capability in SLEEP and STOP modes
- Selectable reset or interrupt when the counter underflow
- Support two early wakeup comparators with interrupt
- I2C
- Provide one I2c module: I2C0
- I2C module common functions
- Support master and slave mode
- Support programmable clock rate control and clock rate up to 400 KHz
- Support programmable high/low period control for master mode
- Support clock stretching for slave mode
- Support general call function
- Support multi-master processing capability
- Support both Byte mode and Buffer mode flow control
- Support Byte mode bus event code for simplex firmware control
- Support Buffer mode 4-byte data buffer and 32-bit data register for high speed communication
- Received and transmitted data are buffered with DMA capability
- Support slave address hardware detection wakeup from STOP mode
- Support SMBus timeout detection
- UART
- Provide one UART modules: URT4
- UART module common functions
- Provide precise UART baud-rate control by programmable oversampling rate
- Support baud rate up to 6 Mbit/s
- Programmable data word length - 7 or 8 bits
- Programmable 4~32 oversampling rate
- Hardware parity checking and parity generation
- Swappable TX/RX pin configuration
- Separate signal polarity control for transmission and reception
- Support fundamental UART mode
- Support TX/RX independent 8-bit data register for simplex firmware control
- Configurable stop bits - 1 or 2 stop bits
- SPI
- Provide one modules for SPI communication: SPI0
- Support master and slave mode
- Support full duplex , half duplex or simplex communication mode
- Support data communication without NSS(slave select signal)
- Support master data input sampling delay half of SPI clock
- Support slave data output advance half of SPI clock
- Support programmable clock rate control
- Support clock rate up to 12 MHz for master/slave
- Selectable 8/16/24/32-bit frame size
- Support 4-byte data buffer and 32-bit data register for high speed communication
- Support multi-master processing capability
- Selectable clock polarity and phase
- Selectable MSB or LSB first data order
- NSS line management by hardware or software for master mode
- Configurable data transfer modes
- Standard SPI mode (separated transmit and receive line)
- Single/Dual/Quad SPI mode with bidirectional data transfer
- Data transmit/receive overrun detect
- ADC
- 12-bit SAR ADC with 250 Ksps
- Configurable resolution : 12/10/8-bit
- Configurable sampling time
- Provide external 4 channels and internal 4 channels input
- Internal extra channel source : VBUF, VSSA, DAC_P0, DAC_P1
- Data alignment for output code left/right justify
- Fixed ADC top voltage reference from internal VDD
- Interrupt generation at the end of sampling, end of conversion, end of sequence conversion
- Support voltage window detection and output code limitation
- Support one-shot/channel scan/loop scan
- DAC
- Two 12-bit voltage DAC
- Maximum conversion rate is 50 Ksps
- Conversion start trigger by register written, external pin and internal events
- Build in internal output buffer
- Support DAC output on SLEEP and STOP modes
- Misc.
- Timer synchronous enable global control
- 8-bit non-reset backup register
- Provide on chip 16 bytes Unique ID code
- Operating
- Operating temperature range -10℃ ~ 50℃ (**1)
- Operating frequency range up to 24MHz
- Package Types
- QFN20
- (**1): Tested by sampling.
