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- Low Pin Count 8051 MCU
- 82 SERIES
- MG82FG5B32
82 SERIES
MG82FG5B32
1-T 80C51 Central Processing Unit- MG82FG5B32 with 32K Bytes flash ROM
ISP memory zone could be optioned as 1KB/1.5KB~4KB- Flexible IAP size by software configured
- Code protection for flash memory access
- Flash erase/program cycle: 10,000 times
- Flash data retention: 100 years at 25℃
- Default MG82FG5B32 Flash space mapping
AP 29.5KB 0000h~75FFh IAP 1KB 7600h~79FFh ISP 1.5KB 7A00h~7FFFh
- Data RAM
- On-chip 256 bytes scratch-pad RAM
- 1792 bytes expanded RAM (XRAM)
- Dual data pointer
- Interrupt controller
- 16 sources, four-level-priority interrupt capability
- Four external interrupt inputs, nINT0, nINT1, nINT2 and nINT3, with glitch filter
- All external interrupts support High/Low level or Rising/Falling edge trigger
- Three 16-bit timer/counters, Timer 0, Timer 1 and Timer 2
- T0CKO on P34, T1CKO on P35 and T2CKO on P10
- X12 mode enabled for T0/T1/T2
- S1BRG cascaded with Timer 1 to a 16/24-bit timer/counter
- Programmable 16-bit counter/timer Array (PCA) with 8 compare/capture modules
- Programmable 16-bit PCA base counter
- Up to 100MHz clock source from on-chip CKM
- Capture mode, 16-bit software timer mode and High speed output mode
- 8/10/12/16-bit PWM mode with phase shift function, up to 8-channel PWM
- PWM module with dead-time control and central-aligned option
- Keypad Interrupt
- 10-Bit ADC
- Programmable throughput up to 200 ksps
- Up to 8 channel single-ended inputs
- Enhanced UART (S0)
- Framing Error Detection
- Automatic Address Recognition
- Speed improvement mechanism (X2/X4 mode)
- SPI master supported in mode 4
- Secondary UART (S1)
- Dedicated Baud Rate Generator shares to S0 or set as an 8-bit timer
- SPI master supported in mode 4
- One Master/Slave SPI serial interface (SPI)
- Max. SPI clock frequency up to 12MHz.
- Up to 3 SPI masters including S0 and S1 in mode 4
- Three two-wire-serial-interface: TWSI, TWI1 and SID(TWI2)
- Two Master/Slave hardware engine: TWSI and TWI1
- 3 device address recognized in TWSI/TWI1 slave mode
- Two wire serial interface Start/Stop detection (SID) to support 3rd TWI slave interface
- On-Chip-Debug interface (OCD)
- Programmable Watchdog Timer, clock sourced from ILRCO
- One time enabled by CPU or power-on
- Interrupt CPU or Reset CPU on WDT overflow
- Support WDT function in power down mode (watch mode)
- Real-Time-Clock module
- 0.5S ~ 64S programmable interrupt period
- 21-bit length system timer
- Beeper function
- Maximum 29 GPIOs in 32-pin package
- P3 can be configured to quasi-bidirectional, push-pull output, open-drain output and input only
- P1, P2, P4 and P6 can be configured to open-drain output or push-pull output
- P6.0, P6.1 and P4.7 shared with XTAL2, XTAL1 and RST
- Multiple power control modes: idle mode, power-down mode, slow mode, sub-clock mode, RTC mode, watch mode and monitor mode.
- All interrupts can wake up IDLE mode
- 11 sources to wake up Power-Down mode
- Slow mode and sub-clock mode support low speed MCU operation
- RTC mode supports RTC to resume CPU in power down
- Watch mode supports WDT to resume CPU in power down
- Monitor mode supports BOD1 to resume CPU in power down
- Two Brown-Out Detectors
- BOD0: detect 1.7V
- BOD1: selected detection level on 4.2V/3.7V/2.4V/2.0V
- Interrupt CPU or reset CPU
- Wake up CPU in Power-Down mode
- Operating voltage range: 1.8V – 5.5V
- Minimum 1.7V requirement in flash write operation (ISP/IAP/ICP)
- Operating frequency range: 25MHz(max)
- External crystal mode, 0 – 12MHz @ 1.8V – 5.5V and 0 – 25MHz @ 2.7V – 5.5V
- CPU up to 12MHz @ 1.8V – 5.5V and up to 25MHz @ 2.2V – 5.5V
- Clock Sources
- Internal 12MHz/11.059MHz oscillator (IHRCO): factory calibrated to ±1%, typical
- External crystal mode, support 32.768KHz oscillating and missing clock detection (MCD)
- Internal Low power 32KHz RC Oscillator (ILRCO)
- External clock input (ECKI) on P6.0/XTAL2
- Internal Oscillator output on P6.0/XTAL2
- On-chip Clock Multiplier (CKM) to provide high speed clock source
- Operating Temperature:
- Industrial (-40℃ to +85℃)*
- 16-Bytes Unique ID code
Note*: Tested by sampling.
