|
MG32F157 Standard Peripherals Firmware Library
|
Core Register type definitions. More...
Data Structures | |
| union | APSR_Type |
| Union type to access the Application Program Status Register (APSR). More... | |
| union | IPSR_Type |
| Union type to access the Interrupt Program Status Register (IPSR). More... | |
| union | xPSR_Type |
| Union type to access the Special-Purpose Program Status Registers (xPSR). More... | |
| union | CONTROL_Type |
| Union type to access the Control Registers (CONTROL). More... | |
Macros | |
| #define | APSR_N_Pos 31U |
| #define | APSR_N_Msk (1UL << APSR_N_Pos) |
| #define | APSR_Z_Pos 30U |
| #define | APSR_Z_Msk (1UL << APSR_Z_Pos) |
| #define | APSR_C_Pos 29U |
| #define | APSR_C_Msk (1UL << APSR_C_Pos) |
| #define | APSR_V_Pos 28U |
| #define | APSR_V_Msk (1UL << APSR_V_Pos) |
| #define | APSR_Q_Pos 27U |
| #define | APSR_Q_Msk (1UL << APSR_Q_Pos) |
| #define | IPSR_ISR_Pos 0U |
| #define | IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
| #define | xPSR_N_Pos 31U |
| #define | xPSR_N_Msk (1UL << xPSR_N_Pos) |
| #define | xPSR_Z_Pos 30U |
| #define | xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
| #define | xPSR_C_Pos 29U |
| #define | xPSR_C_Msk (1UL << xPSR_C_Pos) |
| #define | xPSR_V_Pos 28U |
| #define | xPSR_V_Msk (1UL << xPSR_V_Pos) |
| #define | xPSR_Q_Pos 27U |
| #define | xPSR_Q_Msk (1UL << xPSR_Q_Pos) |
| #define | xPSR_ICI_IT_2_Pos 25U |
| #define | xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) |
| #define | xPSR_T_Pos 24U |
| #define | xPSR_T_Msk (1UL << xPSR_T_Pos) |
| #define | xPSR_ICI_IT_1_Pos 10U |
| #define | xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) |
| #define | xPSR_ISR_Pos 0U |
| #define | xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
| #define | CONTROL_SPSEL_Pos 1U |
| #define | CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
| #define | CONTROL_nPRIV_Pos 0U |
| #define | CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) |
Core Register type definitions.
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
| #define APSR_C_Pos 29U |
APSR: C Position
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
| #define APSR_N_Pos 31U |
APSR: N Position
| #define APSR_Q_Msk (1UL << APSR_Q_Pos) |
APSR: Q Mask
| #define APSR_Q_Pos 27U |
APSR: Q Position
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
| #define APSR_V_Pos 28U |
APSR: V Position
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
| #define APSR_Z_Pos 30U |
APSR: Z Position
| #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) |
CONTROL: nPRIV Mask
| #define CONTROL_nPRIV_Pos 0U |
CONTROL: nPRIV Position
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
| #define xPSR_C_Pos 29U |
xPSR: C Position
| #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) |
xPSR: ICI/IT part 1 Mask
| #define xPSR_ICI_IT_1_Pos 10U |
xPSR: ICI/IT part 1 Position
| #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) |
xPSR: ICI/IT part 2 Mask
| #define xPSR_ICI_IT_2_Pos 25U |
xPSR: ICI/IT part 2 Position
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
| #define xPSR_N_Pos 31U |
xPSR: N Position
| #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) |
xPSR: Q Mask
| #define xPSR_Q_Pos 27U |
xPSR: Q Position
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
| #define xPSR_T_Pos 24U |
xPSR: T Position
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
| #define xPSR_V_Pos 28U |
xPSR: V Position
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
| #define xPSR_Z_Pos 30U |
xPSR: Z Position