
/*
 * Auto generated Run-Time-Environment Configuration File
 *      *** Do not modify ! ***
 *
 * Project: 'MG32F02U128_DemoBoard_MG04-04A' 
 * Target:  'Target 1' 
 */

#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H


/*
 * Define the Device Header File: 
 */
#define CMSIS_device_header "MG32x02z.h"

/* Megawin::ChipInit_Wizard:CSC:1.0.4 */
#define MG32x02z_ConfigerWizard_CSC
/* Megawin::Device:Startup:1.0.4 */
#define RTE_DEVICE_STARTUP_MG32F02U128    /* Device Startup for MG32F02U128 */
/* Megawin::Driver:Driver-All:1.0.1 */
#define IRQHandler_Driver_Level_
/* Megawin::IRQ_Handler:17. Enable SYS NVIC:Level-0 (High):1.0.0 */
#define MG32x02z_SYS_IRQ_
        #define MG32x02z_SYS_IRQ_Priority0
        #define MG32x02z_IRQ_Handler_
/* Megawin::IRQ_Handler:19. Enable EXINT0 NVIC:Level-0 (High):1.0.0 */
#define MG32x02z_EXINT0_IRQ_
        #define MG32x02z_EXINT0_IRQ_Priority0
        #define MG32x02z_IRQ_Handler_
/* Megawin::IRQ_Handler:22. Enable EXINT3 NVIC:Level-0 (High):1.0.0 */
#define MG32x02z_EXINT3_IRQ_
        #define MG32x02z_EXINT3_IRQ_Priority0
        #define MG32x02z_IRQ_Handler_
/* Megawin::IRQ_Handler:29. Enable TM10 NVIC:Level-0 (High):1.0.0 */
#define MG32x02z_TM10_IRQ_
        #define MG32x02z_TM10_IRQ_Priority0
        #define MG32x02z_IRQ_Handler_
/* Megawin::IRQ_Handler:31. Enable TM20 NVIC:Level-0 (High):1.0.0 */
#define MG32x02z_TM20_IRQ_
        #define MG32x02z_TM20_IRQ_Priority0
        #define MG32x02z_IRQ_Handler_
/* Megawin::IRQ_Handler:33. Enable TM3x NVIC:Level-0 (High):1.0.0 */
#define MG32x02z_TM3x_IRQ_
        #define MG32x02z_TM3x_IRQ_Priority0
        #define MG32x02z_IRQ_Handler_
/* Megawin::IRQ_Handler:38. Enable URT4x NVIC:Level-0 (High):1.0.0 */
#define MG32x02z_URT4x_IRQ_
        #define MG32x02z_URT4x_IRQ_Priority0
        #define MG32x02z_IRQ_Handler_
/* Megawin::Middleware:Middleware-All:1.0.0 */
#define IRQHandler_Middleware_Level_


#endif /* RTE_COMPONENTS_H */
