MG32L003 Standard Peripherals Firmware Library
Data Fields
OWIRE_TypeDef Struct Reference

Data Fields

__IOM uint32_t CR
 
__IOM uint32_t NFCR
 
__IOM uint32_t RSTCNT
 
__IOM uint32_t PRESCNT
 
__IOM uint32_t BITRATECNT
 
__IOM uint32_t DRVCNT
 
__IOM uint32_t RDSMPCNT
 
__IOM uint32_t RECCNT
 
__IOM uint32_t DATA
 
__IOM uint32_t CMD
 
__IOM uint32_t INTEN
 
__IOM uint32_t SR
 
__IOM uint32_t INTCLR
 

Field Documentation

◆ BITRATECNT

__IOM uint32_t BITRATECNT

One-wire bit rate design count register, Address offset: 0x010

◆ CMD

__IOM uint32_t CMD

One_wire bus operate command register, Address offset: 0x024

◆ CR

__IOM uint32_t CR

One-wire model control register, Address offset: 0x000

◆ DATA

__IOM uint32_t DATA

One_wire data register, Address offset: 0x020

◆ DRVCNT

__IOM uint32_t DRVCNT

One-wire main read/write pull0 drive time register, Address offset: 0x014

◆ INTCLR

__IOM uint32_t INTCLR

One-wire interrupt status clean register, Address offset: 0x030

◆ INTEN

__IOM uint32_t INTEN

One-wire interrupt enable register, Address offset: 0x028

◆ NFCR

__IOM uint32_t NFCR

One-wire input endpoint control register, Address offset: 0x004

◆ PRESCNT

__IOM uint32_t PRESCNT

One-wire device presence pulse count register, Address offset: 0x00C

◆ RDSMPCNT

__IOM uint32_t RDSMPCNT

One-wire main read sample time setting register, Address offset: 0x018

◆ RECCNT

__IOM uint32_t RECCNT

One-wire recover time count register, Address offset: 0x01C

◆ RSTCNT

__IOM uint32_t RSTCNT

One-wire master reset pulse count register, Address offset: 0x008

◆ SR

__IOM uint32_t SR

One-wire status register, Address offset: 0x02C


The documentation for this struct was generated from the following file: