|
#define | ADC_SOFTWARE_START (0x00000000U) |
|
#define | ADC_EXTTRIG1_TIM10 (ADC_CR1_TRIGS0_0) |
|
#define | ADC_EXTTRIG1_TIM11 (ADC_CR1_TRIGS0_1) |
|
#define | ADC_EXTTRIG1_TIM1 (ADC_CR1_TRIGS0_1 | ADC_CR1_TRIGS0_0) |
|
#define | ADC_EXTTRIG1_LPTIM (ADC_CR1_TRIGS0_2) |
|
#define | ADC_EXTTRIG1_TIM1_TRGO (ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_0) |
|
#define | ADC_EXTTRIG1_TIM2_TRGO (ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_1) |
|
#define | ADC_EXTTRIG1_TIM2_INT (ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_1 | ADC_CR1_TRIGS0_0) |
|
#define | ADC_EXTTRIG1_UART1_INT (ADC_CR1_TRIGS0_3) |
|
#define | ADC_EXTTRIG1_UART2_INT (ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_0) |
|
#define | ADC_EXTTRIG1_LPUART_INT (ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_1) |
|
#define | ADC_EXTTRIG1_VC0_INT (ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_1 | ADC_CR1_TRIGS0_0) |
|
#define | ADC_EXTTRIG1_NC (ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_2) |
|
#define | ADC_EXTTRIG1_RTC_INT (ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_0) |
|
#define | ADC_EXTTRIG1_PCA_INT (ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_1) |
|
#define | ADC_EXTTRIG1_SPI_INT (ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_1 | ADC_CR1_TRIGS0_0) |
|
#define | ADC_EXTTRIG1_PA1_INT (ADC_CR1_TRIGS0_4) |
|
#define | ADC_EXTTRIG1_PA2_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_0) |
|
#define | ADC_EXTTRIG1_PA3_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_1) |
|
#define | ADC_EXTTRIG1_PB4_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_1 | ADC_CR1_TRIGS0_0) |
|
#define | ADC_EXTTRIG1_PB5_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_2) |
|
#define | ADC_EXTTRIG1_PC3_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_0) |
|
#define | ADC_EXTTRIG1_PC4_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_0) |
|
#define | ADC_EXTTRIG1_PC5_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_1) |
|
#define | ADC_EXTTRIG1_PC6_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_3) |
|
#define | ADC_EXTTRIG1_PC7_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_0) |
|
#define | ADC_EXTTRIG1_PD1_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_1) |
|
#define | ADC_EXTTRIG1_PD2_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_1 | ADC_CR1_TRIGS0_0) |
|
#define | ADC_EXTTRIG1_PD3_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_2) |
|
#define | ADC_EXTTRIG1_PD4_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_0) |
|
#define | ADC_EXTTRIG1_PD5_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_1) |
|
#define | ADC_EXTTRIG1_PD6_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_1 | ADC_CR1_TRIGS0_0) |
|
#define | ADC_EXTTRIG1_PA4_INT (ADC_CR1_TRIGS0_5 | ADC_CR1_TRIGS0_0) |
|
#define | ADC_EXTTRIG1_PB0_INT (ADC_CR1_TRIGS0_5 | ADC_CR1_TRIGS0_1) |
|
#define | ADC_EXTTRIG1_PB1_INT (ADC_CR1_TRIGS0_5 | ADC_CR1_TRIGS0_1 | ADC_CR1_TRIGS0_0) |
|
#define | ADC_EXTTRIG1_PB2_INT (ADC_CR1_TRIGS0_5 | ADC_CR1_TRIGS0_2) |
|
#define | ADC_EXTTRIG1_PB3_INT (ADC_CR1_TRIGS0_5 | ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_0) |
|
#define | ADC_EXTTRIG1_PB6_INT (ADC_CR1_TRIGS0_5 | ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_1) |
|
#define | ADC_EXTTRIG1_PB7_INT (ADC_CR1_TRIGS0_5 | ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_1 | ADC_CR1_TRIGS0_0) |
|
#define | ADC_EXTTRIG1_PC0_INT (ADC_CR1_TRIGS0_5 | ADC_CR1_TRIGS0_3) |
|
#define | ADC_EXTTRIG1_PC1_INT (ADC_CR1_TRIGS0_5 | ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_0) |
|
#define | ADC_EXTTRIG1_PC2_INT (ADC_CR1_TRIGS0_5 | ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_1) |
|
#define | ADC_EXTTRIG1_PD0_INT (ADC_CR1_TRIGS0_5 | ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_1 | ADC_CR1_TRIGS0_0) |
|
#define | ADC_EXTTRIG1_PD7_INT (ADC_CR1_TRIGS0_5 | ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_2) |
|
#define | ADC_EXTTRIG1_MASK (0x1F | 0x10000) |
|
#define | IS_ADC_EXTRIG1(EXTRIG) ((((EXTRIG) & ADC_EXTTRIG1_MASK) != 0x0000) || ((EXTRIG) == ADC_SOFTWARE_START)) |
|