◆ CR0
ADC control register 0, Address offset: 0x000
◆ CR1
ADC control register 1, Address offset: 0x004
◆ CR2
ADC control register 2, Address offset: 0x008
◆ HT
Compare high threshold, Address offset: 0x034
◆ INTCLR
Interrupt clear register, Address offset: 0x048
◆ INTEN
Interrupt enable register, Address offset: 0x044
◆ LT
Compare low threshold, Address offset: 0x038
◆ MSKINTSR
Post-mask interrupt status register, Address offset: 0x050
◆ RAWINTSR
Pre-mask interrupt status register, Address offset: 0x04C
◆ RESERVED0
__IM uint32_t RESERVED0[2] |
◆ RESERVED1
__IM uint32_t RESERVED1[3] |
◆ RESULT
Channel result register, Address offset: 0x02C
◆ RESULT0
Channel 0 result register, Address offset: 0x00C
◆ RESULT1
Channel 1 result register, Address offset: 0x010
◆ RESULT10
Channel 10 result register, Address offset: 0x060
◆ RESULT11
Channel 11 result register, Address offset: 0x060
◆ RESULT12
Channel 12 result register, Address offset: 0x060
◆ RESULT13
Channel 13 result register, Address offset: 0x060
◆ RESULT14
Channel 14 result register, Address offset: 0x060
◆ RESULT15
Channel 15 result register, Address offset: 0x060
◆ RESULT2
Channel 2 result register, Address offset: 0x014
◆ RESULT3
Channel 3 result register, Address offset: 0x018
◆ RESULT4
Channel 4 result register, Address offset: 0x01C
◆ RESULT5
Channel 5 result register, Address offset: 0x020
◆ RESULT6
Channel 6 result register, Address offset: 0x024
◆ RESULT7
Channel 7 result register, Address offset: 0x028
◆ RESULT8
Channel 8 result register, Address offset: 0x060
◆ RESULT9
Channel 9 result register, Address offset: 0x060
◆ RESULT_ACC
__IOM uint32_t RESULT_ACC |
Channel result accumulate register, Address offset: 0x030
The documentation for this struct was generated from the following file: