MG32L003 Standard Peripherals Firmware Library
Data Fields
SYSCON_TypeDef Struct Reference

Data Fields

__IOM uint32_t CFGR0
 
__IOM uint32_t PORTINTCR
 
__IOM uint32_t PORTCR
 
__IOM uint32_t PCACR
 
__IOM uint32_t TIM1CR
 
__IOM uint32_t TIM2CR
 
__IM uint32_t RESERVED0 [14]
 
__IOM uint32_t UNLOCK
 

Field Documentation

◆ CFGR0

__IOM uint32_t CFGR0

SYSCON setting register 0, Address offset: 0x000

◆ PCACR

__IOM uint32_t PCACR

SYSCON pca capture channel source select register, Address offset: 0x00C

◆ PORTCR

__IOM uint32_t PORTCR

SYSCON port control register, Address offset: 0x008

◆ PORTINTCR

__IOM uint32_t PORTINTCR

SYSCON port interrupt mode setting register, Address offset: 0x004

◆ RESERVED0

__IM uint32_t RESERVED0[14]

Address offset: 0x018

◆ TIM1CR

__IOM uint32_t TIM1CR

SYSCON tim1 channel source select register, Address offset: 0x010

◆ TIM2CR

__IOM uint32_t TIM2CR

SYSCON tim2 channel source select register, Address offset: 0x014

◆ UNLOCK

__IOM uint32_t UNLOCK

SYSCON write enable register, Address offset: 0x050


The documentation for this struct was generated from the following file: