29 #ifndef __MG32L003_H__ 30 #define __MG32L003_H__ 37 #if !defined(MG32L003Fx) && !defined(MG32L003Kx) 38 #error "MG32L003Fx or MG32L003Kx must be selected" 41 #if (defined(MG32L003Fx) + defined(MG32L003Kx)) > 1 42 #error "Only one chip model can be selected, MG32L003Fx or MG32L003Kx" 52 #if !defined HSE_VALUE 53 #define HSE_VALUE (24000000) 63 #if !defined LSE_VALUE 64 #define LSE_VALUE (32768) 74 #if !defined HSI_VALUE 75 #define HSI_VALUE (24000000) 85 #if !defined LSI_VALUE 86 #define LSI_VALUE (32768) 94 NonMaskableInt_IRQn = -14,
138 #if defined (__CC_ARM) 141 #elif defined (__ICCARM__) 142 #pragma language=extended 143 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 144 #pragma clang diagnostic push 145 #pragma clang diagnostic ignored "-Wc11-extensions" 146 #pragma clang diagnostic ignored "-Wreserved-id-macro" 147 #elif defined (__GNUC__) 149 #elif defined (__TMS470__) 151 #elif defined (__TASKING__) 153 #elif defined (__CSMC__) 156 #warning Not supported compiler type 161 #define __CM0PLUS_REV 0x0001U 162 #define __MPU_PRESENT 0U 163 #define __VTOR_PRESENT 1U 164 #define __NVIC_PRIO_BITS 2U 165 #define __Vendor_SysTickConfig 0U 168 #include "system_mg32l003.h" 171 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
173 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
175 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) 177 typedef enum {INACTIVE = 0, ACTIVE = !INACTIVE} SignalState;
179 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
199 __IOM uint32_t OUTCFG;
222 __IOM uint32_t RESULT0;
223 __IOM uint32_t RESULT1;
224 __IOM uint32_t RESULT2;
225 __IOM uint32_t RESULT3;
226 __IOM uint32_t RESULT4;
227 __IOM uint32_t RESULT5;
228 __IOM uint32_t RESULT6;
229 __IOM uint32_t RESULT7;
230 __IOM uint32_t RESULT;
231 __IOM uint32_t RESULT_ACC;
234 __IM uint32_t RESERVED0[2];
235 __IOM uint32_t INTEN;
236 __IOM uint32_t INTCLR;
237 __IOM uint32_t RAWINTSR;
238 __IOM uint32_t MSKINTSR;
239 __IM uint32_t RESERVED1[3];
240 __IOM uint32_t RESULT8;
241 __IOM uint32_t RESULT9;
242 __IOM uint32_t RESULT10;
243 __IOM uint32_t RESULT11;
244 __IOM uint32_t RESULT12;
245 __IOM uint32_t RESULT13;
246 __IOM uint32_t RESULT14;
247 __IOM uint32_t RESULT15;
257 __IOM uint32_t CLKCR;
260 __IOM uint32_t ALM1TIME;
261 __IOM uint32_t ALM1DATE;
262 __IOM uint32_t ALM2PRD;
263 __IOM uint32_t RCLKTRIM;
265 __IOM uint32_t INTCLR;
276 __IOM uint32_t REFCON;
277 __IOM uint32_t REFCNT;
278 __IOM uint32_t CALCNT;
281 __IOM uint32_t CALCON;
292 __IOM uint32_t RSTCNT;
293 __IOM uint32_t PRESCNT;
294 __IOM uint32_t BITRATECNT;
295 __IOM uint32_t DRVCNT;
296 __IOM uint32_t RDSMPCNT;
297 __IOM uint32_t RECCNT;
300 __IOM uint32_t INTEN;
302 __IOM uint32_t INTCLR;
327 __IOM uint32_t TIMRUN;
328 __IOM uint32_t BAUDCR;
339 __IOM uint32_t SADDR;
340 __IOM uint32_t SADEN;
341 __IOM uint32_t INTSR;
342 __IOM uint32_t INTCLR;
343 __IOM uint32_t BAUDCR;
354 __IOM uint32_t SADDR;
355 __IOM uint32_t SADEN;
356 __IOM uint32_t INTSR;
357 __IOM uint32_t INTCLR;
358 __IOM uint32_t BAUDCR;
359 __IOM uint32_t IRDACR;
368 __IOM uint32_t RLOAD;
370 __IOM uint32_t INTEN;
372 __IOM uint32_t INTCLR;
373 __IOM uint32_t CNTVAL;
382 __IOM uint32_t CMDCR;
384 __IOM uint32_t RLOAD;
385 __IOM uint32_t CNTVAL;
387 __IOM uint32_t INTCLR;
388 __IOM uint32_t UNLOCK;
407 __IOM uint32_t RLOAD;
409 __IOM uint32_t INTCLR;
418 __IOM uint32_t CNTVAL;
421 __IOM uint32_t INTSR;
422 __IOM uint32_t INTCLR;
423 __IOM uint32_t BGLOAD;
435 __IOM uint32_t RAWINTSR;
436 __IOM uint32_t MSKINTSR;
437 __IOM uint32_t INTCLR;
438 __IOM uint32_t BGLOAD;
450 __IOM uint32_t INTCLR;
451 __IOM uint32_t CCAPM0;
452 __IOM uint32_t CCAPM1;
453 __IOM uint32_t CCAPM2;
454 __IOM uint32_t CCAPM3;
455 __IOM uint32_t CCAPM4;
456 __IM uint32_t RESERVED0[3];
457 __IOM uint32_t CCAP0L;
458 __IOM uint32_t CCAP0H;
459 __IOM uint32_t CCAP1L;
460 __IOM uint32_t CCAP1H;
461 __IOM uint32_t CCAP2L;
462 __IOM uint32_t CCAP2H;
463 __IOM uint32_t CCAP3L;
464 __IOM uint32_t CCAP3H;
465 __IOM uint32_t CCAP4L;
466 __IOM uint32_t CCAP4H;
467 __IOM uint32_t CCAPO;
469 __IOM uint32_t CCAP0;
470 __IOM uint32_t CCAP1;
471 __IOM uint32_t CCAP2;
472 __IOM uint32_t CCAP3;
473 __IOM uint32_t CCAP4;
488 __IOM uint32_t CCMR1;
489 __IOM uint32_t CCMR2;
508 __IM uint32_t RESERVED0;
509 __IOM uint32_t RESULT;
521 __IOM uint32_t BYPASS;
522 __IOM uint32_t SLOCK0;
523 __IOM uint32_t SLOCK1;
524 __IOM uint32_t ISPCON;
533 __IOM uint32_t DIRCR;
534 __IOM uint32_t OTYPER;
537 __IOM uint32_t INTEN;
538 __IOM uint32_t RAWINTST;
539 __IOM uint32_t MSKINTSR;
540 __IOM uint32_t INTCLR;
541 __IOM uint32_t INTTYPCR;
542 __IOM uint32_t INTPOLCR;
543 __IOM uint32_t INTANY;
544 __IOM uint32_t ODSET;
545 __IOM uint32_t ODCLR;
546 __IOM uint32_t INDBEN;
547 __IOM uint32_t DBCLKCR;
548 __IOM uint32_t PUPDR;
549 __IOM uint32_t SLEWCR;
550 __IOM uint32_t DRVCR;
560 __IOM uint32_t CFGR0;
561 __IOM uint32_t PORTINTCR;
562 __IOM uint32_t PORTCR;
563 __IOM uint32_t PCACR;
564 __IOM uint32_t TIM1CR;
565 __IOM uint32_t TIM2CR;
566 __IM uint32_t RESERVED0[14];
567 __IOM uint32_t UNLOCK;
576 __IOM uint32_t HCLKDIV;
577 __IOM uint32_t PCLKDIV;
578 __IOM uint32_t HCLKEN;
579 __IOM uint32_t PCLKEN;
580 __IOM uint32_t MCOCR;
581 __IM uint32_t RESERVED0;
582 __IOM uint32_t RSTCR;
583 __IOM uint32_t RSTSR;
584 __IOM uint32_t SYSCLKCR;
585 __IOM uint32_t SYSCLKSEL;
586 __IOM uint32_t HSICR;
587 __IOM uint32_t HSECR;
588 __IOM uint32_t LSICR;
589 __IOM uint32_t LSECR;
590 __IOM uint32_t IRQLATENCY;
591 __IOM uint32_t STICKCR;
592 __IOM uint32_t SWDIOCR;
593 __IOM uint32_t PERIRST;
594 __IOM uint32_t RTCRST;
595 __IM uint32_t RESERVED1[5];
596 __IOM uint32_t UNLOCK;
597 __IOM uint32_t RESERVED2[203];
598 __IOM uint32_t HSISTABCR;
599 __IOM uint32_t HSITC;
600 __IOM uint32_t LSITC;
609 __IOM uint32_t APBFZ;
616 #if defined (__CC_ARM) 618 #elif defined (__ICCARM__) 620 #elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) 621 #pragma clang diagnostic pop 622 #elif defined (__GNUC__) 624 #elif defined (__TMS470__) 626 #elif defined (__TASKING__) 627 #pragma warning restore 628 #elif defined (__CSMC__) 631 #warning Not supported compiler type 639 #define FLASH_MEMORY_BASE ((uint32_t)0x00000000UL) 640 #define SRAM_MEMORY_BASE ((uint32_t)0x20000000UL) 641 #define PERIPH_BASE ((uint32_t)0x40000000UL) 642 #define UID_BASE ((uint32_t)0x180000F0UL) 644 #define SCR_BASE ((uint32_t)0xE000ED10UL) 646 #define APBPERIPH_BASE (PERIPH_BASE + 0x00000UL) 647 #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000UL) 649 #define RCC_BASE (AHBPERIPH_BASE + 0x0000) // 4002_0000 650 #define FLASH_BASE (AHBPERIPH_BASE + 0x0400) // 4002_0400 651 #define CRC_BASE (AHBPERIPH_BASE + 0x0800) // 4002_0800 652 #define GPIOA_BASE (AHBPERIPH_BASE + 0x1000) // 4002_1000 653 #define GPIOB_BASE (AHBPERIPH_BASE + 0x1400) // 4002_1400 654 #define GPIOC_BASE (AHBPERIPH_BASE + 0x1800) // 4002_1800 655 #define GPIOD_BASE (AHBPERIPH_BASE + 0x1C00) // 4002_1C00 657 #define UART1_BASE (APBPERIPH_BASE + 0x0000) // 4000_0000 658 #define UART2_BASE (APBPERIPH_BASE + 0x0400) // 4000_0400 659 #define SPI_BASE (APBPERIPH_BASE + 0x0800) // 4000_0800 660 #define I2C_BASE (APBPERIPH_BASE + 0x0C00) // 4000_0C00 661 #define TIM1_BASE (APBPERIPH_BASE + 0x1000) // 4000_1000 662 #define PCA_BASE (APBPERIPH_BASE + 0x1400) // 4000_1400 663 #define TIM10_BASE (APBPERIPH_BASE + 0x1800) // 4000_1800 664 #define TIM11_BASE (APBPERIPH_BASE + 0x1900) // 4000_1900 665 #define SYSCON_BASE (APBPERIPH_BASE + 0x1C00) // 4000_1C00 666 #define WWDG_BASE (APBPERIPH_BASE + 0x2000) // 4000_2000 667 #define IWDG_BASE (APBPERIPH_BASE + 0x2400) // 4000_2400 668 #define AWK_BASE (APBPERIPH_BASE + 0x2800) // 4000_2800 669 #define ADC_BASE (APBPERIPH_BASE + 0x2C00) // 4000_2C00 670 #define RTC_BASE (APBPERIPH_BASE + 0x3000) // 4000_3000 671 #define CLKTRIM_BASE (APBPERIPH_BASE + 0x3400) // 4000_3400 672 #define OWIRE_BASE (APBPERIPH_BASE + 0x3800) // 4000_3800 673 #define TIM2_BASE (APBPERIPH_BASE + 0x3C00) // 4000_3C00 674 #define LVD_BASE (APBPERIPH_BASE + 0x4000) // 4000_4000 675 #define VCMP_BASE (APBPERIPH_BASE + 0x4080) // 4000_4080 676 #define LPTIM_BASE (APBPERIPH_BASE + 0x4400) // 4000_4400 677 #define BEEP_BASE (APBPERIPH_BASE + 0x4800) // 4000_4800 678 #define DBG_BASE (APBPERIPH_BASE + 0x4C00) // 4000_4C00 679 #define LPUART_BASE (APBPERIPH_BASE + 0x5000) // 4000_5000 686 #define VCMP (( VCMP_TypeDef*) VCMP_BASE) 687 #define LVD (( LVD_TypeDef*) LVD_BASE) 688 #define ADC (( ADC_TypeDef*) ADC_BASE) 689 #define RTC (( RTC_TypeDef*) RTC_BASE) 690 #define CLKTRIM (( CLKTRIM_TypeDef*) CLKTRIM_BASE) 691 #define OWIRE (( OWIRE_TypeDef*) OWIRE_BASE) 692 #define SPI (( SPI_TypeDef*) SPI_BASE) 693 #define I2C (( I2C_TypeDef*) I2C_BASE) 694 #define LPUART (( LPUART_TypeDef*) LPUART_BASE) 695 #define UART1 (( UART_TypeDef*) UART1_BASE) 696 #define UART2 (( UART_TypeDef*) UART2_BASE) 697 #define WWDG (( WWDG_TypeDef*) WWDG_BASE) 698 #define IWDG (( IWDG_TypeDef*) IWDG_BASE) 699 #define BEEP (( BEEP_TypeDef*) BEEP_BASE) 700 #define AWK (( AWK_TypeDef*) AWK_BASE) 701 #define LPTIM (( LPTIM_TypeDef*) LPTIM_BASE) 702 #define TIM10 (( BASETIM_TypeDef*) TIM10_BASE) 703 #define TIM11 (( BASETIM_TypeDef*) TIM11_BASE) 704 #define PCA (( PCA_TypeDef*) PCA_BASE) 705 #define TIM1 (( TIM_TypeDef*) TIM1_BASE) 706 #define TIM2 (( TIM_TypeDef*) TIM2_BASE) 707 #define CRC (( CRC_TypeDef*) CRC_BASE) 708 #define FLASH (( FLASH_TypeDef*) FLASH_BASE) 709 #define GPIOA (( GPIO_TypeDef*) GPIOA_BASE) 710 #define GPIOB (( GPIO_TypeDef*) GPIOB_BASE) 711 #define GPIOC (( GPIO_TypeDef*) GPIOC_BASE) 712 #define GPIOD (( GPIO_TypeDef*) GPIOD_BASE) 713 #define SYSCON (( SYSCON_TypeDef*) SYSCON_BASE) 714 #define RCC (( RCC_TypeDef*) RCC_BASE) 715 #define DBG (( DBG_TypeDef *) DBG_BASE) 724 #define DBG_APBFZ_TIM10DBGSTOP_Pos (0UL) 725 #define DBG_APBFZ_TIM10DBGSTOP_Msk (0x1UL) 726 #define DBG_APBFZ_TIM11DBGSTOP_Pos (1UL) 727 #define DBG_APBFZ_TIM11DBGSTOP_Msk (0x1UL) 728 #define DBG_APBFZ_LPTIMDBGSTOP_Pos (2UL) 729 #define DBG_APBFZ_LPTIMDBGSTOP_Msk (0x1UL) 730 #define DBG_APBFZ_PCADBGSTOP_Pos (4UL) 731 #define DBG_APBFZ_PCADBGSTOP_Msk (0x1UL) 732 #define DBG_APBFZ_TIM1DBGSTOP_Pos (5UL) 733 #define DBG_APBFZ_TIM1DBGSTOP_Msk (0x1UL) 734 #define DBG_APBFZ_RTCDBGSTOP_Pos (6UL) 735 #define DBG_APBFZ_RTCDBGSTOP_Msk (0x1UL) 736 #define DBG_APBFZ_BEEPDBGSTOP_Pos (8UL) 737 #define DBG_APBFZ_BEEPDBGSTOP_Msk (0x1UL) 738 #define DBG_APBFZ_IWDGDBGSTOP_Pos (9UL) 739 #define DBG_APBFZ_IWDGDBGSTOP_Msk (0x1UL) 740 #define DBG_APBFZ_WWDGDBGSTOP_Pos (10UL) 741 #define DBG_APBFZ_WWDGDBGSTOP_Msk (0x1UL) 742 #define DBG_APBFZ_TIM2DBGSTOP_Pos (11UL) 743 #define DBG_APBFZ_TIM2DBGSTOP_Msk (0x1UL) 744 #define DBG_APBFZ_KEY_Pos (16UL) 745 #define DBG_APBFZ_KEY_Msk (0xFFUL) 753 #define VCMP_CR0_PINSEL_Pos (0UL) 754 #define VCMP_CR0_PINSEL_Msk (0x3UL) 755 #define VCMP_CR0_NINSEL_Pos (2UL) 756 #define VCMP_CR0_NINSEL_Msk (0xCUL) 757 #define VCMP_CR0_VCAPDIV_Pos (4UL) 758 #define VCMP_CR0_VCAPDIV_Msk (0x30UL) 759 #define VCMP_CR0_VCAPDIV_EN_Pos (6UL) 760 #define VCMP_CR0_VCAPDIV_EN_Msk (0x40UL) 761 #define VCMP_CR0_VCAPDIV_EN VCMP_CR0_VCAPDIV_EN_Msk 763 #define VCMP_CR1_VCEN_Pos (0UL) 764 #define VCMP_CR1_VCEN_Msk (0x1UL) 765 #define VCMP_CR1_VCEN VCMP_CR1_VCEN_Msk 766 #define VCMP_CR1_VCMP_FLTCLK_SEL_Pos (2UL) 767 #define VCMP_CR1_VCMP_FLTCLK_SEL_Msk (0xCUL) 768 #define VCMP_CR1_VCMP_FLTCLK_SEL VCMP_CR1_VCMP_FLTCLK_SEL_Msk 769 #define VCMP_CR1_FLTEN_Pos (8UL) 770 #define VCMP_CR1_FLTEN_Msk (0x100UL) 771 #define VCMP_CR1_FLTEN VCMP_CR1_FLTEN_Msk 772 #define VCMP_CR1_FALLINTEN_Pos (12UL) 773 #define VCMP_CR1_FALLINTEN_Msk (0x1000UL) 774 #define VCMP_CR1_FALLINTEN VCMP_CR1_FALLINTEN_Msk 775 #define VCMP_CR1_RISEINTEN_Pos (13UL) 776 #define VCMP_CR1_RISEINTEN_Msk (0x2000UL) 777 #define VCMP_CR1_RISEINTEN VCMP_CR1_RISEINTEN_Msk 778 #define VCMP_CR1_HIGHINTEN_Pos (14UL) 779 #define VCMP_CR1_HIGHINTEN_Msk (0x4000UL) 780 #define VCMP_CR1_HIGHINTEN VCMP_CR1_HIGHINTEN_Msk 781 #define VCMP_CR1_INT_EN_Pos (15UL) 782 #define VCMP_CR1_INT_EN_Msk (0x8000UL) 783 #define VCMP_CR1_INT_EN VCMP_CR1_INT_EN_Msk 784 #define VCMP_CR1_FLT_NUM_Pos (16UL) 785 #define VCMP_CR1_FLT_NUM_Msk (0xFFFF0000UL) 787 #define VCMP_OUTCFG_INV_TIMX_Pos (0UL) 788 #define VCMP_OUTCFG_INV_TIMX_Msk (0x1UL) 789 #define VCMP_OUTCFG_TIM10_EN_Pos (1UL) 790 #define VCMP_OUTCFG_TIM10_EN_Msk (0x2UL) 791 #define VCMP_OUTCFG_TIM11_EN_Pos (2UL) 792 #define VCMP_OUTCFG_TIM11_EN_Msk (0x4UL) 793 #define VCMP_OUTCFG_LPTIM_EN_Pos (4UL) 794 #define VCMP_OUTCFG_LPTIM_EN_Msk (0x10UL) 795 #define VCMP_OUTCFG_LPTIMEXT_EN_Pos (5UL) 796 #define VCMP_OUTCFG_LPTIMEXT_EN_Msk (0x20UL) 797 #define VCMP_OUTCFG_INV_PCA_Pos (6UL) 798 #define VCMP_OUTCFG_INV_PCA_Msk (0x40UL) 799 #define VCMP_OUTCFG_PCACAP0_EN_Pos (7UL) 800 #define VCMP_OUTCFG_PCACAP0_EN_Msk (0x80UL) 801 #define VCMP_OUTCFG_PCAECI_EN_Pos (8UL) 802 #define VCMP_OUTCFG_PCAECI_EN_Msk (0x100UL) 803 #define VCMP_OUTCFG_INV_TIM1CH1_Pos (9UL) 804 #define VCMP_OUTCFG_INV_TIM1CH1_Msk (0x200UL) 805 #define VCMP_OUTCFG_TIM1CH1_EN_Pos (10UL) 806 #define VCMP_OUTCFG_TIM1CH1_EN_Msk (0x400UL) 807 #define VCMP_OUTCFG_INV_TIM1CH2_Pos (11UL) 808 #define VCMP_OUTCFG_INV_TIM1CH2_Msk (0x800UL) 809 #define VCMP_OUTCFG_TIM1CH2_EN_Pos (12UL) 810 #define VCMP_OUTCFG_TIM1CH2_EN_Msk (0x1000UL) 811 #define VCMP_OUTCFG_INV_TIM1CH3_Pos (13UL) 812 #define VCMP_OUTCFG_INV_TIM1CH3_Msk (0x2000UL) 813 #define VCMP_OUTCFG_TIM1CH3_EN_Pos (14UL) 814 #define VCMP_OUTCFG_TIM1CH3_EN_Msk (0x4000UL) 815 #define VCMP_OUTCFG_INV_TIM1CH4_Pos (15UL) 816 #define VCMP_OUTCFG_INV_TIM1CH4_Msk (0x8000UL) 817 #define VCMP_OUTCFG_TIM1CH4_EN_Pos (16UL) 818 #define VCMP_OUTCFG_TIM1CH4_EN_Msk (0x10000UL) 819 #define VCMP_OUTCFG_TIM1BKE_Pos (17UL) 820 #define VCMP_OUTCFG_TIM1BKE_Msk (0x20000UL) 821 #define VCMP_OUTCFG_INV_PAD_Pos (18UL) 822 #define VCMP_OUTCFG_INV_PAD_Msk (0x40000UL) 824 #define VCMP_SR_INTF_Pos (0UL) 825 #define VCMP_SR_INTF_Msk (0x1UL) 826 #define VCMP_SR_INTF VCMP_SR_INTF_Msk 827 #define VCMP_SR_VCMP_FLOUT_Pos (1UL) 828 #define VCMP_SR_VCMP_FLOUT_Msk (0x2UL) 829 #define VCMP_SR_VCMP_FLOUT VCMP_SR_VCMP_FLOUT_Msk 837 #define LVD_CR_DIV_SEL_Pos (0UL) 838 #define LVD_CR_DIV_SEL_Msk (0xFUL) 839 #define LVD_CR_DIV_SEL LVD_CR_DIV_SEL_Msk 840 #define LVD_CR_DIV_SEL_0 (0x1 << LVD_CR_DIV_SEL_Pos) 841 #define LVD_CR_DIV_SEL_1 (0x2 << LVD_CR_DIV_SEL_Pos) 842 #define LVD_CR_DIV_SEL_2 (0x4 << LVD_CR_DIV_SEL_Pos) 843 #define LVD_CR_DIV_SEL_3 (0x8 << LVD_CR_DIV_SEL_Pos) 844 #define LVD_CR_LVDEN_Pos (5UL) 845 #define LVD_CR_LVDEN_Msk (0x20UL) 846 #define LVD_CR_LVDEN LVD_CR_LVDEN_Msk 847 #define LVD_CR_ACT_Pos (6UL) 848 #define LVD_CR_ACT_Msk (0x40UL) 849 #define LVD_CR_ACT LVD_CR_ACT_Msk 850 #define LVD_CR_FLTEN_Pos (7UL) 851 #define LVD_CR_FLTEN_Msk (0x80UL) 852 #define LVD_CR_FLTEN LVD_CR_FLTEN_Msk 853 #define LVD_CR_FLTCLK_SEL_Pos (8UL) 854 #define LVD_CR_FLTCLK_SEL_Msk (0x300UL) 855 #define LVD_CR_FLTCLK_SEL LVD_CR_FLTCLK_SEL_Msk 856 #define LVD_CR_FLTCLK_SEL_0 (0x1 << LVD_CR_FLTCLK_SEL_Pos) 857 #define LVD_CR_FLTCLK_SEL_1 (0x2 << LVD_CR_FLTCLK_SEL_Pos) 858 #define LVD_CR_FALLINTEN_Pos (12UL) 859 #define LVD_CR_FALLINTEN_Msk (0x1000UL) 860 #define LVD_CR_FALLINTEN LVD_CR_FALLINTEN_Msk 861 #define LVD_CR_RISEINTEN_Pos (13UL) 862 #define LVD_CR_RISEINTEN_Msk (0x2000UL) 863 #define LVD_CR_RISEINTEN LVD_CR_RISEINTEN_Msk 864 #define LVD_CR_HIGHINTEN_Pos (14UL) 865 #define LVD_CR_HIGHINTEN_Msk (0x4000UL) 866 #define LVD_CR_HIGHINTEN LVD_CR_HIGHINTEN_Msk 867 #define LVD_CR_INT_EN_Pos (15UL) 868 #define LVD_CR_INT_EN_Msk (0x8000UL) 869 #define LVD_CR_INT_EN LVD_CR_INT_EN_Msk 870 #define LVD_CR_FLT_NUM_Pos (16UL) 871 #define LVD_CR_FLT_NUM_Msk (0xFFFF0000UL) 872 #define LVD_CR_FLT_NUM LVD_CR_FLT_NUM_Msk 873 #define LVD_CR_ALL_Msk (0xFFFFF3EFUL) 875 #define LVD_SR_INTF_Pos (0UL) 876 #define LVD_SR_INTF_Msk (0x1UL) 877 #define LVD_SR_INTF LVD_SR_INTF_Msk 885 #define ADC_CR0_ADCEN_Pos (0UL) 886 #define ADC_CR0_ADCEN_Msk (0x1UL) 887 #define ADC_CR0_ADCEN ADC_CR0_ADCEN_Msk 888 #define ADC_CR0_START_Pos (1UL) 889 #define ADC_CR0_START_Msk (0x2UL) 890 #define ADC_CR0_START ADC_CR0_START_Msk 891 #define ADC_CR0_CLKSEL_Pos (4UL) 892 #define ADC_CR0_CLKSEL_Msk (0x70UL) 893 #define ADC_CR0_CLKSEL ADC_CR0_CLKSEL_Msk 894 #define ADC_CR0_CLKSEL_0 (0x1 << ADC_CR0_CLKSEL_Pos) 895 #define ADC_CR0_CLKSEL_1 (0x2 << ADC_CR0_CLKSEL_Pos) 896 #define ADC_CR0_CLKSEL_2 (0x4 << ADC_CR0_CLKSEL_Pos) 897 #define ADC_CR0_SEL_Pos (8UL) 898 #define ADC_CR0_SEL3_Pos (7UL) 899 #define ADC_CR0_SEL_Msk (0x700UL | 0x80UL) 900 #define ADC_CR0_SEL ADC_CR0_SEL_Msk 901 #define ADC_CR0_SEL_0 (0x1 << ADC_CR0_SEL_Pos) 902 #define ADC_CR0_SEL_1 (0x2 << ADC_CR0_SEL_Pos) 903 #define ADC_CR0_SEL_2 (0x4 << ADC_CR0_SEL_Pos) 904 #define ADC_CR0_SEL_3 (0x1 << ADC_CR0_SEL3_Pos) 905 #define ADC_CR0_SAM_Pos (11UL) 906 #define ADC_CR0_SAM_Msk (0x800UL) 907 #define ADC_CR0_SAM ADC_CR0_SAM_Msk 908 #define ADC_CR0_STATERST_Pos (15UL) 909 #define ADC_CR0_STATERST_Msk (0x8000UL) 910 #define ADC_CR0_STATERST ADC_CR0_STATERST_Msk 912 #define ADC_CR1_TRIGS0_Pos (0UL) 913 #define ADC_CR1_TRIGS0_Msk (0x1001FUL) 914 #define ADC_CR1_TRIGS0 ADC_CR1_TRIGS0_Msk 915 #define ADC_CR1_TRIGS0_0 (0x1 << ADC_CR1_TRIGS0_Pos) 916 #define ADC_CR1_TRIGS0_1 (0x2 << ADC_CR1_TRIGS0_Pos) 917 #define ADC_CR1_TRIGS0_2 (0x4 << ADC_CR1_TRIGS0_Pos) 918 #define ADC_CR1_TRIGS0_3 (0x8 << ADC_CR1_TRIGS0_Pos) 919 #define ADC_CR1_TRIGS0_4 (0x10 << ADC_CR1_TRIGS0_Pos) 920 #define ADC_CR1_TRIGS0_5 (0x1 << 16) 922 #define ADC_CR1_TRIGS1_Pos (5UL) 923 #define ADC_CR1_TRIGS1_Msk (0x203E0UL) 924 #define ADC_CR1_TRIGS1 ADC_CR1_TRIGS1_Msk 925 #define ADC_CR1_TRIGS1_0 (0x1 << ADC_CR1_TRIGS1_Pos) 926 #define ADC_CR1_TRIGS1_1 (0x2 << ADC_CR1_TRIGS1_Pos) 927 #define ADC_CR1_TRIGS1_2 (0x4 << ADC_CR1_TRIGS1_Pos) 928 #define ADC_CR1_TRIGS1_3 (0x8 << ADC_CR1_TRIGS1_Pos) 929 #define ADC_CR1_TRIGS1_4 (0x10 << ADC_CR1_TRIGS1_Pos) 930 #define ADC_CR1_TRIGS1_5 (0x1 << 17) 931 #define ADC_CR1_CT_Pos (10UL) 932 #define ADC_CR1_CT_Msk (0x400UL) 933 #define ADC_CR1_CT ADC_CR1_CT_Msk 934 #define ADC_CR1_RACC_EN_Pos (11UL) 935 #define ADC_CR1_RACC_EN_Msk (0x800UL) 936 #define ADC_CR1_RACC_EN ADC_CR1_RACC_EN_Msk 937 #define ADC_CR1_LTCMP_Pos (12UL) 938 #define ADC_CR1_LTCMP_Msk (0x1000UL) 939 #define ADC_CR1_LTCMP ADC_CR1_LTCMP_Msk 940 #define ADC_CR1_HTCMP_Pos (13UL) 941 #define ADC_CR1_HTCMP_Msk (0x2000UL) 942 #define ADC_CR1_HTCMP ADC_CR1_HTCMP_Msk 943 #define ADC_CR1_REGCMP_Pos (14UL) 944 #define ADC_CR1_REGCMP_Msk (0x4000UL) 945 #define ADC_CR1_REGCMP ADC_CR1_REGCMP_Msk 946 #define ADC_CR1_RACC_CLR_Pos (15UL) 947 #define ADC_CR1_RACC_CLR_Msk (0x8000UL) 948 #define ADC_CR1_RACC_CLR ADC_CR1_RACC_CLR_Msk 950 #define ADC_CR2_CHEN_Pos (0UL) 951 #define ADC_CR2_CH15_8EN_Pos (20UL) 952 #define ADC_CR2_CHEN_Msk (0xFFUL | (0xFF00000UL)) 954 #define ADC_CR2_CHEN ADC_CR2_CHEN_Msk 955 #define ADC_CR2_CHEN_0 (0x1 << ADC_CR2_CHEN_Pos) 956 #define ADC_CR2_CHEN_1 (0x2 << ADC_CR2_CHEN_Pos) 957 #define ADC_CR2_CHEN_2 (0x4 << ADC_CR2_CHEN_Pos) 958 #define ADC_CR2_CHEN_3 (0x8 << ADC_CR2_CHEN_Pos) 959 #define ADC_CR2_CHEN_4 (0x10 << ADC_CR2_CHEN_Pos) 960 #define ADC_CR2_CHEN_5 (0x20 << ADC_CR2_CHEN_Pos) 961 #define ADC_CR2_CHEN_6 (0x40 << ADC_CR2_CHEN_Pos) 962 #define ADC_CR2_CHEN_7 (0x80 << ADC_CR2_CHEN_Pos) 963 #define ADC_CR2_CHEN_8 (0x1 << ADC_CR2_CH15_8EN_Pos) 964 #define ADC_CR2_CHEN_9 (0x2 << ADC_CR2_CH15_8EN_Pos) 965 #define ADC_CR2_CHEN_10 (0x4 << ADC_CR2_CH15_8EN_Pos) 966 #define ADC_CR2_CHEN_11 (0x8 << ADC_CR2_CH15_8EN_Pos) 967 #define ADC_CR2_CHEN_12 (0x10 << ADC_CR2_CH15_8EN_Pos) 968 #define ADC_CR2_CHEN_13 (0x20 << ADC_CR2_CH15_8EN_Pos) 969 #define ADC_CR2_CHEN_14 (0x40 << ADC_CR2_CH15_8EN_Pos) 970 #define ADC_CR2_CHEN_15 (0x80 << ADC_CR2_CH15_8EN_Pos) 972 #define ADC_CR2_ADCCNT_Pos (8UL) 973 #define ADC_CR2_ADCCNT_Msk (0xFF00UL) 974 #define ADC_CR2_ADCCNT ADC_CR2_ADCCNT_Msk 975 #define ADC_CR2_CIRCLE_MODE_Pos (16UL) 976 #define ADC_CR2_CIRCLE_MODE_Msk (0x10000UL) 977 #define ADC_CR2_CIRCLE_MODE ADC_CR2_CIRCLE_MODE_Msk 979 #define ADC_RESULT0_Result0_Pos (0UL) 980 #define ADC_RESULT0_Result0_Msk (0xFFFUL) 982 #define ADC_RESULT1_Result1_Pos (0UL) 983 #define ADC_RESULT1_Result1_Msk (0xFFFFFFUL) 985 #define ADC_RESULT2_Result2_Pos (0UL) 986 #define ADC_RESULT2_Result2_Msk (0xFFFUL) 988 #define ADC_RESULT3_Result3_Pos (0UL) 989 #define ADC_RESULT3_Result3_Msk (0xFFFUL) 991 #define ADC_RESULT4_Result4_Pos (0UL) 992 #define ADC_RESULT4_Result4_Msk (0xFFFUL) 994 #define ADC_RESULT5_Result5_Pos (0UL) 995 #define ADC_RESULT5_Result5_Msk (0xFFFUL) 997 #define ADC_RESULT6_Result6_Pos (0UL) 998 #define ADC_RESULT6_Result6_Msk (0xFFFUL) 1000 #define ADC_RESULT7_Result7_Pos (0UL) 1001 #define ADC_RESULT7_Result7_Msk (0xFFFUL) 1003 #define ADC_RESULT8_Result8_Pos (0UL) 1004 #define ADC_RESULT8_Result8_Msk (0xFFFUL) 1006 #define ADC_RESULT9_Result9_Pos (0UL) 1007 #define ADC_RESULT9_Result9_Msk (0xFFFUL) 1009 #define ADC_RESULT10_Result10_Pos (0UL) 1010 #define ADC_RESULT10_Result10_Msk (0xFFFUL) 1012 #define ADC_RESULT11_Result11_Pos (0UL) 1013 #define ADC_RESULT11_Result11_Msk (0xFFFUL) 1015 #define ADC_RESULT12_Result12_Pos (0UL) 1016 #define ADC_RESULT12_Result12_Msk (0xFFFUL) 1018 #define ADC_RESULT13_Result13_Pos (0UL) 1019 #define ADC_RESULT13_Result13_Msk (0xFFFUL) 1021 #define ADC_RESULT14_Result14_Pos (0UL) 1022 #define ADC_RESULT14_Result14_Msk (0xFFFUL) 1024 #define ADC_RESULT15_Result15_Pos (0UL) 1025 #define ADC_RESULT15_Result15_Msk (0xFFFUL) 1027 #define ADC_RESULT_RESULT_Pos (0UL) 1028 #define ADC_RESULT_RESULT_Msk (0xFFFUL) 1030 #define ADC_RESULT_ACC_HT_Pos (0UL) 1031 #define ADC_RESULT_ACC_HT_Msk (0xFFFUL) 1033 #define ADC_HT_HT_Pos (0UL) 1034 #define ADC_HT_HT_Msk (0xFFFUL) 1036 #define ADC_LT_LT_Pos (0UL) 1037 #define ADC_LT_LT_Msk (0xFFFUL) 1039 #define ADC_INTEN_ADCXIEN_Pos (0UL) 1040 #define ADC_INTEN_ADC15_8XIEN_Pos (12UL) 1041 #define ADC_INTEN_ADCXIEN_Msk (0xFFUL | 0xFF000UL) 1042 #define ADC_INTEN_ADCXIEN ADC_INTEN_ADCXIEN_Msk 1043 #define ADC_INTEN_ADCXIEN_0 (0x1 << ADC_INTEN_ADCXIEN_Pos) 1044 #define ADC_INTEN_ADCXIEN_1 (0x2 << ADC_INTEN_ADCXIEN_Pos) 1045 #define ADC_INTEN_ADCXIEN_2 (0x4 << ADC_INTEN_ADCXIEN_Pos) 1046 #define ADC_INTEN_ADCXIEN_3 (0x8 << ADC_INTEN_ADCXIEN_Pos) 1047 #define ADC_INTEN_ADCXIEN_4 (0x10 << ADC_INTEN_ADCXIEN_Pos) 1048 #define ADC_INTEN_ADCXIEN_5 (0x20 << ADC_INTEN_ADCXIEN_Pos) 1049 #define ADC_INTEN_ADCXIEN_6 (0x40 << ADC_INTEN_ADCXIEN_Pos) 1050 #define ADC_INTEN_ADCXIEN_7 (0x80 << ADC_INTEN_ADCXIEN_Pos) 1051 #define ADC_INTEN_ADCXIEN_8 (0x1 << ADC_INTEN_ADC15_8XIEN_Pos) 1052 #define ADC_INTEN_ADCXIEN_9 (0x2 << ADC_INTEN_ADC15_8XIEN_Pos) 1053 #define ADC_INTEN_ADCXIEN_10 (0x4 << ADC_INTEN_ADC15_8XIEN_Pos) 1054 #define ADC_INTEN_ADCXIEN_11 (0x8 << ADC_INTEN_ADC15_8XIEN_Pos) 1055 #define ADC_INTEN_ADCXIEN_12 (0x10 << ADC_INTEN_ADC15_8XIEN_Pos) 1056 #define ADC_INTEN_ADCXIEN_13 (0x20 << ADC_INTEN_ADC15_8XIEN_Pos) 1057 #define ADC_INTEN_ADCXIEN_14 (0x40 << ADC_INTEN_ADC15_8XIEN_Pos) 1058 #define ADC_INTEN_ADCXIEN_15 (0x80 << ADC_INTEN_ADC15_8XIEN_Pos) 1060 #define ADC_INTEN_LLT_IEN_Pos (8UL) 1061 #define ADC_INTEN_LLT_IEN_Msk (0x100UL) 1062 #define ADC_INTEN_LLT_IEN ADC_INTEN_LLT_IEN_Msk 1063 #define ADC_INTEN_HHT_IEN_Pos (9UL) 1064 #define ADC_INTEN_HHT_IEN_Msk (0x200UL) 1065 #define ADC_INTEN_HHT_IEN ADC_INTEN_HHT_IEN_Msk 1066 #define ADC_INTEN_REG_IEN_Pos (10UL) 1067 #define ADC_INTEN_REG_IEN_Msk (0x400UL) 1068 #define ADC_INTEN_REG_IEN ADC_INTEN_REG_IEN_Msk 1069 #define ADC_INTEN_CONT_IEN_Pos (11UL) 1070 #define ADC_INTEN_CONT_IEN_Msk (0x800UL) 1071 #define ADC_INTEN_CONT_IEN ADC_INTEN_CONT_IEN_Msk 1072 #define ADC_INTEN_CONT_ALL (0xFFFUL) 1074 #define ADC_INTCLR_ADCICLR_Pos (0UL) 1075 #define ADC_INTCLR_ADC15_8ICLR_Pos (12UL) 1076 #define ADC_INTCLR_ADCICLR_Msk (0xFFUL | 0xFF000UL) 1077 #define ADC_INTCLR_ADCICLR ADC_INTCLR_ADCICLR_Msk 1078 #define ADC_INTCLR_ADCICLR_0 (0x1 << ADC_INTCLR_ADCICLR_Pos) 1079 #define ADC_INTCLR_ADCICLR_1 (0x2 << ADC_INTCLR_ADCICLR_Pos) 1080 #define ADC_INTCLR_ADCICLR_2 (0x4 << ADC_INTCLR_ADCICLR_Pos) 1081 #define ADC_INTCLR_ADCICLR_3 (0x8 << ADC_INTCLR_ADCICLR_Pos) 1082 #define ADC_INTCLR_ADCICLR_4 (0x10 << ADC_INTCLR_ADCICLR_Pos) 1083 #define ADC_INTCLR_ADCICLR_5 (0x20 << ADC_INTCLR_ADCICLR_Pos) 1084 #define ADC_INTCLR_ADCICLR_6 (0x40 << ADC_INTCLR_ADCICLR_Pos) 1085 #define ADC_INTCLR_ADCICLR_7 (0x80 << ADC_INTCLR_ADCICLR_Pos) 1086 #define ADC_INTCLR_ADCICLR_8 (0x1 << ADC_INTCLR_ADC15_8ICLR_Pos) 1087 #define ADC_INTCLR_ADCICLR_9 (0x2 << ADC_INTCLR_ADC15_8ICLR_Pos) 1088 #define ADC_INTCLR_ADCICLR_10 (0x4 << ADC_INTCLR_ADC15_8ICLR_Pos) 1089 #define ADC_INTCLR_ADCICLR_11 (0x8 << ADC_INTCLR_ADC15_8ICLR_Pos) 1090 #define ADC_INTCLR_ADCICLR_12 (0x10 << ADC_INTCLR_ADC15_8ICLR_Pos) 1091 #define ADC_INTCLR_ADCICLR_13 (0x20 << ADC_INTCLR_ADC15_8ICLR_Pos) 1092 #define ADC_INTCLR_ADCICLR_14 (0x40 << ADC_INTCLR_ADC15_8ICLR_Pos) 1093 #define ADC_INTCLR_ADCICLR_15 (0x80 << ADC_INTCLR_ADC15_8ICLR_Pos) 1095 #define ADC_INTCLR_LLT_INTC_Pos (8UL) 1096 #define ADC_INTCLR_LLT_INTC_Msk (0x100UL) 1097 #define ADC_INTCLR_LLT_INTC ADC_INTCLR_LLT_INTC_Msk 1098 #define ADC_INTCLR_HHT_INTC_Pos (9UL) 1099 #define ADC_INTCLR_HHT_INTC_Msk (0x200UL) 1100 #define ADC_INTCLR_HHT_INTC ADC_INTCLR_HHT_INTC_Msk 1101 #define ADC_INTCLR_REG_INTC_Pos (10UL) 1102 #define ADC_INTCLR_REG_INTC_Msk (0x400UL) 1103 #define ADC_INTCLR_REG_INTC ADC_INTCLR_REG_INTC_Msk 1104 #define ADC_INTCLR_CONT_INTC_Pos (11UL) 1105 #define ADC_INTCLR_CONT_INTC_Msk (0x800UL) 1106 #define ADC_INTCLR_CONT_INTC ADC_INTCLR_CONT_INTC_Msk 1108 #define ADC_RAWINTSR_ADCRIS_Pos (0UL) 1109 #define ADC_RAWINTSR_ADC15_8RIS_Pos (12UL) 1110 #define ADC_RAWINTSR_ADCRIS_Msk (0xFFUL | 0xFF000UL) 1111 #define ADC_RAWINTSR_ADCRIS ADC_RAWINTSR_ADCRIS_Msk 1112 #define ADC_RAWINTSR_ADCRIS_0 (0x1 << ADC_RAWINTSR_ADCRIS_Pos) 1113 #define ADC_RAWINTSR_ADCRIS_1 (0x2 << ADC_RAWINTSR_ADCRIS_Pos) 1114 #define ADC_RAWINTSR_ADCRIS_2 (0x4 << ADC_RAWINTSR_ADCRIS_Pos) 1115 #define ADC_RAWINTSR_ADCRIS_3 (0x8 << ADC_RAWINTSR_ADCRIS_Pos) 1116 #define ADC_RAWINTSR_ADCRIS_4 (0x10 << ADC_RAWINTSR_ADCRIS_Pos) 1117 #define ADC_RAWINTSR_ADCRIS_5 (0x20 << ADC_RAWINTSR_ADCRIS_Pos) 1118 #define ADC_RAWINTSR_ADCRIS_6 (0x40 << ADC_RAWINTSR_ADCRIS_Pos) 1119 #define ADC_RAWINTSR_ADCRIS_7 (0x80 << ADC_RAWINTSR_ADCRIS_Pos) 1120 #define ADC_RAWINTSR_ADCRIS_8 (0x1 << ADC_RAWINTSR_ADC15_8RIS_Pos) 1121 #define ADC_RAWINTSR_ADCRIS_9 (0x2 << ADC_RAWINTSR_ADC15_8RIS_Pos) 1122 #define ADC_RAWINTSR_ADCRIS_10 (0x4 << ADC_RAWINTSR_ADC15_8RIS_Pos) 1123 #define ADC_RAWINTSR_ADCRIS_11 (0x8 << ADC_RAWINTSR_ADC15_8RIS_Pos) 1124 #define ADC_RAWINTSR_ADCRIS_12 (0x10 << ADC_RAWINTSR_ADC15_8RIS_Pos) 1125 #define ADC_RAWINTSR_ADCRIS_13 (0x20 << ADC_RAWINTSR_ADC15_8RIS_Pos) 1126 #define ADC_RAWINTSR_ADCRIS_14 (0x40 << ADC_RAWINTSR_ADC15_8RIS_Pos) 1127 #define ADC_RAWINTSR_ADCRIS_15 (0x80 << ADC_RAWINTSR_ADC15_8RIS_Pos) 1129 #define ADC_RAWINTSR_LLT_INTF_Pos (8UL) 1130 #define ADC_RAWINTSR_LLT_INTF_Msk (0x100UL) 1131 #define ADC_RAWINTSR_LLT_INTF ADC_RAWINTSR_LLT_INTF_Msk 1132 #define ADC_RAWINTSR_HHT_INTF_Pos (9UL) 1133 #define ADC_RAWINTSR_HHT_INTF_Msk (0x200UL) 1134 #define ADC_RAWINTSR_HHT_INTF ADC_RAWINTSR_HHT_INTF_Msk 1135 #define ADC_RAWINTSR_REG_INTF_Pos (10UL) 1136 #define ADC_RAWINTSR_REG_INTF_Msk (0x400UL) 1137 #define ADC_RAWINTSR_REG_INTF ADC_RAWINTSR_REG_INTF_Msk 1138 #define ADC_RAWINTSR_CONT_INTF_Pos (11UL) 1139 #define ADC_RAWINTSR_CONT_INTF_Msk (0x800UL) 1140 #define ADC_RAWINTSR_CONT_INTF ADC_RAWINTSR_CONT_INTF_Msk 1142 #define ADC_MSKINTSR_ADCMIS_Pos (0UL) 1143 #define ADC_MSKINTSR_ADC15_8MIS_Pos (12UL) 1144 #define ADC_MSKINTSR_ADCMIS_Msk (0xFFUL | 0xFF000UL) 1145 #define ADC_MSKINTSR_ADCMIS ADC_MSKINTSR_ADCMIS_Msk 1146 #define ADC_MSKINTSR_ADCMIS_0 (0x1 << ADC_MSKINTSR_ADCMIS_Pos) 1147 #define ADC_MSKINTSR_ADCMIS_1 (0x2 << ADC_MSKINTSR_ADCMIS_Pos) 1148 #define ADC_MSKINTSR_ADCMIS_2 (0x4 << ADC_MSKINTSR_ADCMIS_Pos) 1149 #define ADC_MSKINTSR_ADCMIS_3 (0x8 << ADC_MSKINTSR_ADCMIS_Pos) 1150 #define ADC_MSKINTSR_ADCMIS_4 (0x10 << ADC_MSKINTSR_ADCMIS_Pos) 1151 #define ADC_MSKINTSR_ADCMIS_5 (0x20 << ADC_MSKINTSR_ADCMIS_Pos) 1152 #define ADC_MSKINTSR_ADCMIS_6 (0x40 << ADC_MSKINTSR_ADCMIS_Pos) 1153 #define ADC_MSKINTSR_ADCMIS_7 (0x80 << ADC_MSKINTSR_ADCMIS_Pos) 1154 #define ADC_MSKINTSR_ADCMIS_8 (0x1 << ADC_MSKINTSR_ADC15_8MIS_Pos) 1155 #define ADC_MSKINTSR_ADCMIS_9 (0x2 << ADC_MSKINTSR_ADC15_8MIS_Pos) 1156 #define ADC_MSKINTSR_ADCMIS_10 (0x4 << ADC_MSKINTSR_ADC15_8MIS_Pos) 1157 #define ADC_MSKINTSR_ADCMIS_11 (0x8 << ADC_MSKINTSR_ADC15_8MIS_Pos) 1158 #define ADC_MSKINTSR_ADCMIS_12 (0x10 << ADC_MSKINTSR_ADC15_8MIS_Pos) 1159 #define ADC_MSKINTSR_ADCMIS_13 (0x20 << ADC_MSKINTSR_ADC15_8MIS_Pos) 1160 #define ADC_MSKINTSR_ADCMIS_14 (0x40 << ADC_MSKINTSR_ADC15_8MIS_Pos) 1161 #define ADC_MSKINTSR_ADCMIS_15 (0x80 << ADC_MSKINTSR_ADC15_8MIS_Pos) 1163 #define ADC_MSKINTSR_LLT_MIF_Pos (8UL) 1164 #define ADC_MSKINTSR_LLT_MIF_Msk (0x100UL) 1165 #define ADC_MSKINTSR_LLT_MIF ADC_MSKINTSR_LLT_MIF_Msk 1166 #define ADC_MSKINTSR_HHT_MIF_Pos (9UL) 1167 #define ADC_MSKINTSR_HHT_MIF_Msk (0x200UL) 1168 #define ADC_MSKINTSR_HHT_MIF ADC_MSKINTSR_HHT_MIF_Msk 1169 #define ADC_MSKINTSR_REG_MIF_Pos (10UL) 1170 #define ADC_MSKINTSR_REG_MIF_Msk (0x400UL) 1171 #define ADC_MSKINTSR_REG_MIF ADC_MSKINTSR_REG_MIF_Msk 1172 #define ADC_MSKINTSR_CONT_MIF_Pos (11UL) 1173 #define ADC_MSKINTSR_CONT_MIF_Msk (0x800UL) 1174 #define ADC_MSKINTSR_CONT_MIF ADC_MSKINTSR_CONT_MIF_Msk 1182 #define RTC_CR_BYPSHAD_Pos (0UL) 1183 #define RTC_CR_BYPSHAD_Msk (0x1UL) 1184 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk 1185 #define RTC_CR_RTC1HZOE_Pos (1UL) 1186 #define RTC_CR_RTC1HZOE_Msk (0x2UL) 1187 #define RTC_CR_RTC1HZOE RTC_CR_RTC1HZOE_Msk 1188 #define RTC_CR_FMT_Pos (2UL) 1189 #define RTC_CR_FMT_Msk (0x4UL) 1190 #define RTC_CR_FMT RTC_CR_FMT_Msk 1191 #define RTC_CR_ALM1_INTEN_Pos (4UL) 1192 #define RTC_CR_ALM1_INTEN_Msk (0x10UL) 1193 #define RTC_CR_ALM1_INTEN RTC_CR_ALM1_INTEN_Msk 1194 #define RTC_CR_ALM2_INTEN_Pos (5UL) 1195 #define RTC_CR_ALM2_INTEN_Msk (0x20UL) 1196 #define RTC_CR_ALM2_INTEN RTC_CR_ALM2_INTEN_Msk 1197 #define RTC_CR_ALM1EN_Pos (6UL) 1198 #define RTC_CR_ALM1EN_Msk (0x40UL) 1199 #define RTC_CR_ALM1EN RTC_CR_ALM1EN_Msk 1200 #define RTC_CR_START_Pos (8UL) 1201 #define RTC_CR_START_Msk (0x100UL) 1202 #define RTC_CR_START RTC_CR_START_Msk 1204 #define RTC_CLKCR_HSEDIV_Pos (0UL) 1205 #define RTC_CLKCR_HSEDIV_Msk (0x3FFUL) 1206 #define RTC_CLKCR_HSEDIV RTC_CLKCR_HSEDIV_Msk 1207 #define RTC_CLKCR_RTCCKSEL_Pos (16UL) 1208 #define RTC_CLKCR_RTCCKSEL_Msk (0x30000UL) 1209 #define RTC_CLKCR_RTCCKEN_Pos (20UL) 1210 #define RTC_CLKCR_RTCCKEN_Msk (0x100000UL) 1211 #define RTC_CLKCR_RTCCKEN RTC_CLKCR_RTCCKEN_Msk 1213 #define RTC_TIME_SEC_Pos (0UL) 1214 #define RTC_TIME_SEC_Msk (0x7FUL) 1215 #define RTC_TIME_SEC RTC_TIME_SEC_Msk 1216 #define RTC_TIME_MIN_Pos (8UL) 1217 #define RTC_TIME_MIN_Msk (0x7F00UL) 1218 #define RTC_TIME_MIN RTC_TIME_MIN_Msk 1219 #define RTC_TIME_HOUR19_Pos (16UL) 1220 #define RTC_TIME_HOUR19_Msk (0x1F0000UL) 1221 #define RTC_TIME_HOUR19 RTC_TIME_HOUR19_Msk 1222 #define RTC_TIME_H20_PA_Pos (21UL) 1223 #define RTC_TIME_H20_PA_Msk (0x200000UL) 1224 #define RTC_TIME_H20_PA RTC_TIME_H20_PA_Msk 1225 #define RTC_TIME_WEEK_Pos (24UL) 1226 #define RTC_TIME_WEEK_Msk (0x7000000UL) 1227 #define RTC_TIME_WEEK RTC_TIME_WEEK_Msk 1229 #define RTC_DATE_DAY_Pos (0UL) 1230 #define RTC_DATE_DAY_Msk (0x3FUL) 1231 #define RTC_DATE_DAY RTC_DATE_DAY_Msk 1232 #define RTC_DATE_MONTH_Pos (8UL) 1233 #define RTC_DATE_MONTH_Msk (0x1F00UL) 1234 #define RTC_DATE_MONTH RTC_DATE_MONTH_Msk 1235 #define RTC_DATE_CEN_Pos (15UL) 1236 #define RTC_DATE_CEN_Msk (0x8000UL) 1237 #define RTC_DATE_CEN RTC_DATE_CEN_Msk 1238 #define RTC_DATE_YEAR_Pos (16UL) 1239 #define RTC_DATE_YEAR_Msk (0xFF0000UL) 1240 #define RTC_DATE_YEAR RTC_DATE_YEAR_Msk 1242 #define RTC_ALM1TIME_ALSEC_Pos (0UL) 1243 #define RTC_ALM1TIME_ALSEC_Msk (0x7FUL) 1244 #define RTC_ALM1TIME_ALMIN_Pos (8UL) 1245 #define RTC_ALM1TIME_ALMIN_Msk (0x7F00UL) 1246 #define RTC_ALM1TIME_ALHOUR19_Pos (16UL) 1247 #define RTC_ALM1TIME_ALHOUR19_Msk (0x1F0000UL) 1248 #define RTC_ALM1TIME_ALH20_PA_Pos (21UL) 1249 #define RTC_ALM1TIME_ALH20_PA_Msk (0x200000UL) 1250 #define RTC_ALM1TIME_ALWEEK_Pos (24UL) 1251 #define RTC_ALM1TIME_ALWEEK_Msk (0x7000000UL) 1253 #define RTC_ALM1DATE_ALDAY_Pos (0UL) 1254 #define RTC_ALM1DATE_ALDAY_Msk (0x3FUL) 1255 #define RTC_ALM1DATE_ALMONTH_Pos (8UL) 1256 #define RTC_ALM1DATE_ALMONTH_Msk (0x1F00UL) 1257 #define RTC_ALM1DATE_ALCEN_Pos (15UL) 1258 #define RTC_ALM1DATE_ALCEN_Msk (0x8000UL) 1259 #define RTC_ALM1DATE_ALYEAR_Pos (16UL) 1260 #define RTC_ALM1DATE_ALYEAR_Msk (0xFF0000UL) 1261 #define RTC_ALM1DATE_ALYEAR RTC_ALM1DATE_ALYEAR_Msk 1262 #define RTC_ALM1DATE_ALMSECEN_Pos (24UL) 1263 #define RTC_ALM1DATE_ALMSECEN_Msk (0x1000000UL) 1264 #define RTC_ALM1DATE_ALMSECEN RTC_ALM1DATE_ALMSECEN_Msk 1265 #define RTC_ALM1DATE_ALMMINEN_Pos (25UL) 1266 #define RTC_ALM1DATE_ALMMINEN_Msk (0x2000000UL) 1267 #define RTC_ALM1DATE_ALMMINEN RTC_ALM1DATE_ALMMINEN_Msk 1268 #define RTC_ALM1DATE_ALMHOUREN_Pos (26UL) 1269 #define RTC_ALM1DATE_ALMHOUREN_Msk (0x4000000UL) 1270 #define RTC_ALM1DATE_ALMHOUREN RTC_ALM1DATE_ALMHOUREN_Msk 1271 #define RTC_ALM1DATE_ALMWEEKEN_Pos (27UL) 1272 #define RTC_ALM1DATE_ALMWEEKEN_Msk (0x8000000UL) 1273 #define RTC_ALM1DATE_ALMWEEKEN RTC_ALM1DATE_ALMWEEKEN_Msk 1274 #define RTC_ALM1DATE_ALMDAYEN_Pos (28UL) 1275 #define RTC_ALM1DATE_ALMDAYEN_Msk (0x10000000UL) 1276 #define RTC_ALM1DATE_ALMDAYEN RTC_ALM1DATE_ALMDAYEN_Msk 1277 #define RTC_ALM1DATE_ALMMONEN_Pos (29UL) 1278 #define RTC_ALM1DATE_ALMMONEN_Msk (0x20000000UL) 1279 #define RTC_ALM1DATE_ALMMONEN RTC_ALM1DATE_ALMMONEN_Msk 1280 #define RTC_ALM1DATE_ALMYEAREN_Pos (30UL) 1281 #define RTC_ALM1DATE_ALMYEAREN_Msk (0x40000000UL) 1282 #define RTC_ALM1DATE_ALMYEAREN RTC_ALM1DATE_ALMYEAREN_Msk 1284 #define RTC_ALM2PRD_ALM2PR_CNT_Pos (0UL) 1285 #define RTC_ALM2PRD_ALM2PR_CNT_Msk (0xFUL) 1287 #define RTC_CLKTRIM_TRIM_Pos (0UL) 1288 #define RTC_CLKTRIM_TRIM_Msk (0xFFUL) 1289 #define RTC_CLKTRIM_MODE_1_0_Pos (8UL) 1290 #define RTC_CLKTRIM_MODE_1_0_Msk (0x100UL) 1292 #define RTC_ISR_WAIT_Pos (0UL) 1293 #define RTC_ISR_WAIT_Msk (0x1UL) 1294 #define RTC_ISR_WAIT RTC_ISR_WAIT_Msk 1295 #define RTC_ISR_WAITF_Pos (1UL) 1296 #define RTC_ISR_WAITF_Msk (0x2UL) 1297 #define RTC_ISR_WAITF RTC_ISR_WAITF_Msk 1298 #define RTC_ISR_RSF_Pos (2UL) 1299 #define RTC_ISR_RSF_Msk (0x4UL) 1300 #define RTC_ISR_RSF RTC_ISR_RSF_Msk 1301 #define RTC_ISR_ALM1_F_Pos (4UL) 1302 #define RTC_ISR_ALM1_F_Msk (0x10UL) 1303 #define RTC_ISR_ALM1_F RTC_ISR_ALM1_F_Msk 1304 #define RTC_ISR_ALM2_F_Pos (5UL) 1305 #define RTC_ISR_ALM2_F_Msk (0x20UL) 1306 #define RTC_ISR_ALM2_F RTC_ISR_ALM2_F_Msk 1308 #define RTC_INTCLR_ALM1_CLR_Pos (4UL) 1309 #define RTC_INTCLR_ALM1_CLR_Msk (0x10UL) 1310 #define RTC_INTCLR_ALM1_CLR RTC_INTCLR_ALM1_CLR_Msk 1311 #define RTC_INTCLR_ALM2_CLR_Pos (5UL) 1312 #define RTC_INTCLR_ALM2_CLR_Msk (0x20UL) 1313 #define RTC_INTCLR_ALM2_CLR RTC_INTCLR_ALM2_CLR_Msk 1315 #define RTC_WPR_WPR_Pos (0UL) 1316 #define RTC_WPR_WPR_Msk (0xFFUL) 1324 #define CLKTRIM_CR_TRIM_START_Pos (0UL) 1325 #define CLKTRIM_CR_TRIM_START_Msk (0x1UL) 1326 #define CLKTRIM_CR_TRIM_START CLKTRIM_CR_TRIM_START_Msk 1327 #define CLKTRIM_CR_REFCLK_SEL_Pos (1UL) 1328 #define CLKTRIM_CR_REFCLK_SEL_Msk (0xEUL) 1329 #define CLKTRIM_CR_REFCLK_SEL CLKTRIM_CR_REFCLK_SEL_Msk 1330 #define CLKTRIM_CR_REFCLK_SEL_0 (0x1 << CLKTRIM_CR_REFCLK_SEL_Pos) 1331 #define CLKTRIM_CR_REFCLK_SEL_1 (0x2 << CLKTRIM_CR_REFCLK_SEL_Pos) 1332 #define CLKTRIM_CR_REFCLK_SEL_2 (0x4 << CLKTRIM_CR_REFCLK_SEL_Pos) 1333 #define CLKTRIM_CR_CALCLK_SEL_Pos (4UL) 1334 #define CLKTRIM_CR_CALCLK_SEL_Msk (0x30UL) 1335 #define CLKTRIM_CR_CALCLK_SEL CLKTRIM_CR_CALCLK_SEL_Msk 1336 #define CLKTRIM_CR_CALCLK_SEL_0 (0x1 << CLKTRIM_CR_CALCLK_SEL_Pos) 1337 #define CLKTRIM_CR_CALCLK_SEL_1 (0x2 << CLKTRIM_CR_CALCLK_SEL_Pos) 1338 #define CLKTRIM_CR_CALCLK_SEL_2 (0x4 << CLKTRIM_CR_CALCLK_SEL_Pos) 1339 #define CLKTRIM_CR_MON_EN_Pos (6UL) 1340 #define CLKTRIM_CR_MON_EN_Msk (0x40UL) 1341 #define CLKTRIM_CR_MON_EN CLKTRIM_CR_MON_EN_Msk 1342 #define CLKTRIM_CR_IE_Pos (7UL) 1343 #define CLKTRIM_CR_IE_Msk (0x80UL) 1344 #define CLKTRIM_CR_IE CLKTRIM_CR_IE_Msk 1345 #define CLKTRIM_CR_CLKEN_Pos (8UL) 1346 #define CLKTRIM_CR_CLKEN_Msk (0x100UL) 1347 #define CLKTRIM_CR_CLKEN CLKTRIM_CR_CLKEN_Msk 1348 #define CLKTRIM_CR_ALL_Msk (0x1FFUL) 1350 #define CLKTRIM_REFCON_RCNTVAL_Pos (0UL) 1351 #define CLKTRIM_REFCON_RCNTVAL_Msk (0xFFFFFFFFUL) 1352 #define CLKTRIM_REFCON_RCNTVAL CLKTRIM_REFCON_RCNTVAL_Msk 1354 #define CLKTRIM_REFCNT_REFCNT_Pos (0UL) 1355 #define CLKTRIM_REFCNT_REFCNT_Msk (0xFFFFFFFFUL) 1356 #define CLKTRIM_REFCNT_REFCNT CLKTRIM_REFCNT_REFCNT_Msk 1358 #define CLKTRIM_CALCNT_CALCNT_Pos (0UL) 1359 #define CLKTRIM_CALCNT_CALCNT_Msk (0xFFFFFFFFUL) 1360 #define CLKTRIM_CALCNT_CALCNT CLKTRIM_CALCNT_CALCNT_Msk 1362 #define CLKTRIM_IFR_STOP_Pos (0UL) 1363 #define CLKTRIM_IFR_STOP_Msk (0x1UL) 1364 #define CLKTRIM_IFR_STOP CLKTRIM_IFR_STOP_Msk 1365 #define CLKTRIM_IFR_CALCNT_OVF_Pos (1UL) 1366 #define CLKTRIM_IFR_CALCNT_OVF_Msk (0x2UL) 1367 #define CLKTRIM_IFR_CALCNT_OVF CLKTRIM_IFR_CALCNT_OVF_Msk 1368 #define CLKTRIM_IFR_LSE_FAULT_Pos (2UL) 1369 #define CLKTRIM_IFR_LSE_FAULT_Msk (0x4UL) 1370 #define CLKTRIM_IFR_LSE_FAULT CLKTRIM_IFR_LSE_FAULT_Msk 1371 #define CLKTRIM_IFR_HSE_FAULT_Pos (3UL) 1372 #define CLKTRIM_IFR_HSE_FAULT_Msk (0x8UL) 1373 #define CLKTRIM_IFR_HSE_FAULT CLKTRIM_IFR_HSE_FAULT_Msk 1375 #define CLKTRIM_ICLR_LSE_FAULT_CLR_Pos (2UL) 1376 #define CLKTRIM_ICLR_LSE_FAULT_CLR_Msk (0x4UL) 1377 #define CLKTRIM_ICLR_LSE_FAULT_CLR CLKTRIM_ICLR_LSE_FAULT_CLR_Msk 1378 #define CLKTRIM_ICLR_HSE_FAULT_CLR_Pos (3UL) 1379 #define CLKTRIM_ICLR_HSE_FAULT_CLR_Msk (0x8UL) 1380 #define CLKTRIM_ICLR_HSE_FAULT_CLR CLKTRIM_ICLR_HSE_FAULT_CLR_Msk 1382 #define CLKTRIM_CALCON_CALOVCNT_Pos (0UL) 1383 #define CLKTRIM_CALCON_CALOVCNT_Msk (0xFFFFUL) 1384 #define CLKTRIM_CALCON_CALOVCNT CLKTRIM_CALCON_CALOVCNT_Msk 1392 #define OWIRE_CR_CLKDIV_Pos (0UL) 1393 #define OWIRE_CR_CLKDIV_Msk (0x3UL) 1394 #define OWIRE_CR_SIZE_Pos (4UL) 1395 #define OWIRE_CR_SIZE_Msk (0x10UL) 1396 #define OWIRE_CR_EN_Pos (5UL) 1397 #define OWIRE_CR_EN_Msk (0x20UL) 1398 #define OWIRE_CR_MSBFIRST_Pos (6UL) 1399 #define OWIRE_CR_MSBFIRST_Msk (0x40UL) 1400 #define OWIRE_CR_RDMODE_Pos (7UL) 1401 #define OWIRE_CR_RDMODE_Msk (0x80UL) 1403 #define OWIRE_NFCR_NFDIV_Pos (0UL) 1404 #define OWIRE_NFCR_NFDIV_Msk (0x3UL) 1405 #define OWIRE_NFCR_NFEN_Pos (4UL) 1406 #define OWIRE_NFCR_NFEN_Msk (0x10UL) 1408 #define OWIRE_RSTCNT_RSTCNT_Pos (0UL) 1409 #define OWIRE_RSTCNT_RSTCNT_Msk (0xFFFFUL) 1411 #define OWIRE_PRESCNT_PRESCNT_Pos (0UL) 1412 #define OWIRE_PRESCNT_PRESCNT_Msk (0x1FFFUL) 1414 #define OWIRE_BITRATECNT_BITRATECNT_Pos (0UL) 1415 #define OWIRE_BITRATECNT_BITRATECNT_Msk (0xFFFUL) 1417 #define OWIRE_DRVCNT_DRVCNT_Pos (0UL) 1418 #define OWIRE_DRVCNT_DRVCNT_Msk (0x1FFUL) 1420 #define OWIRE_RDSMPCNT_RDSMPCNT_Pos (0UL) 1421 #define OWIRE_RDSMPCNT_RDSMPCNT_Msk (0x1FFUL) 1423 #define OWIRE_RECCNT_RECCNT_Pos (0UL) 1424 #define OWIRE_RECCNT_RECCNT_Msk (0x7FFUL) 1426 #define OWIRE_DATA_DRVCNT_Pos (0UL) 1427 #define OWIRE_DATA_DRVCNT_Msk (0xFFUL) 1429 #define OWIRE_CMD_CMD_Pos (0UL) 1430 #define OWIRE_CMD_CMD_Msk (0x3UL) 1432 #define OWIRE_INTEN_ACKERREN_Pos (0UL) 1433 #define OWIRE_INTEN_ACKERREN_Msk (0x1UL) 1434 #define OWIRE_INTEN_INITEN_Pos (1UL) 1435 #define OWIRE_INTEN_INITEN_Msk (0x2UL) 1436 #define OWIRE_INTEN_TXDONEEN_Pos (2UL) 1437 #define OWIRE_INTEN_TXDONEEN_Msk (0x4UL) 1438 #define OWIRE_INTEN_RXDONEEN_Pos (3UL) 1439 #define OWIRE_INTEN_RXDONEEN_Msk (0x8UL) 1441 #define OWIRE_SR_ACKERR_Pos (0UL) 1442 #define OWIRE_SR_ACKERR_Msk (0x1UL) 1443 #define OWIRE_SR_INITDONE_Pos (1UL) 1444 #define OWIRE_SR_INITDONE_Msk (0x2UL) 1445 #define OWIRE_SR_TXDONE_Pos (2UL) 1446 #define OWIRE_SR_TXDONE_Msk (0x4UL) 1447 #define OWIRE_SR_RXDONE_Pos (3UL) 1448 #define OWIRE_SR_RXDONE_Msk (0x8UL) 1450 #define OWIRE_INTCLR_ACKERRCLR_Pos (0UL) 1451 #define OWIRE_INTCLR_ACKERRCLR_Msk (0x1UL) 1452 #define OWIRE_INTCLR_INTDONCECLR_Pos (1UL) 1453 #define OWIRE_INTCLR_INTDONCECLR_Msk (0x2UL) 1454 #define OWIRE_INTCLR_TXDONECLR_Pos (2UL) 1455 #define OWIRE_INTCLR_TXDONECLR_Msk (0x4UL) 1456 #define OWIRE_INTCLR_RXDONECLR_Pos (3UL) 1457 #define OWIRE_INTCLR_RXDONECLR_Msk (0x8UL) 1465 #define SPI_CR_SPR0_Pos (0UL) 1466 #define SPI_CR_SPR0_Msk (0x1UL) 1467 #define SPI_CR_SPR0 SPI_CR_SPR0_Msk 1468 #define SPI_CR_SPR1_Pos (1UL) 1469 #define SPI_CR_SPR1_Msk (0x2UL) 1470 #define SPI_CR_SPR1 SPI_CR_SPR1_Msk 1471 #define SPI_CR_CPHA_Pos (2UL) 1472 #define SPI_CR_CPHA_Msk (0x4UL) 1473 #define SPI_CR_CPHA SPI_CR_CPHA_Msk 1474 #define SPI_CR_CPOL_Pos (3UL) 1475 #define SPI_CR_CPOL_Msk (0x8UL) 1476 #define SPI_CR_CPOL SPI_CR_CPOL_Msk 1477 #define SPI_CR_MSTR_Pos (4UL) 1478 #define SPI_CR_MSTR_Msk (0x10UL) 1479 #define SPI_CR_MSTR SPI_CR_MSTR_Msk 1480 #define SPI_CR_SPEN_Pos (6UL) 1481 #define SPI_CR_SPEN_Msk (0x40UL) 1482 #define SPI_CR_SPEN SPI_CR_SPEN_Msk 1483 #define SPI_CR_SPR2_Pos (7UL) 1484 #define SPI_CR_SPR2_Msk (0x80UL) 1485 #define SPI_CR_SPR2 SPI_CR_SPR2_Msk 1487 #define SPI_SSN_SSN_Pos (0UL) 1488 #define SPI_SSN_SSN_Msk (0x1UL) 1489 #define SPI_SSN_SSN SPI_SSN_SSN_Msk 1491 #define SPI_SR_MDF_Pos (4UL) 1492 #define SPI_SR_MDF_Msk (0x10UL) 1493 #define SPI_SR_MDF SPI_SR_MDF_Msk 1494 #define SPI_SR_SSERR_Pos (5UL) 1495 #define SPI_SR_SSERR_Msk (0x20UL) 1496 #define SPI_SR_SSERR SPI_SR_SSERR_Msk 1497 #define SPI_SR_WCOL_Pos (6UL) 1498 #define SPI_SR_WCOL_Msk (0x40UL) 1499 #define SPI_SR_WCOL SPI_SR_WCOL_Msk 1500 #define SPI_SR_SPIF_Pos (7UL) 1501 #define SPI_SR_SPIF_Msk (0x80UL) 1502 #define SPI_SR_SPIF SPI_SR_SPIF_Msk 1504 #define SPI_DATA_SPDATA_Pos (0UL) 1505 #define SPI_DATA_SPDATA_Msk (0xFFUL) 1513 #define I2C_CR_H1M_Pos (0UL) 1514 #define I2C_CR_H1M_Msk (0x1UL) 1515 #define I2C_CR_H1M I2C_CR_H1M_Msk 1516 #define I2C_CR_AA_Pos (2UL) 1517 #define I2C_CR_AA_Msk (0x4UL) 1518 #define I2C_CR_AA I2C_CR_AA_Msk 1519 #define I2C_CR_SI_Pos (3UL) 1520 #define I2C_CR_SI_Msk (0x8UL) 1521 #define I2C_CR_SI I2C_CR_SI_Msk 1522 #define I2C_CR_STO_Pos (4UL) 1523 #define I2C_CR_STO_Msk (0x10UL) 1524 #define I2C_CR_STO I2C_CR_STO_Msk 1525 #define I2C_CR_STA_Pos (5UL) 1526 #define I2C_CR_STA_Msk (0x20UL) 1527 #define I2C_CR_STA I2C_CR_STA_Msk 1528 #define I2C_CR_ENS_Pos (6UL) 1529 #define I2C_CR_ENS_Msk (0x40UL) 1530 #define I2C_CR_ENS I2C_CR_ENS_Msk 1532 #define I2C_DATA_DAT_Pos (0UL) 1533 #define I2C_DATA_DAT_Msk (0xFFUL) 1535 #define I2C_ADDR_GC_Pos (0UL) 1536 #define I2C_ADDR_GC_Msk (0x1UL) 1537 #define I2C_ADDR_GC I2C_ADDR_GC_Msk 1538 #define I2C_ADDR_I2CADR_Pos (1UL) 1539 #define I2C_ADDR_I2CADR_Msk (0xFEUL) 1541 #define I2C_SR_I2CSTA_Pos (0UL) 1542 #define I2C_SR_I2CSTA_Msk (0xFFUL) 1544 #define I2C_TIMRUN_TME_Pos (0UL) 1545 #define I2C_TIMRUN_TME_Msk (0x1UL) 1546 #define I2C_TIMRUN_TME I2C_TIMRUN_TME_Msk 1548 #define I2C_BAUDCR_TM_Pos (0UL) 1549 #define I2C_BAUDCR_TM_Msk (0xFFUL) 1550 #define I2C_BAUDCR_TM I2C_BAUDCR_TM_Msk 1558 #define LPUART_SBUF_SBUF_Pos (0UL) 1559 #define LPUART_SBUF_SBUF_Msk (0xFFUL) 1560 #define LPUART_SBUF_SBUF LPUART_SBUF_SBUF_Msk 1562 #define LPUART_SADDR_SADDR_Pos (0UL) 1563 #define LPUART_SADDR_SADDR_Msk (0xFFUL) 1564 #define LPUART_SADDR_SADDR LPUART_SADDR_SADDR_Msk 1566 #define LPUART_SADEN_SADEN_Pos (0UL) 1567 #define LPUART_SADEN_SADEN_Msk (0xFFUL) 1568 #define LPUART_SADEN_SADEN LPUART_SADEN_SADEN_Msk 1570 #define LPUART_INTSR_RI_Pos (0UL) 1571 #define LPUART_INTSR_RI_Msk (0x1UL) 1572 #define LPUART_INTSR_RI LPUART_INTSR_RI_Msk 1573 #define LPUART_INTSR_TI_Pos (1UL) 1574 #define LPUART_INTSR_TI_Msk (0x2UL) 1575 #define LPUART_INTSR_TI LPUART_INTSR_TI_Msk 1576 #define LPUART_INTSR_FE_Pos (2UL) 1577 #define LPUART_INTSR_FE_Msk (0x4UL) 1578 #define LPUART_INTSR_FE LPUART_INTSR_FE_Msk 1580 #define LPUART_SCON_RIEN_Pos (0UL) 1581 #define LPUART_SCON_RIEN_Msk (0x1UL) 1582 #define LPUART_SCON_RIEN LPUART_SCON_RIEN_Msk 1583 #define LPUART_SCON_TIEN_Pos (1UL) 1584 #define LPUART_SCON_TIEN_Msk (0x2UL) 1585 #define LPUART_SCON_TIEN LPUART_SCON_TIEN_Msk 1586 #define LPUART_SCON_RB8_Pos (2UL) 1587 #define LPUART_SCON_RB8_Msk (0x4UL) 1588 #define LPUART_SCON_RB8 LPUART_SCON_RB8_Msk 1589 #define LPUART_SCON_TB8_Pos (3UL) 1590 #define LPUART_SCON_TB8_Msk (0x8UL) 1591 #define LPUART_SCON_TB8 LPUART_SCON_TB8_Msk 1592 #define LPUART_SCON_REN_Pos (4UL) 1593 #define LPUART_SCON_REN_Msk (0x10UL) 1594 #define LPUART_SCON_REN LPUART_SCON_REN_Msk 1595 #define LPUART_SCON_SM2_Pos (5UL) 1596 #define LPUART_SCON_SM2_Msk (0x20UL) 1597 #define LPUART_SCON_SM2 LPUART_SCON_SM2_Msk 1598 #define LPUART_SCON_SM0_SM1_Pos (6UL) 1599 #define LPUART_SCON_SM0_SM1_Msk (0x40UL) 1600 #define LPUART_SCON_SM0_SM1 LPUART_SCON_SM0_SM1_Msk 1601 #define LPUART_SCON_SM0_SM1_1 (0x1 << LPUART_SCON_SM0_SM1_Pos) 1602 #define LPUART_SCON_SM0_SM1_0 (0x2 << LPUART_SCON_SM0_SM1_Pos) 1603 #define LPUART_SCON_TEEN_Pos (8UL) 1604 #define LPUART_SCON_TEEN_Msk (0x100UL) 1605 #define LPUART_SCON_TEEN LPUART_SCON_TEEN_Msk 1606 #define LPUART_SCON_DBAUD_Pos (9UL) 1607 #define LPUART_SCON_DBAUD_Msk (0x200UL) 1608 #define LPUART_SCON_DBAUD LPUART_SCON_DBAUD_Msk 1609 #define LPUART_SCON_LPMODE_Pos (10UL) 1610 #define LPUART_SCON_LPMODE_Msk (0x400UL) 1611 #define LPUART_SCON_LPMODE LPUART_SCON_LPMODE_Msk 1612 #define LPUART_SCON_SCLKSEL_Pos (11UL) 1613 #define LPUART_SCON_SCLKSEL_Msk (0x1800UL) 1614 #define LPUART_SCON_SCLKSEL LPUART_SCON_SCLKSEL_Msk 1615 #define LPUART_SCON_SCLKSEL_0 (0x1 << LPUART_SCON_SCLKSEL_Pos) 1616 #define LPUART_SCON_SCLKSEL_1 (0x2 << LPUART_SCON_SCLKSEL_Pos) 1617 #define LPUART_SCON_PRSC_Pos (13UL) 1618 #define LPUART_SCON_PRSC_Msk (0xE000UL) 1619 #define LPUART_SCON_PRSC LPUART_SCON_PRSC_Msk 1620 #define LPUART_SCON_PRSC_0 (0x1 << LPUART_SCON_PRSC_Pos) 1621 #define LPUART_SCON_PRSC_1 (0x2 << LPUART_SCON_PRSC_Pos) 1622 #define LPUART_SCON_PRSC_2 (0x4 << LPUART_SCON_PRSC_Pos) 1623 #define LPUART_SCON_EN_Pos (16UL) 1624 #define LPUART_SCON_EN_Msk (0x10000UL) 1625 #define LPUART_SCON_EN LPUART_SCON_EN_Msk 1627 #define LPUART_INTCLR_RICLR_Pos (0UL) 1628 #define LPUART_INTCLR_RICLR_Msk (0x1UL) 1629 #define LPUART_INTCLR_RICLR LPUART_INTCLR_RICLR_Msk 1630 #define LPUART_INTCLR_TICLR_Pos (1UL) 1631 #define LPUART_INTCLR_TICLR_Msk (0x2UL) 1632 #define LPUART_INTCLR_TICLR LPUART_INTCLR_TICLR_Msk 1633 #define LPUART_INTCLR_FECLR_Pos (2UL) 1634 #define LPUART_INTCLR_FECLR_Msk (0x4UL) 1635 #define LPUART_INTCLR_FECLR LPUART_INTCLR_FECLR_Msk 1637 #define LPUART_BAUDCR_BRG_Pos (0UL) 1638 #define LPUART_BAUDCR_BRG_Msk (0xFFFFUL) 1639 #define LPUART_BAUDCR_BRG LPUART_BAUDCR_BRG_Msk 1640 #define LPUART_BAUDCR_SELF_BRG_Pos (16UL) 1641 #define LPUART_BAUDCR_SELF_BRG_Msk (0x10000UL) 1642 #define LPUART_BAUDCR_SELF_BRG LPUART_BAUDCR_SELF_BRG_Msk 1650 #define UART_SCON_RIEN_Pos (0UL) 1651 #define UART_SCON_RIEN_Msk (0x1UL) 1652 #define UART_SCON_RIEN UART_SCON_RIEN_Msk 1653 #define UART_SCON_TIEN_Pos (1UL) 1654 #define UART_SCON_TIEN_Msk (0x2UL) 1655 #define UART_SCON_TIEN UART_SCON_TIEN_Msk 1656 #define UART_SCON_RB8_Pos (2UL) 1657 #define UART_SCON_RB8_Msk (0x4UL) 1658 #define UART_SCON_RB8 UART_SCON_RB8_Msk 1659 #define UART_SCON_TB8_Pos (3UL) 1660 #define UART_SCON_TB8_Msk (0x8UL) 1661 #define UART_SCON_TB8 UART_SCON_TB8_Msk 1662 #define UART_SCON_REN_Pos (4UL) 1663 #define UART_SCON_REN_Msk (0x10UL) 1664 #define UART_SCON_REN UART_SCON_REN_Msk 1665 #define UART_SCON_SM2_Pos (5UL) 1666 #define UART_SCON_SM2_Msk (0x20UL) 1667 #define UART_SCON_SM2 UART_SCON_SM2_Msk 1668 #define UART_SCON_SM0_SM1_Pos (6UL) 1669 #define UART_SCON_SM0_SM1_Msk (0xC0UL) 1670 #define UART_SCON_SM0_SM1 UART_SCON_SM0_SM1_Msk 1671 #define UART_SCON_FEEN_Pos (8UL) 1672 #define UART_SCON_FEEN_Msk (0x100UL) 1673 #define UART_SCON_FEEN UART_SCON_FEEN_Msk 1674 #define UART_SCON_DBAUD_Pos (9UL) 1675 #define UART_SCON_DBAUD_Msk (0x200UL) 1676 #define UART_SCON_DBAUD UART_SCON_DBAUD_Msk 1678 #define UART_SBUF_SBUF_Pos (0UL) 1679 #define UART_SBUF_SBUF_Msk (0xFFUL) 1680 #define UART_SBUF_SBUF UART_SBUF_SBUF_Msk 1682 #define UART_SADDR_SADDR_Pos (0UL) 1683 #define UART_SADDR_SADDR_Msk (0xFFUL) 1685 #define UART_SADEN_SADEN_Pos (0UL) 1686 #define UART_SADEN_SADEN_Msk (0xFFUL) 1688 #define UART_INTSR_RI_Pos (0UL) 1689 #define UART_INTSR_RI_Msk (0x1UL) 1690 #define UART_INTSR_RI UART_INTSR_RI_Msk 1691 #define UART_INTSR_TI_Pos (1UL) 1692 #define UART_INTSR_TI_Msk (0x2UL) 1693 #define UART_INTSR_TI UART_INTSR_TI_Msk 1694 #define UART_INTSR_FE_Pos (2UL) 1695 #define UART_INTSR_FE_Msk (0x4UL) 1696 #define UART_INTSR_FE UART_INTSR_FE_Msk 1698 #define UART_INTCLR_RICLR_Pos (0UL) 1699 #define UART_INTCLR_RICLR_Msk (0x1UL) 1700 #define UART_INTCLR_TICLR_Pos (1UL) 1701 #define UART_INTCLR_TICLR_Msk (0x2UL) 1702 #define UART_INTCLR_FECLR_Pos (2UL) 1703 #define UART_INTCLR_FECLR_Msk (0x4UL) 1705 #define UART_BAUDCR_BRG_Pos (0UL) 1706 #define UART_BAUDCR_BRG_Msk (0xFFFFUL) 1707 #define UART_BAUDCR_BRG UART_BAUDCR_BRG_Msk 1708 #define UART_BAUDCR_SELF_BRG_Pos (16UL) 1709 #define UART_BAUDCR_SELF_BRG_Msk (0x10000UL) 1710 #define UART_BAUDCR_SELF_BRG UART_BAUDCR_SELF_BRG_Msk 1711 #define UART_BAUDCR_NOREF_Pos (31UL) 1712 #define UART_BAUDCR_NOREF_Msk (0x80000000UL) 1714 #define UART_IRDACR_PSC_Pos (0UL) 1715 #define UART_IRDACR_PSC_Msk (0xFFUL) 1716 #define UART_IRDACR_IREN_Pos (8UL) 1717 #define UART_IRDACR_IREN_Msk (0x100UL) 1718 #define UART_IRDACR_IRTXINV_Pos (9UL) 1719 #define UART_IRDACR_IRTXINV_Msk (0x200UL) 1720 #define UART_IRDACR_IRRXINV_Pos (10UL) 1721 #define UART_IRDACR_IRRXINV_Msk (0x400UL) 1722 #define UART_IRDACR_IRLPMODE_Pos (11UL) 1723 #define UART_IRDACR_IRLPMODE_Msk (0x800UL) 1731 #define WWDG_RLOAD_RLOAD_Pos (0UL) 1732 #define WWDG_RLOAD_RLOAD_Msk (0xFFUL) 1733 #define WWDG_RLOAD_RLOAD WWDG_RLOAD_RLOAD_Msk 1735 #define WWDG_CR_WINCMP_Pos (0UL) 1736 #define WWDG_CR_WINCMP_Msk (0xFFUL) 1737 #define WWDG_CR_WINCMP WWDG_CR_WINCMP_Msk 1738 #define WWDG_CR_PRSC_Pos (8UL) 1739 #define WWDG_CR_PRSC_Msk (0xFFFFF00UL) 1740 #define WWDG_CR_PRSC WWDG_CR_PRSC_Msk 1741 #define WWDG_CR_WWDGEN_Pos (28UL) 1742 #define WWDG_CR_WWDGEN_Msk (0x10000000UL) 1743 #define WWDG_CR_WWDGEN WWDG_CR_WWDGEN_Msk 1745 #define WWDG_INTEN_WWDGIEN_Pos (0UL) 1746 #define WWDG_INTEN_WWDGIEN_Msk (0x1UL) 1747 #define WWDG_INTEN_WWDGIEN WWDG_INTEN_WWDGIEN_Msk 1749 #define WWDG_SR_WWDGIF_Pos (0UL) 1750 #define WWDG_SR_WWDGIF_Msk (0x1UL) 1751 #define WWDG_SR_WWDGIF WWDG_SR_WWDGIF_Msk 1753 #define WWDG_INTCLR_INTCLR_Pos (0UL) 1754 #define WWDG_INTCLR_INTCLR_Msk (0x1UL) 1755 #define WWDG_INTCLR_INTCLR WWDG_INTCLR_INTCLR_Msk 1757 #define WWDG_CNTVAL_WWDGCNT_Pos (0UL) 1758 #define WWDG_CNTVAL_WWDGCNT_Msk (0xFFUL) 1759 #define WWDG_CNTVAL_WWDGCNT WWDG_CNTVAL_WWDGCNT_Msk 1767 #define IWDG_CMDCR_CMD_Pos (0UL) 1768 #define IWDG_CMDCR_CMD_Msk (0xFFUL) 1770 #define IWDG_CFGR_IWDGMODE_Pos (0UL) 1771 #define IWDG_CFGR_IWDGMODE_Msk (0x1UL) 1772 #define IWDG_CFGR_IWDGMODE IWDG_CFGR_IWDGMODE_Msk 1773 #define IWDG_CFGR_IWDGINTMSK_Pos (1UL) 1774 #define IWDG_CFGR_IWDGINTMSK_Msk (0x2UL) 1775 #define IWDG_CFGR_IWDGINTMSK IWDG_CFGR_IWDGINTMSK_Msk 1776 #define IWDG_CFGR_IWDGRUNF_Pos (2UL) 1777 #define IWDG_CFGR_IWDGRUNF_Msk (0x4UL) 1779 #define IWDG_RLOAD_IWDGRLOAD_Pos (0UL) 1780 #define IWDG_RLOAD_IWDGRLOAD_Msk (0xFFFFFUL) 1781 #define IWDG_RLOAD_IWDGRLOAD IWDG_RLOAD_IWDGRLOAD_Msk 1783 #define IWDG_CNTVAL_IWDGCNT_Pos (0UL) 1784 #define IWDG_CNTVAL_IWDGCNT_Msk (0xFFFFFUL) 1785 #define IWDG_CNTVAL_IWDGCNT IWDG_CNTVAL_IWDGCNT_Msk 1787 #define IWDG_SR_IWDGOVF_Pos (0UL) 1788 #define IWDG_SR_IWDGOVF_Msk (0x1UL) 1790 #define IWDG_INTCLR_IWDGINTCLR_Pos (0UL) 1791 #define IWDG_INTCLR_IWDGINTCLR_Msk (0x1UL) 1793 #define IWDG_UNLOCK_IWDGREN_Pos (0UL) 1794 #define IWDG_UNLOCK_IWDGREN_Msk (0x1UL) 1802 #define BEEP_CSR_BEEPDIV_Pos (0UL) 1803 #define BEEP_CSR_BEEPDIV_Msk (0xFFFUL) 1804 #define BEEP_CSR_BEEPDIV BEEP_CSR_BEEPDIV_Msk 1805 #define BEEP_CSR_BEEPSEL_Pos (16UL) 1806 #define BEEP_CSR_BEEPSEL_Msk (0x30000UL) 1807 #define BEEP_CSR_BEEPSEL BEEP_CSR_BEEPSEL_Msk 1808 #define BEEP_CSR_BEEPSEL_0 (0x1 << BEEP_CSR_BEEPSEL_Pos) 1809 #define BEEP_CSR_BEEPSEL_1 (0x2 << BEEP_CSR_BEEPSEL_Pos) 1810 #define BEEP_CSR_BEEPEN_Pos (18UL) 1811 #define BEEP_CSR_BEEPEN_Msk (0x40000UL) 1812 #define BEEP_CSR_BEEPEN BEEP_CSR_BEEPEN_Msk 1813 #define BEEP_CSR_CLKSEL_Pos (20UL) 1814 #define BEEP_CSR_CLKSEL_Msk (0x300000UL) 1815 #define BEEP_CSR_CLKSEL BEEP_CSR_CLKSEL_Msk 1816 #define BEEP_CSR_CLKSEL_0 (0x1 << BEEP_CSR_CLKSEL_Pos) 1817 #define BEEP_CSR_CLKSEL_1 (0x2 << BEEP_CSR_CLKSEL_Pos) 1818 #define BEEP_CSR_CLKSEL_2 (0x4 << BEEP_CSR_CLKSEL_Pos) 1819 #define BEEP_CSR_ALL_Msk (BEEP_CSR_BEEPDIV_Msk | BEEP_CSR_BEEPSEL_Msk | BEEP_CSR_BEEPEN_Msk | BEEP_CSR_CLKSEL_Msk) 1827 #define AWK_CR_DIVSEL_Pos (0UL) 1828 #define AWK_CR_DIVSEL_Msk (0xFUL) 1829 #define AWK_CR_DIVSEL AWK_CR_DIVSEL_Msk 1830 #define AWK_CR_DIVSEL_0 (0x1 << AWK_CR_DIVSEL_Pos) 1831 #define AWK_CR_DIVSEL_1 (0x2 << AWK_CR_DIVSEL_Pos) 1832 #define AWK_CR_DIVSEL_2 (0x4 << AWK_CR_DIVSEL_Pos) 1833 #define AWK_CR_DIVSEL_3 (0x8 << AWK_CR_DIVSEL_Pos) 1834 #define AWK_CR_AWKEN_Pos (4UL) 1835 #define AWK_CR_AWKEN_Msk (0x10UL) 1836 #define AWK_CR_AWKEN AWK_CR_AWKEN_Msk 1837 #define AWK_CR_TCLKSEL_Pos (5UL) 1838 #define AWK_CR_TCLKSEL_Msk (0x60UL) 1839 #define AWK_CR_TCLKSEL AWK_CR_TCLKSEL_Msk 1840 #define AWK_CR_TCLKSEL_0 (0x1 << AWK_CR_TCLKSEL_Pos) 1841 #define AWK_CR_TCLKSEL_1 (0x2 << AWK_CR_TCLKSEL_Pos) 1842 #define AWK_CR_HXPRSC_Pos (8UL) 1843 #define AWK_CR_HXPRSC_Msk (0x7FFF00UL) 1844 #define AWK_CR_HXPRSC AWK_CR_HXPRSC_Msk 1846 #define AWK_RLOAD_RLDVAL_Pos (0UL) 1847 #define AWK_RLOAD_RLDVAL_Msk (0xFFUL) 1848 #define AWK_RLOAD_RLDVAL AWK_RLOAD_RLDVAL_Msk 1850 #define AWK_SR_AWUF_Pos (0UL) 1851 #define AWK_SR_AWUF_Msk (0x1UL) 1852 #define AWK_SR_AWUF AWK_SR_AWUF_Msk 1854 #define AWK_INTCLR_INTCLR_Pos (0UL) 1855 #define AWK_INTCLR_INTCLR_Msk (0x1UL) 1856 #define AWK_INTCLR_INTCLR AWK_INTCLR_INTCLR_Msk 1864 #define LPTIM_CNTVAL_LPT_CNT_Pos (0UL) 1865 #define LPTIM_CNTVAL_LPT_CNT_Msk (0x1UL) 1867 #define LPTIM_CR_TIM_RUN_Pos (0UL) 1868 #define LPTIM_CR_TIM_RUN_Msk (0x1UL) 1869 #define LPTIM_CR_TIM_RUN LPTIM_CR_TIM_RUN_Msk 1870 #define LPTIM_CR_MODE_Pos (1UL) 1871 #define LPTIM_CR_MODE_Msk (0x2UL) 1872 #define LPTIM_CR_MODE LPTIM_CR_MODE_Msk 1873 #define LPTIM_CR_CT_SEL_Pos (2UL) 1874 #define LPTIM_CR_CT_SEL_Msk (0x4UL) 1875 #define LPTIM_CR_CT_SEL LPTIM_CR_CT_SEL_Msk 1876 #define LPTIM_CR_TOG_EN_Pos (3UL) 1877 #define LPTIM_CR_TOG_EN_Msk (0x8UL) 1878 #define LPTIM_CR_TOG_EN LPTIM_CR_TOG_EN_Msk 1879 #define LPTIM_CR_TCK_SEL_Pos (4UL) 1880 #define LPTIM_CR_TCK_SEL_Msk (0x30UL) 1881 #define LPTIM_CR_TCK_SEL LPTIM_CR_TCK_SEL_Msk 1882 #define LPTIM_CR_TCK_SEL_0 (0x1 << LPTIM_CR_TCK_SEL_Pos) 1883 #define LPTIM_CR_TCK_SEL_1 (0x2 << LPTIM_CR_TCK_SEL_Pos) 1884 #define LPTIM_CR_GATE_EN_Pos (6UL) 1885 #define LPTIM_CR_GATE_EN_Msk (0x40UL) 1886 #define LPTIM_CR_GATE_EN LPTIM_CR_GATE_EN_Msk 1887 #define LPTIM_CR_GATE_P_Pos (7UL) 1888 #define LPTIM_CR_GATE_P_Msk (0x80UL) 1889 #define LPTIM_CR_GATE_P LPTIM_CR_GATE_P_Msk 1890 #define LPTIM_CR_INT_EN_Pos (8UL) 1891 #define LPTIM_CR_INT_EN_Msk (0x100UL) 1892 #define LPTIM_CR_INT_EN LPTIM_CR_INT_EN_Msk 1893 #define LPTIM_CR_TCK_EN_Pos (9UL) 1894 #define LPTIM_CR_TCK_EN_Msk (0x200UL) 1895 #define LPTIM_CR_TCK_EN LPTIM_CR_TCK_EN_Msk 1896 #define LPTIM_CR_WT_FLAG_Pos (16UL) 1897 #define LPTIM_CR_WT_FLAG_Msk (0x10000UL) 1898 #define LPTIM_CR_WT_FLAG LPTIM_CR_WT_FLAG_Msk 1899 #define LPTIM_CR_ALL_Msk (0x3FFUL) 1901 #define LPTIM_LOAD_LOAD_Pos (0UL) 1902 #define LPTIM_LOAD_LOAD_Msk (0xFFFFUL) 1903 #define LPTIM_LOAD_LOAD LPTIM_LOAD_LOAD_Msk 1905 #define LPTIM_INTSR_INTF_Pos (0UL) 1906 #define LPTIM_INTSR_INTF_Msk (0x01UL) 1907 #define LPTIM_INTSR_INTF LPTIM_INTSR_INTF_Msk 1909 #define LPTIM_INTCLR_ICLR_Pos (0UL) 1910 #define LPTIM_INTCLR_ICLR_Msk (0x1UL) 1911 #define LPTIM_INTCLR_ICLR LPTIM_INTCLR_ICLR_Msk 1913 #define LPTIM_BGLOAD_BGLOAD_Pos (0UL) 1914 #define LPTIM_BGLOAD_BGLOAD_Msk (0xFFFFUL) 1915 #define LPTIM_BGLOAD_BGLOAD LPTIM_BGLOAD_BGLOAD_Msk 1923 #define BASETIM_CR_TMR_PRSC_Pos (0UL) 1924 #define BASETIM_CR_TMR_PRSC_Msk (0x7UL) 1925 #define BASETIM_CR_TMR_PRSC BASETIM_CR_TMR_PRSC_Msk 1926 #define BASETIM_CR_TMR_PRSC_0 (0x1 << BASETIM_CR_TMR_PRSC_Pos) 1927 #define BASETIM_CR_TMR_PRSC_1 (0x2 << BASETIM_CR_TMR_PRSC_Pos) 1928 #define BASETIM_CR_TMR_PRSC_2 (0x4 << BASETIM_CR_TMR_PRSC_Pos) 1929 #define BASETIM_CR_ONESHOT_Pos (3UL) 1930 #define BASETIM_CR_ONESHOT_Msk (0x8UL) 1931 #define BASETIM_CR_ONESHOT BASETIM_CR_ONESHOT_Msk 1932 #define BASETIM_CR_TMR_SIZE_Pos (4UL) 1933 #define BASETIM_CR_TMR_SIZE_Msk (0x10UL) 1934 #define BASETIM_CR_TMR_SIZE BASETIM_CR_TMR_SIZE_Msk 1935 #define BASETIM_CR_INTEN_Pos (5UL) 1936 #define BASETIM_CR_INTEN_Msk (0x20UL) 1937 #define BASETIM_CR_INTEN BASETIM_CR_INTEN_Msk 1938 #define BASETIM_CR_MODE_Pos (6UL) 1939 #define BASETIM_CR_MODE_Msk (0x40UL) 1940 #define BASETIM_CR_MODE BASETIM_CR_MODE_Msk 1941 #define BASETIM_CR_TR_Pos (7UL) 1942 #define BASETIM_CR_TR_Msk (0x80UL) 1943 #define BASETIM_CR_TR BASETIM_CR_TR_Msk 1944 #define BASETIM_CR_CT_SEL_Pos (8UL) 1945 #define BASETIM_CR_CT_SEL_Msk (0x100UL) 1946 #define BASETIM_CR_CT_SEL BASETIM_CR_CT_SEL_Msk 1947 #define BASETIM_CR_TOG_EN_Pos (9UL) 1948 #define BASETIM_CR_TOG_EN_Msk (0x200UL) 1949 #define BASETIM_CR_TOG_EN BASETIM_CR_TOG_EN_Msk 1950 #define BASETIM_CR_GATE_EN_Pos (10UL) 1951 #define BASETIM_CR_GATE_EN_Msk (0x400UL) 1952 #define BASETIM_CR_GATE_EN BASETIM_CR_GATE_EN_Msk 1953 #define BASETIM_CR_GATE_P_Pos (11UL) 1954 #define BASETIM_CR_GATE_P_Msk (0x800UL) 1955 #define BASETIM_CR_GATE_P BASETIM_CR_GATE_P_Msk 1956 #define BASETIM_CR_ALL_Msk (0xFFFUL) 1958 #define BASETIM_LOAD_LOAD_Pos (0UL) 1959 #define BASETIM_LOAD_LOAD_Msk (0xFFFFFFFFUL) 1960 #define BASETIM_LOAD_LOAD BASETIM_LOAD_LOAD_Msk 1962 #define BASETIM_CNT_CNT_Pos (0UL) 1963 #define BASETIM_CNT_CNT_Msk (0xFFFFFFFFUL) 1965 #define BASETIM_RAWINTSR_RIS_Pos (0UL) 1966 #define BASETIM_RAWINTSR_RIS_Msk (0x1UL) 1967 #define BASETIM_RAWINTSR_RIS BASETIM_RAWINTSR_RIS_Msk 1969 #define BASETIM_MSKINTSR_TF_Pos (0UL) 1970 #define BASETIM_MSKINTSR_TF_Msk (0x1UL) 1971 #define BASETIM_MSKINTSR_TF BASETIM_MSKINTSR_TF_Msk 1973 #define BASETIM_INTCLR_INTCLR_Pos (0UL) 1974 #define BASETIM_INTCLR_INTCLR_Msk (0x1UL) 1975 #define BASETIM_INTCLR_INTCLR BASETIM_INTCLR_INTCLR_Msk 1977 #define BASETIM_BGLOAD_BGLOAD_Pos (0UL) 1978 #define BASETIM_BGLOAD_BGLOAD_Msk (0xFFFFFFFFUL) 1979 #define BASETIM_BGLOAD_BGLOAD BASETIM_BGLOAD_BGLOAD_Msk 1987 #define PCA_CR_CCF0_Pos (0UL) 1988 #define PCA_CR_CCF0_Msk (0x1UL) 1989 #define PCA_CR_CCF0 PCA_CR_CCF0_Msk 1990 #define PCA_CR_CCF1_Pos (1UL) 1991 #define PCA_CR_CCF1_Msk (0x2UL) 1992 #define PCA_CR_CCF1 PCA_CR_CCF1_Msk 1993 #define PCA_CR_CCF2_Pos (2UL) 1994 #define PCA_CR_CCF2_Msk (0x4UL) 1995 #define PCA_CR_CCF2 PCA_CR_CCF2_Msk 1996 #define PCA_CR_CCF3_Pos (3UL) 1997 #define PCA_CR_CCF3_Msk (0x8UL) 1998 #define PCA_CR_CCF3 PCA_CR_CCF3_Msk 1999 #define PCA_CR_CCF4_Pos (4UL) 2000 #define PCA_CR_CCF4_Msk (0x10UL) 2001 #define PCA_CR_CCF4 PCA_CR_CCF4_Msk 2002 #define PCA_CR_CR_Pos (6UL) 2003 #define PCA_CR_CR_Msk (0x40UL) 2004 #define PCA_CR_CR PCA_CR_CR_Msk 2005 #define PCA_CR_CF_Pos (7UL) 2006 #define PCA_CR_CF_Msk (0x80UL) 2007 #define PCA_CR_CF PCA_CR_CF_Msk 2009 #define PCA_MOD_CFIE_Pos (0UL) 2010 #define PCA_MOD_CFIE_Msk (0x1UL) 2011 #define PCA_MOD_CFIE PCA_MOD_CFIE_Msk 2012 #define PCA_MOD_CPS_Pos (1UL) 2013 #define PCA_MOD_CPS_Msk (0xEUL) 2014 #define PCA_MOD_CPS PCA_MOD_CPS_Msk 2015 #define PCA_MOD_CPS_0 (0x01 << PCA_MOD_CPS_Pos) 2016 #define PCA_MOD_CPS_1 (0x02 << PCA_MOD_CPS_Pos) 2017 #define PCA_MOD_CPS_2 (0x04 << PCA_MOD_CPS_Pos) 2018 #define PCA_MOD_CIDL_Pos (7UL) 2019 #define PCA_MOD_CIDL_Msk (0x80UL) 2020 #define PCA_MOD_CIDL PCA_MOD_CIDL_Msk 2022 #define PCA_CNT_CNT_Pos (0UL) 2023 #define PCA_CNT_CNT_Msk (0xFFUL) 2025 #define PCA_INTCLR_CCF0_Pos (0UL) 2026 #define PCA_INTCLR_CCF0_Msk (0x1UL) 2027 #define PCA_INTCLR_CCF1_Pos (1UL) 2028 #define PCA_INTCLR_CCF1_Msk (0x2UL) 2029 #define PCA_INTCLR_CCF2_Pos (2UL) 2030 #define PCA_INTCLR_CCF2_Msk (0x4UL) 2031 #define PCA_INTCLR_CCF3_Pos (3UL) 2032 #define PCA_INTCLR_CCF3_Msk (0x8UL) 2033 #define PCA_INTCLR_CCF4_Pos (4UL) 2034 #define PCA_INTCLR_CCF4_Msk (0x10UL) 2035 #define PCA_INTCLR_CF_Pos (7UL) 2036 #define PCA_INTCLR_CF_Msk (0x80UL) 2038 #define PCA_CCAPM0_ECOM_Pos (6UL) 2039 #define PCA_CCAPM0_ECOM_Msk (0x40UL) 2040 #define PCA_CCAPM0_ECOM PCA_CCAPM0_ECOM_Msk 2041 #define PCA_CCAPM0_CAPP_Pos (5UL) 2042 #define PCA_CCAPM0_CAPP_Msk (0x20UL) 2043 #define PCA_CCAPM0_CAPP PCA_CCAPM0_CAPP_Msk 2044 #define PCA_CCAPM0_CAPN_Pos (4UL) 2045 #define PCA_CCAPM0_CAPN_Msk (0x10UL) 2046 #define PCA_CCAPM0_CAPN PCA_CCAPM0_CAPN_Msk 2047 #define PCA_CCAPM0_MAT_Pos (3UL) 2048 #define PCA_CCAPM0_MAT_Msk (0x8UL) 2049 #define PCA_CCAPM0_MAT PCA_CCAPM0_MAT_Msk 2050 #define PCA_CCAPM0_TOG_Pos (2UL) 2051 #define PCA_CCAPM0_TOG_Msk (0x4UL) 2052 #define PCA_CCAPM0_TOG PCA_CCAPM0_TOG_Msk 2053 #define PCA_CCAPM0_PWM_Pos (1UL) 2054 #define PCA_CCAPM0_PWM_Msk (0x2UL) 2055 #define PCA_CCAPM0_PWM PCA_CCAPM0_PWM_Msk 2056 #define PCA_CCAPM0_CCIE_Pos (0UL) 2057 #define PCA_CCAPM0_CCIE_Msk (0x1UL) 2058 #define PCA_CCAPM0_CCIE PCA_CCAPM0_CCIE_Msk 2060 #define PCA_CCAPM1_ECOM_Pos (6UL) 2061 #define PCA_CCAPM1_ECOM_Msk (0x40UL) 2062 #define PCA_CCAPM1_ECOM PCA_CCAPM1_ECOM_Msk 2063 #define PCA_CCAPM1_CAPP_Pos (5UL) 2064 #define PCA_CCAPM1_CAPP_Msk (0x20UL) 2065 #define PCA_CCAPM1_CAPP PCA_CCAPM1_CAPP_Msk 2066 #define PCA_CCAPM1_CAPN_Pos (4UL) 2067 #define PCA_CCAPM1_CAPN_Msk (0x10UL) 2068 #define PCA_CCAPM1_CAPN PCA_CCAPM1_CAPN_Msk 2069 #define PCA_CCAPM1_MAT_Pos (3UL) 2070 #define PCA_CCAPM1_MAT_Msk (0x8UL) 2071 #define PCA_CCAPM1_MAT PCA_CCAPM1_MAT_Msk 2072 #define PCA_CCAPM1_TOG_Pos (2UL) 2073 #define PCA_CCAPM1_TOG_Msk (0x4UL) 2074 #define PCA_CCAPM1_TOG PCA_CCAPM1_TOG_Msk 2075 #define PCA_CCAPM1_PWM_Pos (1UL) 2076 #define PCA_CCAPM1_PWM_Msk (0x2UL) 2077 #define PCA_CCAPM1_PWM PCA_CCAPM1_PWM_Msk 2078 #define PCA_CCAPM1_CCIE_Pos (0UL) 2079 #define PCA_CCAPM1_CCIE_Msk (0x1UL) 2080 #define PCA_CCAPM1_CCIE PCA_CCAPM1_CCIE_Msk 2082 #define PCA_CCAPM2_ECOM_Pos (6UL) 2083 #define PCA_CCAPM2_ECOM_Msk (0x40UL) 2084 #define PCA_CCAPM2_ECOM PCA_CCAPM2_ECOM_Msk 2085 #define PCA_CCAPM2_CAPP_Pos (5UL) 2086 #define PCA_CCAPM2_CAPP_Msk (0x20UL) 2087 #define PCA_CCAPM2_CAPP PCA_CCAPM2_CAPP_Msk 2088 #define PCA_CCAPM2_CAPN_Pos (4UL) 2089 #define PCA_CCAPM2_CAPN_Msk (0x10UL) 2090 #define PCA_CCAPM2_CAPN PCA_CCAPM2_CAPN_Msk 2091 #define PCA_CCAPM2_MAT_Pos (3UL) 2092 #define PCA_CCAPM2_MAT_Msk (0x8UL) 2093 #define PCA_CCAPM2_MAT PCA_CCAPM2_MAT_Msk 2094 #define PCA_CCAPM2_TOG_Pos (2UL) 2095 #define PCA_CCAPM2_TOG_Msk (0x4UL) 2096 #define PCA_CCAPM2_TOG PCA_CCAPM2_TOG_Msk 2097 #define PCA_CCAPM2_PWM_Pos (1UL) 2098 #define PCA_CCAPM2_PWM_Msk (0x2UL) 2099 #define PCA_CCAPM2_PWM PCA_CCAPM2_PWM_Msk 2100 #define PCA_CCAPM2_CCIE_Pos (0UL) 2101 #define PCA_CCAPM2_CCIE_Msk (0x1UL) 2102 #define PCA_CCAPM2_CCIE PCA_CCAPM2_CCIE_Msk 2104 #define PCA_CCAPM3_ECOM_Pos (6UL) 2105 #define PCA_CCAPM3_ECOM_Msk (0x40UL) 2106 #define PCA_CCAPM3_ECOM PCA_CCAPM3_ECOM_Msk 2107 #define PCA_CCAPM3_CAPP_Pos (5UL) 2108 #define PCA_CCAPM3_CAPP_Msk (0x20UL) 2109 #define PCA_CCAPM3_CAPP PCA_CCAPM3_CAPP_Msk 2110 #define PCA_CCAPM3_CAPN_Pos (4UL) 2111 #define PCA_CCAPM3_CAPN_Msk (0x10UL) 2112 #define PCA_CCAPM3_CAPN PCA_CCAPM3_CAPN_Msk 2113 #define PCA_CCAPM3_MAT_Pos (3UL) 2114 #define PCA_CCAPM3_MAT_Msk (0x8UL) 2115 #define PCA_CCAPM3_MAT PCA_CCAPM3_MAT_Msk 2116 #define PCA_CCAPM3_TOG_Pos (2UL) 2117 #define PCA_CCAPM3_TOG_Msk (0x4UL) 2118 #define PCA_CCAPM3_TOG PCA_CCAPM3_TOG_Msk 2119 #define PCA_CCAPM3_PWM_Pos (1UL) 2120 #define PCA_CCAPM3_PWM_Msk (0x2UL) 2121 #define PCA_CCAPM3_PWM PCA_CCAPM3_PWM_Msk 2122 #define PCA_CCAPM3_CCIE_Pos (0UL) 2123 #define PCA_CCAPM3_CCIE_Msk (0x1UL) 2124 #define PCA_CCAPM3_CCIE PCA_CCAPM3_CCIE_Msk 2126 #define PCA_CCAPM4_ECOM_Pos (6UL) 2127 #define PCA_CCAPM4_ECOM_Msk (0x40UL) 2128 #define PCA_CCAPM4_ECOM PCA_CCAPM4_ECOM_Msk 2129 #define PCA_CCAPM4_CAPP_Pos (5UL) 2130 #define PCA_CCAPM4_CAPP_Msk (0x20UL) 2131 #define PCA_CCAPM4_CAPP PCA_CCAPM4_CAPP_Msk 2132 #define PCA_CCAPM4_CAPN_Pos (4UL) 2133 #define PCA_CCAPM4_CAPN_Msk (0x10UL) 2134 #define PCA_CCAPM4_CAPN PCA_CCAPM4_CAPN_Msk 2135 #define PCA_CCAPM4_MAT_Pos (3UL) 2136 #define PCA_CCAPM4_MAT_Msk (0x8UL) 2137 #define PCA_CCAPM4_MAT PCA_CCAPM4_MAT_Msk 2138 #define PCA_CCAPM4_TOG_Pos (2UL) 2139 #define PCA_CCAPM4_TOG_Msk (0x4UL) 2140 #define PCA_CCAPM4_TOG PCA_CCAPM4_TOG_Msk 2141 #define PCA_CCAPM4_PWM_Pos (1UL) 2142 #define PCA_CCAPM4_PWM_Msk (0x2UL) 2143 #define PCA_CCAPM4_PWM PCA_CCAPM4_PWM_Msk 2144 #define PCA_CCAPM4_CCIE_Pos (0UL) 2145 #define PCA_CCAPM4_CCIE_Msk (0x1UL) 2146 #define PCA_CCAPM4_CCIE PCA_CCAPM4_CCIE_Msk 2148 #define PCA_CCAP0L_CCAP0_Pos (0UL) 2149 #define PCA_CCAP0L_CCAP0_Msk (0xFFUL) 2151 #define PCA_CCAP0H_CCAP0_Pos (8UL) 2152 #define PCA_CCAP0H_CCAP0_Msk (0xFF00UL) 2154 #define PCA_CCAP1L_CCAP1_Pos (0UL) 2155 #define PCA_CCAP1L_CCAP1_Msk (0xFFUL) 2157 #define PCA_CCAP1H_CCAP1_Pos (8UL) 2158 #define PCA_CCAP1H_CCAP1_Msk (0xFF00UL) 2160 #define PCA_CCAP2L_CCAP2_Pos (0UL) 2161 #define PCA_CCAP2L_CCAP2_Msk (0xFFUL) 2163 #define PCA_CCAP2H_CCAP2_Pos (0UL) 2164 #define PCA_CCAP2H_CCAP2_Msk (0xFFUL) 2166 #define PCA_CCAP3L_CCAP3_Pos (0UL) 2167 #define PCA_CCAP3L_CCAP3_Msk (0xFFUL) 2169 #define PCA_CCAP3H_CCAP3_Pos (8UL) 2170 #define PCA_CCAP3H_CCAP3_Msk (0xFF00UL) 2172 #define PCA_CCAP4L_CCAP4_Pos (0UL) 2173 #define PCA_CCAP4L_CCAP4_Msk (0xFFUL) 2175 #define PCA_CCAP4H_CCAP4_Pos (8UL) 2176 #define PCA_CCAP4H_CCAP4_Msk (0xFF00UL) 2178 #define PCA_CCAPO_CCAPO4_Pos (4UL) 2179 #define PCA_CCAPO_CCAPO4_Msk (0x10UL) 2180 #define PCA_CCAPO_CCAPO3_Pos (3UL) 2181 #define PCA_CCAPO_CCAPO3_Msk (0x8UL) 2182 #define PCA_CCAPO_CCAPO2_Pos (2UL) 2183 #define PCA_CCAPO_CCAPO2_Msk (0x4UL) 2184 #define PCA_CCAPO_CCAPO1_Pos (1UL) 2185 #define PCA_CCAPO_CCAPO1_Msk (0x2UL) 2186 #define PCA_CCAPO_CCAPO0_Pos (0UL) 2187 #define PCA_CCAPO_CCAPO0_Msk (0x1UL) 2189 #define PCA_POCR_POINV4_Pos (12UL) 2190 #define PCA_POCR_POINV4_Msk (0x1000UL) 2191 #define PCA_POCR_POINV3_Pos (11UL) 2192 #define PCA_POCR_POINV3_Msk (0x800UL) 2193 #define PCA_POCR_POINV2_Pos (10UL) 2194 #define PCA_POCR_POINV2_Msk (0x400UL) 2195 #define PCA_POCR_POINV1_Pos (9UL) 2196 #define PCA_POCR_POINV1_Msk (0x200UL) 2197 #define PCA_POCR_POINV0_Pos (8UL) 2198 #define PCA_POCR_POINV0_Msk (0x100UL) 2199 #define PCA_POCR_POE4_Pos (4UL) 2200 #define PCA_POCR_POE4_Msk (0x10UL) 2201 #define PCA_POCR_POE4 PCA_POCR_POE4_Msk 2202 #define PCA_POCR_POE3_Pos (3UL) 2203 #define PCA_POCR_POE3_Msk (0x8UL) 2204 #define PCA_POCR_POE3 PCA_POCR_POE3_Msk 2205 #define PCA_POCR_POE2_Pos (2UL) 2206 #define PCA_POCR_POE2_Msk (0x4UL) 2207 #define PCA_POCR_POE2 PCA_POCR_POE2_Msk 2208 #define PCA_POCR_POE1_Pos (1UL) 2209 #define PCA_POCR_POE1_Msk (0x2UL) 2210 #define PCA_POCR_POE1 PCA_POCR_POE1_Msk 2211 #define PCA_POCR_POE0_Pos (0UL) 2212 #define PCA_POCR_POE0_Msk (0x1UL) 2213 #define PCA_POCR_POE0 PCA_POCR_POE0_Msk 2215 #define PCA_CCAP0_CCAP0_Pos (0UL) 2216 #define PCA_CCAP0_CCAP0_Msk (0xFFFFUL) 2218 #define PCA_CCAP1_CCAP1_Pos (0UL) 2219 #define PCA_CCAP1_CCAP1_Msk (0xFFFFUL) 2221 #define PCA_CCAP2_CCAP2_Pos (0UL) 2222 #define PCA_CCAP2_CCAP2_Msk (0xFFFFUL) 2224 #define PCA_CCAP3_CCAP3_Pos (0UL) 2225 #define PCA_CCAP3_CCAP3_Msk (0x7FFFUL) 2227 #define PCA_CCAP4_CCAP4_Pos (0UL) 2228 #define PCA_CCAP4_CCAP4_Msk (0xFFFFUL) 2236 #define TIM_CR1_CEN_Pos (0UL) 2237 #define TIM_CR1_CEN_Msk (0x1UL) 2238 #define TIM_CR1_CEN TIM_CR1_CEN_Msk 2239 #define TIM_CR1_UDIS_Pos (1UL) 2240 #define TIM_CR1_UDIS_Msk (0x2UL) 2241 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk 2242 #define TIM_CR1_URS_Pos (2UL) 2243 #define TIM_CR1_URS_Msk (0x4UL) 2244 #define TIM_CR1_URS TIM_CR1_URS_Msk 2245 #define TIM_CR1_OPM_Pos (3UL) 2246 #define TIM_CR1_OPM_Msk (0x8UL) 2247 #define TIM_CR1_OPM TIM_CR1_OPM_Msk 2248 #define TIM_CR1_DIR_Pos (4UL) 2249 #define TIM_CR1_DIR_Msk (0x10UL) 2250 #define TIM_CR1_DIR TIM_CR1_DIR_Msk 2251 #define TIM_CR1_CMS_Pos (5UL) 2252 #define TIM_CR1_CMS_Msk (0x60UL) 2253 #define TIM_CR1_CMS TIM_CR1_CMS_Msk 2254 #define TIM_CR1_ARPE_Pos (7UL) 2255 #define TIM_CR1_ARPE_Msk (0x80UL) 2256 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk 2257 #define TIM_CR1_CKD_Pos (8UL) 2258 #define TIM_CR1_CKD_Msk (0x300UL) 2259 #define TIM_CR1_CKD TIM_CR1_CKD_Msk 2261 #define TIM_CR2_CCPC_Pos (0UL) 2262 #define TIM_CR2_CCPC_Msk (0x1UL) 2263 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk 2264 #define TIM_CR2_CCUS_Pos (2UL) 2265 #define TIM_CR2_CCUS_Msk (0x4UL) 2266 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk 2267 #define TIM_CR2_MMS_Pos (4UL) 2268 #define TIM_CR2_MMS_Msk (0x70UL) 2269 #define TIM_CR2_MMS TIM_CR2_MMS_Msk 2270 #define TIM_CR2_TI1S_Pos (7UL) 2271 #define TIM_CR2_TI1S_Msk (0x80UL) 2272 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk 2273 #define TIM_CR2_OIS1_Pos (8UL) 2274 #define TIM_CR2_OIS1_Msk (0x100UL) 2275 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk 2276 #define TIM_CR2_OIS1N_Pos (9UL) 2277 #define TIM_CR2_OIS1N_Msk (0x200UL) 2278 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk 2279 #define TIM_CR2_OIS2_Pos (10UL) 2280 #define TIM_CR2_OIS2_Msk (0x400UL) 2281 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk 2282 #define TIM_CR2_OIS2N_Pos (11UL) 2283 #define TIM_CR2_OIS2N_Msk (0x800UL) 2284 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk 2285 #define TIM_CR2_OIS3_Pos (12UL) 2286 #define TIM_CR2_OIS3_Msk (0x1000UL) 2287 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk 2288 #define TIM_CR2_OIS3N_Pos (13UL) 2289 #define TIM_CR2_OIS3N_Msk (0x2000UL) 2290 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk 2291 #define TIM_CR2_OIS4_Pos (14UL) 2292 #define TIM_CR2_OIS4_Msk (0x4000UL) 2293 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk 2296 #define TIM_SMCR_SMS_Pos (0UL) 2297 #define TIM_SMCR_SMS_Msk (0x7UL) 2298 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk 2299 #define TIM_SMCR_TS_Pos (4UL) 2300 #define TIM_SMCR_TS_Msk (0x70UL) 2301 #define TIM_SMCR_TS TIM_SMCR_TS_Msk 2302 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) 2303 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) 2304 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) 2305 #define TIM_SMCR_MSM_Pos (7UL) 2306 #define TIM_SMCR_MSM_Msk (0x80UL) 2307 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk 2308 #define TIM_SMCR_ETF_Pos (8UL) 2309 #define TIM_SMCR_ETF_Msk (0xF00UL) 2310 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk 2311 #define TIM_SMCR_ETPS_Pos (12UL) 2312 #define TIM_SMCR_ETPS_Msk (0x3000UL) 2313 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk 2314 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) 2315 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) 2316 #define TIM_SMCR_ECE_Pos (14UL) 2317 #define TIM_SMCR_ECE_Msk (0x4000UL) 2318 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk 2319 #define TIM_SMCR_ETP_Pos (15UL) 2320 #define TIM_SMCR_ETP_Msk (0x8000UL) 2321 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk 2323 #define TIM_DIER_UIE_Pos (0UL) 2324 #define TIM_DIER_UIE_Msk (0x1UL) 2325 #define TIM_DIER_UIE TIM_DIER_UIE_Msk 2326 #define TIM_DIER_CC1IE_Pos (1UL) 2327 #define TIM_DIER_CC1IE_Msk (0x2UL) 2328 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk 2329 #define TIM_DIER_CC2IE_Pos (2UL) 2330 #define TIM_DIER_CC2IE_Msk (0x4UL) 2331 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk 2332 #define TIM_DIER_CC3IE_Pos (3UL) 2333 #define TIM_DIER_CC3IE_Msk (0x8UL) 2334 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk 2335 #define TIM_DIER_CC4IE_Pos (4UL) 2336 #define TIM_DIER_CC4IE_Msk (0x10UL) 2337 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk 2338 #define TIM_DIER_COMIE_Pos (5UL) 2339 #define TIM_DIER_COMIE_Msk (0x20UL) 2340 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk 2341 #define TIM_DIER_TIE_Pos (6UL) 2342 #define TIM_DIER_TIE_Msk (0x40UL) 2343 #define TIM_DIER_TIE TIM_DIER_TIE_Msk 2344 #define TIM_DIER_BIE_Pos (7UL) 2345 #define TIM_DIER_BIE_Msk (0x80UL) 2346 #define TIM_DIER_BIE TIM_DIER_BIE_Msk 2348 #define TIM_SR_CC4OF_Pos (12UL) 2349 #define TIM_SR_CC4OF_Msk (0x1000UL) 2350 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk 2351 #define TIM_SR_CC3OF_Pos (11UL) 2352 #define TIM_SR_CC3OF_Msk (0x800UL) 2353 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk 2354 #define TIM_SR_CC2OF_Pos (10UL) 2355 #define TIM_SR_CC2OF_Msk (0x400UL) 2356 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk 2357 #define TIM_SR_CC1OF_Pos (9UL) 2358 #define TIM_SR_CC1OF_Msk (0x200UL) 2359 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk 2360 #define TIM_SR_BIF_Pos (7UL) 2361 #define TIM_SR_BIF_Msk (0x80UL) 2362 #define TIM_SR_BIF TIM_SR_BIF_Msk 2363 #define TIM_SR_TIF_Pos (6UL) 2364 #define TIM_SR_TIF_Msk (0x40UL) 2365 #define TIM_SR_TIF TIM_SR_TIF_Msk 2366 #define TIM_SR_COMIF_Pos (5UL) 2367 #define TIM_SR_COMIF_Msk (0x20UL) 2368 #define TIM_SR_COMIF TIM_SR_COMIF_Msk 2369 #define TIM_SR_CC4IF_Pos (4UL) 2370 #define TIM_SR_CC4IF_Msk (0x10UL) 2371 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk 2372 #define TIM_SR_CC3IF_Pos (3UL) 2373 #define TIM_SR_CC3IF_Msk (0x8UL) 2374 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk 2375 #define TIM_SR_CC2IF_Pos (2UL) 2376 #define TIM_SR_CC2IF_Msk (0x4UL) 2377 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk 2378 #define TIM_SR_CC1IF_Pos (1UL) 2379 #define TIM_SR_CC1IF_Msk (0x2UL) 2380 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk 2381 #define TIM_SR_UIF_Pos (0UL) 2382 #define TIM_SR_UIF_Msk (0x1UL) 2383 #define TIM_SR_UIF TIM_SR_UIF_Msk 2385 #define TIM_EGR_BG_Pos (7UL) 2386 #define TIM_EGR_BG_Msk (0x80UL) 2387 #define TIM_EGR_TG_Pos (6UL) 2388 #define TIM_EGR_TG_Msk (0x40UL) 2389 #define TIM_EGR_COMG_Pos (5UL) 2390 #define TIM_EGR_COMG_Msk (0x20UL) 2391 #define TIM_EGR_CC4G_Pos (4UL) 2392 #define TIM_EGR_CC4G_Msk (0x10UL) 2393 #define TIM_EGR_CC3G_Pos (3UL) 2394 #define TIM_EGR_CC3G_Msk (0x8UL) 2395 #define TIM_EGR_CC2G_Pos (2UL) 2396 #define TIM_EGR_CC2G_Msk (0x4UL) 2397 #define TIM_EGR_CC1G_Pos (1UL) 2398 #define TIM_EGR_CC1G_Msk (0x2UL) 2399 #define TIM_EGR_UG_Pos (0UL) 2400 #define TIM_EGR_UG_Msk (0x1UL) 2401 #define TIM_EGR_UG TIM_EGR_UG_Msk 2403 #define TIM_CCMR1_OC2CE_Pos (15UL) 2404 #define TIM_CCMR1_OC2CE_Msk (0x8000UL) 2405 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk 2406 #define TIM_CCMR1_OC2M_Pos (12UL) 2407 #define TIM_CCMR1_OC2M_Msk (0x7000UL) 2408 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk 2409 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) 2410 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) 2411 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) 2412 #define TIM_CCMR1_OC2PE_Pos (11UL) 2413 #define TIM_CCMR1_OC2PE_Msk (0x800UL) 2414 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk 2415 #define TIM_CCMR1_OC2FE_Pos (10UL) 2416 #define TIM_CCMR1_OC2FE_Msk (0x400UL) 2417 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk 2418 #define TIM_CCMR1_CC2S_Pos (8UL) 2419 #define TIM_CCMR1_CC2S_Msk (0x300UL) 2420 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk 2421 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) 2422 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) 2423 #define TIM_CCMR1_OC1CE_Pos (7UL) 2424 #define TIM_CCMR1_OC1CE_Msk (0x80UL) 2425 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk 2426 #define TIM_CCMR1_OC1M_Pos (4UL) 2427 #define TIM_CCMR1_OC1M_Msk (0x70UL) 2428 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk 2429 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) 2430 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) 2431 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) 2432 #define TIM_CCMR1_OC1PE_Pos (3UL) 2433 #define TIM_CCMR1_OC1PE_Msk (0x8UL) 2434 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk 2435 #define TIM_CCMR1_OC1FE_Pos (2UL) 2436 #define TIM_CCMR1_OC1FE_Msk (0x4UL) 2437 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk 2438 #define TIM_CCMR1_CC1S_Pos (0UL) 2439 #define TIM_CCMR1_CC1S_Msk (0x3UL) 2440 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk 2441 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) 2442 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) 2443 #define TIM_CCMR1_IC1PSC_Pos (2UL) 2444 #define TIM_CCMR1_IC1PSC_Msk (0x0000000CUL) 2445 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk 2446 #define TIM_CCMR1_IC1PSC_0 (0x00000004UL) 2447 #define TIM_CCMR1_IC1PSC_1 (0x00000008UL) 2448 #define TIM_CCMR1_IC1F_Pos (4UL) 2449 #define TIM_CCMR1_IC1F_Msk (0x000000F0UL) 2450 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk 2451 #define TIM_CCMR1_IC1F_0 (0x00000010UL) 2452 #define TIM_CCMR1_IC1F_1 (0x00000020UL) 2453 #define TIM_CCMR1_IC1F_2 (0x00000040UL) 2454 #define TIM_CCMR1_IC1F_3 (0x00000080UL) 2455 #define TIM_CCMR1_IC2PSC_Pos (10UL) 2456 #define TIM_CCMR1_IC2PSC_Msk (0x00000C00UL) 2457 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk 2458 #define TIM_CCMR1_IC2PSC_0 (0x00000400UL) 2459 #define TIM_CCMR1_IC2PSC_1 (0x00000800UL) 2460 #define TIM_CCMR1_IC2F_Pos (12U) 2461 #define TIM_CCMR1_IC2F_Msk (0x0000F000UL) 2462 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk 2463 #define TIM_CCMR1_IC2F_0 (0x00001000UL) 2464 #define TIM_CCMR1_IC2F_1 (0x00002000UL) 2465 #define TIM_CCMR1_IC2F_2 (0x00004000UL) 2466 #define TIM_CCMR1_IC2F_3 (0x00008000UL) 2468 #define TIM_CCMR2_OC4CE_Pos (15UL) 2469 #define TIM_CCMR2_OC4CE_Msk (0x8000UL) 2470 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk 2471 #define TIM_CCMR2_OC4M_Pos (12UL) 2472 #define TIM_CCMR2_OC4M_Msk (0x7000UL) 2473 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk 2474 #define TIM_CCMR2_OC4PE_Pos (11UL) 2475 #define TIM_CCMR2_OC4PE_Msk (0x800UL) 2476 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk 2477 #define TIM_CCMR2_OC4FE_Pos (10UL) 2478 #define TIM_CCMR2_OC4FE_Msk (0x400UL) 2479 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk 2480 #define TIM_CCMR2_CC4S_Pos (8UL) 2481 #define TIM_CCMR2_CC4S_Msk (0x300UL) 2482 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk 2483 #define TIM_CCMR2_OC3CE_Pos (7UL) 2484 #define TIM_CCMR2_OC3CE_Msk (0x80UL) 2485 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk 2486 #define TIM_CCMR2_OC3M_Pos (4UL) 2487 #define TIM_CCMR2_OC3M_Msk (0x70UL) 2488 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk 2489 #define TIM_CCMR2_OC3PE_Pos (3UL) 2490 #define TIM_CCMR2_OC3PE_Msk (0x8UL) 2491 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk 2492 #define TIM_CCMR2_OC3FE_Pos (2UL) 2493 #define TIM_CCMR2_OC3FE_Msk (0x4UL) 2494 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk 2495 #define TIM_CCMR2_CC3S_Pos (0UL) 2496 #define TIM_CCMR2_CC3S_Msk (0x3UL) 2497 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk 2499 #define TIM_CCMR2_IC3PSC_Pos (2UL) 2500 #define TIM_CCMR2_IC3PSC_Msk (0x0000000CUL) 2501 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk 2502 #define TIM_CCMR2_IC3PSC_0 (0x00000004UL) 2503 #define TIM_CCMR2_IC3PSC_1 (0x00000008UL) 2504 #define TIM_CCMR2_IC3F_Pos (4UL) 2505 #define TIM_CCMR2_IC3F_Msk (0x000000F0UL) 2506 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk 2507 #define TIM_CCMR2_IC3F_0 (0x00000010UL) 2508 #define TIM_CCMR2_IC3F_1 (0x00000020UL) 2509 #define TIM_CCMR2_IC3F_2 (0x00000040UL) 2510 #define TIM_CCMR2_IC3F_3 (0x00000080UL) 2511 #define TIM_CCMR2_IC4PSC_Pos (10UL) 2512 #define TIM_CCMR2_IC4PSC_Msk (0x00000C00UL) 2513 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk 2514 #define TIM_CCMR2_IC4PSC_0 (0x00000400UL) 2515 #define TIM_CCMR2_IC4PSC_1 (0x00000800UL) 2516 #define TIM_CCMR2_IC4F_Pos (12UL) 2517 #define TIM_CCMR2_IC4F_Msk (0x0000F000UL) 2518 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk 2519 #define TIM_CCMR2_IC4F_0 (0x00001000UL) 2520 #define TIM_CCMR2_IC4F_1 (0x00002000UL) 2521 #define TIM_CCMR2_IC4F_2 (0x00004000UL) 2522 #define TIM_CCMR2_IC4F_3 (0x00008000UL) 2524 #define TIM_CCER_CC4P_Pos (13UL) 2525 #define TIM_CCER_CC4P_Msk (0x2000UL) 2526 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk 2527 #define TIM_CCER_CC4E_Pos (12UL) 2528 #define TIM_CCER_CC4E_Msk (0x1000UL) 2529 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk 2530 #define TIM_CCER_CC3NP_Pos (11UL) 2531 #define TIM_CCER_CC3NP_Msk (0x800UL) 2532 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk 2533 #define TIM_CCER_CC3NE_Pos (10UL) 2534 #define TIM_CCER_CC3NE_Msk (0x400UL) 2535 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk 2536 #define TIM_CCER_CC3P_Pos (9UL) 2537 #define TIM_CCER_CC3P_Msk (0x200UL) 2538 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk 2539 #define TIM_CCER_CC3E_Pos (8UL) 2540 #define TIM_CCER_CC3E_Msk (0x100UL) 2541 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk 2542 #define TIM_CCER_CC2NP_Pos (7UL) 2543 #define TIM_CCER_CC2NP_Msk (0x80UL) 2544 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk 2545 #define TIM_CCER_CC2NE_Pos (6UL) 2546 #define TIM_CCER_CC2NE_Msk (0x40UL) 2547 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk 2548 #define TIM_CCER_CC2P_Pos (5UL) 2549 #define TIM_CCER_CC2P_Msk (0x20UL) 2550 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk 2551 #define TIM_CCER_CC2E_Pos (4UL) 2552 #define TIM_CCER_CC2E_Msk (0x10UL) 2553 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk 2554 #define TIM_CCER_CC1NP_Pos (3UL) 2555 #define TIM_CCER_CC1NP_Msk (0x8UL) 2556 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk 2557 #define TIM_CCER_CC1NE_Pos (2UL) 2558 #define TIM_CCER_CC1NE_Msk (0x4UL) 2559 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk 2560 #define TIM_CCER_CC1P_Pos (1UL) 2561 #define TIM_CCER_CC1P_Msk (0x2UL) 2562 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk 2563 #define TIM_CCER_CC1E_Pos (0UL) 2564 #define TIM_CCER_CC1E_Msk (0x1UL) 2565 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk 2567 #define TIM_CNT_CNT_Pos (0UL) 2568 #define TIM_CNT_CNT_Msk (0xFFFFUL) 2570 #define TIM_PSC_PSC_Pos (0UL) 2571 #define TIM_PSC_PSC_Msk (0xFFFFUL) 2573 #define TIM_ARR_ARR_Pos (0UL) 2574 #define TIM_ARR_ARR_Msk (0xFFFFUL) 2576 #define TIM_RCR_REP_Pos (0UL) 2577 #define TIM_RCR_REP_Msk (0xFFUL) 2579 #define TIM_CCR1_CCR1_Pos (0UL) 2580 #define TIM_CCR1_CCR1_Msk (0xFFFFUL) 2582 #define TIM_CCR2_CCR2_Pos (0UL) 2583 #define TIM_CCR2_CCR2_Msk (0xFFFFUL) 2585 #define TIM_CCR3_CCR3_Pos (0UL) 2586 #define TIM_CCR3_CCR3_Msk (0xFFFFUL) 2588 #define TIM_CCR4_CCR4_Pos (0UL) 2589 #define TIM_CCR4_CCR4_Msk (0xFFFFUL) 2591 #define TIM_BDTR_DTG_Pos (0UL) 2592 #define TIM_BDTR_DTG_Msk (0xFFUL) 2593 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk 2594 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) 2595 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) 2596 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) 2597 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) 2598 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) 2599 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) 2600 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) 2601 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) 2602 #define TIM_BDTR_LOCK_Pos (8UL) 2603 #define TIM_BDTR_LOCK_Msk (0x300UL) 2604 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk 2605 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) 2606 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) 2607 #define TIM_BDTR_OSSI_Pos (10UL) 2608 #define TIM_BDTR_OSSI_Msk (0x400UL) 2609 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk 2610 #define TIM_BDTR_OSSR_Pos (11UL) 2611 #define TIM_BDTR_OSSR_Msk (0x800UL) 2612 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk 2613 #define TIM_BDTR_BKE_Pos (12UL) 2614 #define TIM_BDTR_BKE_Msk (0x1000UL) 2615 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk 2616 #define TIM_BDTR_BKP_Pos (13UL) 2617 #define TIM_BDTR_BKP_Msk (0x2000UL) 2618 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk 2619 #define TIM_BDTR_AOE_Pos (14UL) 2620 #define TIM_BDTR_AOE_Msk (0x4000UL) 2621 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk 2622 #define TIM_BDTR_MOE_Pos (15UL) 2623 #define TIM_BDTR_MOE_Msk (0x8000UL) 2624 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk 2632 #define CRC_RESULT_RESULT_Pos (0UL) 2633 #define CRC_RESULT_RESULT_Msk (0xFFFFUL) 2634 #define CRC_RESULT_RESULT CRC_RESULT_RESULT_Msk 2635 #define CRC_RESULT_FLAG_Pos (16UL) 2636 #define CRC_RESULT_FLAG_Msk (0x10000UL) 2637 #define CRC_RESULT_FLAG CRC_RESULT_FLAG_Msk 2645 #define FLASH_CR_OP_Pos (0UL) 2646 #define FLASH_CR_OP_Msk (0x3UL) 2647 #define FLASH_CR_OP FLASH_CR_OP_Msk 2648 #define FLASH_CR_OP_0 (0x1 << FLASH_CR_OP_Pos) 2649 #define FLASH_CR_OP_1 (0x2 << FLASH_CR_OP_Pos) 2650 #define FLASH_CR_BUSY_Pos (2UL) 2651 #define FLASH_CR_BUSY_Msk (0x4UL) 2652 #define FLASH_CR_BUSY FLASH_CR_BUSY_Msk 2653 #define FLASH_CR_IE_Pos (3UL) 2654 #define FLASH_CR_IE_Msk (0x18UL) 2655 #define FLASH_CR_IE FLASH_CR_IE_Msk 2656 #define FLASH_CR_IE_0 (0x1 << FLASH_CR_IE_Pos) 2657 #define FLASH_CR_IE_1 (0x2 << FLASH_CR_IE_Pos) 2659 #define FLASH_IFR_IF1_Pos (1UL) 2660 #define FLASH_IFR_IF1_Msk (0x2UL) 2661 #define FLASH_IFR_IF1 FLASH_IFR_IF1_Msk 2662 #define FLASH_IFR_IF0_Pos (0UL) 2663 #define FLASH_IFR_IF0_Msk (0x1UL) 2664 #define FLASH_IFR_IF0 FLASH_IFR_IF0_Msk 2666 #define FLASH_ICLR_ICLR1_Pos (1UL) 2667 #define FLASH_ICLR_ICLR1_Msk (0x2UL) 2668 #define FLASH_ICLR_ICLR1 FLASH_ICLR_ICLR1_Msk 2669 #define FLASH_ICLR_ICLR0_Pos (0UL) 2670 #define FLASH_ICLR_ICLR0_Msk (0x1UL) 2671 #define FLASH_ICLR_ICLR0 FLASH_ICLR_ICLR0_Msk 2673 #define FLASH_BYPASS_BYPASSSEQ_Pos (0UL) 2674 #define FLASH_BYPASS_BYPASSSEQ_Msk (0xFFFFUL) 2676 #define FLASH_SLOCK0_SLOCK0_31_Pos (31UL) 2677 #define FLASH_SLOCK0_SLOCK0_31_Msk (0x80000000UL) 2678 #define FLASH_SLOCK0_SLOCK0_30_Pos (30UL) 2679 #define FLASH_SLOCK0_SLOCK0_30_Msk (0x40000000UL) 2680 #define FLASH_SLOCK0_SLOCK0_29_Pos (29UL) 2681 #define FLASH_SLOCK0_SLOCK0_29_Msk (0x20000000UL) 2682 #define FLASH_SLOCK0_SLOCK0_28_Pos (28UL) 2683 #define FLASH_SLOCK0_SLOCK0_28_Msk (0x10000000UL) 2684 #define FLASH_SLOCK0_SLOCK0_27_Pos (27UL) 2685 #define FLASH_SLOCK0_SLOCK0_27_Msk (0x8000000UL) 2686 #define FLASH_SLOCK0_SLOCK0_26_Pos (26UL) 2687 #define FLASH_SLOCK0_SLOCK0_26_Msk (0x4000000UL) 2688 #define FLASH_SLOCK0_SLOCK0_25_Pos (25UL) 2689 #define FLASH_SLOCK0_SLOCK0_25_Msk (0x2000000UL) 2690 #define FLASH_SLOCK0_SLOCK0_24_Pos (24UL) 2691 #define FLASH_SLOCK0_SLOCK0_24_Msk (0x1000000UL) 2692 #define FLASH_SLOCK0_SLOCK0_23_Pos (23UL) 2693 #define FLASH_SLOCK0_SLOCK0_23_Msk (0x800000UL) 2694 #define FLASH_SLOCK0_SLOCK0_22_Pos (22UL) 2695 #define FLASH_SLOCK0_SLOCK0_22_Msk (0x400000UL) 2696 #define FLASH_SLOCK0_SLOCK0_21_Pos (21UL) 2697 #define FLASH_SLOCK0_SLOCK0_21_Msk (0x200000UL) 2698 #define FLASH_SLOCK0_SLOCK0_20_Pos (20UL) 2699 #define FLASH_SLOCK0_SLOCK0_20_Msk (0x100000UL) 2700 #define FLASH_SLOCK0_SLOCK0_19_Pos (19UL) 2701 #define FLASH_SLOCK0_SLOCK0_19_Msk (0x80000UL) 2702 #define FLASH_SLOCK0_SLOCK0_18_Pos (18UL) 2703 #define FLASH_SLOCK0_SLOCK0_18_Msk (0x40000UL) 2704 #define FLASH_SLOCK0_SLOCK0_17_Pos (17UL) 2705 #define FLASH_SLOCK0_SLOCK0_17_Msk (0x20000UL) 2706 #define FLASH_SLOCK0_SLOCK0_16_Pos (16UL) 2707 #define FLASH_SLOCK0_SLOCK0_16_Msk (0x10000UL) 2708 #define FLASH_SLOCK0_SLOCK0_15_Pos (15UL) 2709 #define FLASH_SLOCK0_SLOCK0_15_Msk (0x8000UL) 2710 #define FLASH_SLOCK0_SLOCK0_14_Pos (14UL) 2711 #define FLASH_SLOCK0_SLOCK0_14_Msk (0x4000UL) 2712 #define FLASH_SLOCK0_SLOCK0_13_Pos (13UL) 2713 #define FLASH_SLOCK0_SLOCK0_13_Msk (0x2000UL) 2714 #define FLASH_SLOCK0_SLOCK0_12_Pos (12UL) 2715 #define FLASH_SLOCK0_SLOCK0_12_Msk (0x1000UL) 2716 #define FLASH_SLOCK0_SLOCK0_11_Pos (11UL) 2717 #define FLASH_SLOCK0_SLOCK0_11_Msk (0x800UL) 2718 #define FLASH_SLOCK0_SLOCK0_10_Pos (10UL) 2719 #define FLASH_SLOCK0_SLOCK0_10_Msk (0x400UL) 2720 #define FLASH_SLOCK0_SLOCK0_9_Pos (9UL) 2721 #define FLASH_SLOCK0_SLOCK0_9_Msk (0x200UL) 2722 #define FLASH_SLOCK0_SLOCK0_8_Pos (8UL) 2723 #define FLASH_SLOCK0_SLOCK0_8_Msk (0x100UL) 2724 #define FLASH_SLOCK0_SLOCK0_7_Pos (7UL) 2725 #define FLASH_SLOCK0_SLOCK0_7_Msk (0x80UL) 2726 #define FLASH_SLOCK0_SLOCK0_6_Pos (6UL) 2727 #define FLASH_SLOCK0_SLOCK0_6_Msk (0x40UL) 2728 #define FLASH_SLOCK0_SLOCK0_5_Pos (5UL) 2729 #define FLASH_SLOCK0_SLOCK0_5_Msk (0x20UL) 2730 #define FLASH_SLOCK0_SLOCK0_4_Pos (4UL) 2731 #define FLASH_SLOCK0_SLOCK0_4_Msk (0x10UL) 2732 #define FLASH_SLOCK0_SLOCK0_3_Pos (3UL) 2733 #define FLASH_SLOCK0_SLOCK0_3_Msk (0x8UL) 2734 #define FLASH_SLOCK0_SLOCK0_2_Pos (2UL) 2735 #define FLASH_SLOCK0_SLOCK0_2_Msk (0x4UL) 2736 #define FLASH_SLOCK0_SLOCK0_1_Pos (1UL) 2737 #define FLASH_SLOCK0_SLOCK0_1_Msk (0x2UL) 2738 #define FLASH_SLOCK0_SLOCK0_0_Pos (0UL) 2739 #define FLASH_SLOCK0_SLOCK0_0_Msk (0x1UL) 2741 #define FLASH_SLOCK1_SLOCK1_31_Pos (31UL) 2742 #define FLASH_SLOCK1_SLOCK1_31_Msk (0x80000000UL) 2743 #define FLASH_SLOCK1_SLOCK1_30_Pos (30UL) 2744 #define FLASH_SLOCK1_SLOCK1_30_Msk (0x40000000UL) 2745 #define FLASH_SLOCK1_SLOCK1_29_Pos (29UL) 2746 #define FLASH_SLOCK1_SLOCK1_29_Msk (0x20000000UL) 2747 #define FLASH_SLOCK1_SLOCK1_28_Pos (28UL) 2748 #define FLASH_SLOCK1_SLOCK1_28_Msk (0x10000000UL) 2749 #define FLASH_SLOCK1_SLOCK1_27_Pos (27UL) 2750 #define FLASH_SLOCK1_SLOCK1_27_Msk (0x8000000UL) 2751 #define FLASH_SLOCK1_SLOCK1_26_Pos (26UL) 2752 #define FLASH_SLOCK1_SLOCK1_26_Msk (0x4000000UL) 2753 #define FLASH_SLOCK1_SLOCK1_25_Pos (25UL) 2754 #define FLASH_SLOCK1_SLOCK1_25_Msk (0x2000000UL) 2755 #define FLASH_SLOCK1_SLOCK1_24_Pos (24UL) 2756 #define FLASH_SLOCK1_SLOCK1_24_Msk (0x1000000UL) 2757 #define FLASH_SLOCK1_SLOCK1_23_Pos (23UL) 2758 #define FLASH_SLOCK1_SLOCK1_23_Msk (0x800000UL) 2759 #define FLASH_SLOCK1_SLOCK1_22_Pos (22UL) 2760 #define FLASH_SLOCK1_SLOCK1_22_Msk (0x400000UL) 2761 #define FLASH_SLOCK1_SLOCK1_21_Pos (21UL) 2762 #define FLASH_SLOCK1_SLOCK1_21_Msk (0x200000UL) 2763 #define FLASH_SLOCK1_SLOCK1_20_Pos (20UL) 2764 #define FLASH_SLOCK1_SLOCK1_20_Msk (0x100000UL) 2765 #define FLASH_SLOCK1_SLOCK1_19_Pos (19UL) 2766 #define FLASH_SLOCK1_SLOCK1_19_Msk (0x80000UL) 2767 #define FLASH_SLOCK1_SLOCK1_18_Pos (18UL) 2768 #define FLASH_SLOCK1_SLOCK1_18_Msk (0x40000UL) 2769 #define FLASH_SLOCK1_SLOCK1_17_Pos (17UL) 2770 #define FLASH_SLOCK1_SLOCK1_17_Msk (0x20000UL) 2771 #define FLASH_SLOCK1_SLOCK1_16_Pos (16UL) 2772 #define FLASH_SLOCK1_SLOCK1_16_Msk (0x10000UL) 2773 #define FLASH_SLOCK1_SLOCK1_15_Pos (15UL) 2774 #define FLASH_SLOCK1_SLOCK1_15_Msk (0x8000UL) 2775 #define FLASH_SLOCK1_SLOCK1_14_Pos (14UL) 2776 #define FLASH_SLOCK1_SLOCK1_14_Msk (0x4000UL) 2777 #define FLASH_SLOCK1_SLOCK1_13_Pos (13UL) 2778 #define FLASH_SLOCK1_SLOCK1_13_Msk (0x2000UL) 2779 #define FLASH_SLOCK1_SLOCK1_12_Pos (12UL) 2780 #define FLASH_SLOCK1_SLOCK1_12_Msk (0x1000UL) 2781 #define FLASH_SLOCK1_SLOCK1_11_Pos (11UL) 2782 #define FLASH_SLOCK1_SLOCK1_11_Msk (0x800UL) 2783 #define FLASH_SLOCK1_SLOCK1_10_Pos (10UL) 2784 #define FLASH_SLOCK1_SLOCK1_10_Msk (0x400UL) 2785 #define FLASH_SLOCK1_SLOCK1_9_Pos (9UL) 2786 #define FLASH_SLOCK1_SLOCK1_9_Msk (0x200UL) 2787 #define FLASH_SLOCK1_SLOCK1_8_Pos (8UL) 2788 #define FLASH_SLOCK1_SLOCK1_8_Msk (0x100UL) 2789 #define FLASH_SLOCK1_SLOCK1_7_Pos (7UL) 2790 #define FLASH_SLOCK1_SLOCK1_7_Msk (0x80UL) 2791 #define FLASH_SLOCK1_SLOCK1_6_Pos (6UL) 2792 #define FLASH_SLOCK1_SLOCK1_6_Msk (0x40UL) 2793 #define FLASH_SLOCK1_SLOCK1_5_Pos (5UL) 2794 #define FLASH_SLOCK1_SLOCK1_5_Msk (0x20UL) 2795 #define FLASH_SLOCK1_SLOCK1_4_Pos (4UL) 2796 #define FLASH_SLOCK1_SLOCK1_4_Msk (0x10UL) 2797 #define FLASH_SLOCK1_SLOCK1_3_Pos (3UL) 2798 #define FLASH_SLOCK1_SLOCK1_3_Msk (0x8UL) 2799 #define FLASH_SLOCK1_SLOCK1_2_Pos (2UL) 2800 #define FLASH_SLOCK1_SLOCK1_2_Msk (0x4UL) 2801 #define FLASH_SLOCK1_SLOCK1_1_Pos (1UL) 2802 #define FLASH_SLOCK1_SLOCK1_1_Msk (0x2UL) 2803 #define FLASH_SLOCK1_SLOCK1_0_Pos (0UL) 2804 #define FLASH_SLOCK1_SLOCK1_0_Msk (0x1UL) 2806 #define FLASH_ISPCON_ISP_CON_Pos (0UL) 2807 #define FLASH_ISPCON_ISP_CON_Msk (0x1UL) 2815 #define GPIO_DIRCR_PxDIR7_Pos (7UL) 2816 #define GPIO_DIRCR_PxDIR7_Msk (0x80UL) 2817 #define GPIO_DIRCR_PxDIR6_Pos (6UL) 2818 #define GPIO_DIRCR_PxDIR6_Msk (0x40UL) 2819 #define GPIO_DIRCR_PxDIR5_Pos (5UL) 2820 #define GPIO_DIRCR_PxDIR5_Msk (0x20UL) 2821 #define GPIO_DIRCR_PxDIR4_Pos (4UL) 2822 #define GPIO_DIRCR_PxDIR4_Msk (0x10UL) 2823 #define GPIO_DIRCR_PxDIR3_Pos (3UL) 2824 #define GPIO_DIRCR_PxDIR3_Msk (0x8UL) 2825 #define GPIO_DIRCR_PxDIR2_Pos (2UL) 2826 #define GPIO_DIRCR_PxDIR2_Msk (0x4UL) 2827 #define GPIO_DIRCR_PxDIR1_Pos (1UL) 2828 #define GPIO_DIRCR_PxDIR1_Msk (0x2UL) 2829 #define GPIO_DIRCR_PxDIR0_Pos (0UL) 2830 #define GPIO_DIRCR_PxDIR0_Msk (0x1UL) 2831 #define GPIO_DIRCR_PxDIR0 GPIO_DIRCR_PxDIR0_Msk 2833 #define GPIO_OTYPER_PxOTYP7_Pos (7UL) 2834 #define GPIO_OTYPER_PxOTYP7_Msk (0x80UL) 2835 #define GPIO_OTYPER_PxOTYP6_Pos (6UL) 2836 #define GPIO_OTYPER_PxOTYP6_Msk (0x40UL) 2837 #define GPIO_OTYPER_PxOTYP5_Pos (5UL) 2838 #define GPIO_OTYPER_PxOTYP5_Msk (0x20UL) 2839 #define GPIO_OTYPER_PxOTYP4_Pos (4UL) 2840 #define GPIO_OTYPER_PxOTYP4_Msk (0x10UL) 2841 #define GPIO_OTYPER_PxOTYP3_Pos (3UL) 2842 #define GPIO_OTYPER_PxOTYP3_Msk (0x8UL) 2843 #define GPIO_OTYPER_PxOTYP2_Pos (2UL) 2844 #define GPIO_OTYPER_PxOTYP2_Msk (0x4UL) 2845 #define GPIO_OTYPER_PxOTYP1_Pos (1UL) 2846 #define GPIO_OTYPER_PxOTYP1_Msk (0x2UL) 2847 #define GPIO_OTYPER_PxOTYP0_Pos (0UL) 2848 #define GPIO_OTYPER_PxOTYP0_Msk (0x1UL) 2850 #define GPIO_ODR_PxOD7_Pos (7UL) 2851 #define GPIO_ODR_PxOD7_Msk (0x80UL) 2852 #define GPIO_ODR_PxOD6_Pos (6UL) 2853 #define GPIO_ODR_PxOD6_Msk (0x40UL) 2854 #define GPIO_ODR_PxOD5_Pos (5UL) 2855 #define GPIO_ODR_PxOD5_Msk (0x20UL) 2856 #define GPIO_ODR_PxOD4_Pos (4UL) 2857 #define GPIO_ODR_PxOD4_Msk (0x10UL) 2858 #define GPIO_ODR_PxOD3_Pos (3UL) 2859 #define GPIO_ODR_PxOD3_Msk (0x8UL) 2860 #define GPIO_ODR_PxOD2_Pos (2UL) 2861 #define GPIO_ODR_PxOD2_Msk (0x4UL) 2862 #define GPIO_ODR_PxOD1_Pos (1UL) 2863 #define GPIO_ODR_PxOD1_Msk (0x2UL) 2864 #define GPIO_ODR_PxOD0_Pos (0UL) 2865 #define GPIO_ODR_PxOD0_Msk (0x1UL) 2867 #define GPIO_IDR_PxID7_Pos (7UL) 2868 #define GPIO_IDR_PxID7_Msk (0x80UL) 2869 #define GPIO_IDR_PxID6_Pos (6UL) 2870 #define GPIO_IDR_PxID6_Msk (0x40UL) 2871 #define GPIO_IDR_PxID5_Pos (5UL) 2872 #define GPIO_IDR_PxID5_Msk (0x20UL) 2873 #define GPIO_IDR_PxID4_Pos (4UL) 2874 #define GPIO_IDR_PxID4_Msk (0x10UL) 2875 #define GPIO_IDR_PxID3_Pos (3UL) 2876 #define GPIO_IDR_PxID3_Msk (0x8UL) 2877 #define GPIO_IDR_PxID2_Pos (2UL) 2878 #define GPIO_IDR_PxID2_Msk (0x4UL) 2879 #define GPIO_IDR_PxID1_Pos (1UL) 2880 #define GPIO_IDR_PxID1_Msk (0x2UL) 2881 #define GPIO_IDR_PxID0_Pos (0UL) 2882 #define GPIO_IDR_PxID0_Msk (0x1UL) 2884 #define GPIO_INTEN_PxIEN7_Pos (7UL) 2885 #define GPIO_INTEN_PxIEN7_Msk (0x80UL) 2886 #define GPIO_INTEN_PxIEN6_Pos (6UL) 2887 #define GPIO_INTEN_PxIEN6_Msk (0x40UL) 2888 #define GPIO_INTEN_PxIEN5_Pos (5UL) 2889 #define GPIO_INTEN_PxIEN5_Msk (0x20UL) 2890 #define GPIO_INTEN_PxIEN4_Pos (4UL) 2891 #define GPIO_INTEN_PxIEN4_Msk (0x10UL) 2892 #define GPIO_INTEN_PxIEN3_Pos (3UL) 2893 #define GPIO_INTEN_PxIEN3_Msk (0x8UL) 2894 #define GPIO_INTEN_PxIEN2_Pos (2UL) 2895 #define GPIO_INTEN_PxIEN2_Msk (0x4UL) 2896 #define GPIO_INTEN_PxIEN1_Pos (1UL) 2897 #define GPIO_INTEN_PxIEN1_Msk (0x2UL) 2898 #define GPIO_INTEN_PxIEN0_Pos (0UL) 2899 #define GPIO_INTEN_PxIEN0_Msk (0x1UL) 2900 #define GPIO_INTEN_PxIEN0 GPIO_INTEN_PxIEN0_Msk 2903 #define GPIO_RAWINTST_PxRIS7_Pos (7UL) 2904 #define GPIO_RAWINTST_PxRIS7_Msk (0x80UL) 2905 #define GPIO_RAWINTST_PxRIS6_Pos (6UL) 2906 #define GPIO_RAWINTST_PxRIS6_Msk (0x40UL) 2907 #define GPIO_RAWINTST_PxRIS5_Pos (5UL) 2908 #define GPIO_RAWINTST_PxRIS5_Msk (0x20UL) 2909 #define GPIO_RAWINTST_PxRIS4_Pos (4UL) 2910 #define GPIO_RAWINTST_PxRIS4_Msk (0x10UL) 2911 #define GPIO_RAWINTST_PxRIS3_Pos (3UL) 2912 #define GPIO_RAWINTST_PxRIS3_Msk (0x8UL) 2913 #define GPIO_RAWINTST_PxRIS2_Pos (2UL) 2914 #define GPIO_RAWINTST_PxRIS2_Msk (0x4UL) 2915 #define GPIO_RAWINTST_PxRIS1_Pos (1UL) 2916 #define GPIO_RAWINTST_PxRIS1_Msk (0x2UL) 2917 #define GPIO_RAWINTST_PxRIS0_Pos (0UL) 2918 #define GPIO_RAWINTST_PxRIS0_Msk (0x1UL) 2920 #define GPIO_MSKINTCR_PxMIS7_Pos (7UL) 2921 #define GPIO_MSKINTCR_PxMIS7_Msk (0x80UL) 2922 #define GPIO_MSKINTCR_PxMIS6_Pos (6UL) 2923 #define GPIO_MSKINTCR_PxMIS6_Msk (0x40UL) 2924 #define GPIO_MSKINTCR_PxMIS5_Pos (5UL) 2925 #define GPIO_MSKINTCR_PxMIS5_Msk (0x20UL) 2926 #define GPIO_MSKINTCR_PxMIS4_Pos (4UL) 2927 #define GPIO_MSKINTCR_PxMIS4_Msk (0x10UL) 2928 #define GPIO_MSKINTCR_PxMIS3_Pos (3UL) 2929 #define GPIO_MSKINTCR_PxMIS3_Msk (0x8UL) 2930 #define GPIO_MSKINTCR_PxMIS2_Pos (2UL) 2931 #define GPIO_MSKINTCR_PxMIS2_Msk (0x4UL) 2932 #define GPIO_MSKINTCR_PxMIS1_Pos (1UL) 2933 #define GPIO_MSKINTCR_PxMIS1_Msk (0x2UL) 2934 #define GPIO_MSKINTCR_PxMIS0_Pos (0UL) 2935 #define GPIO_MSKINTCR_PxMIS0_Msk (0x1UL) 2937 #define GPIO_INTCLR_PxICLR7_Pos (7UL) 2938 #define GPIO_INTCLR_PxICLR7_Msk (0x80UL) 2939 #define GPIO_INTCLR_PxICLR6_Pos (6UL) 2940 #define GPIO_INTCLR_PxICLR6_Msk (0x40UL) 2941 #define GPIO_INTCLR_PxICLR5_Pos (5UL) 2942 #define GPIO_INTCLR_PxICLR5_Msk (0x20UL) 2943 #define GPIO_INTCLR_PxICLR4_Pos (4UL) 2944 #define GPIO_INTCLR_PxICLR4_Msk (0x10UL) 2945 #define GPIO_INTCLR_PxICLR3_Pos (3UL) 2946 #define GPIO_INTCLR_PxICLR3_Msk (0x8UL) 2947 #define GPIO_INTCLR_PxICLR2_Pos (2UL) 2948 #define GPIO_INTCLR_PxICLR2_Msk (0x4UL) 2949 #define GPIO_INTCLR_PxICLR1_Pos (1UL) 2950 #define GPIO_INTCLR_PxICLR1_Msk (0x2UL) 2951 #define GPIO_INTCLR_PxICLR0_Pos (0UL) 2952 #define GPIO_INTCLR_PxICLR0_Msk (0x1UL) 2954 #define GPIO_INTTYPCR_PxITYPE7_Pos (7UL) 2955 #define GPIO_INTTYPCR_PxITYPE7_Msk (0x80UL) 2956 #define GPIO_INTTYPCR_PxITYPE6_Pos (6UL) 2957 #define GPIO_INTTYPCR_PxITYPE6_Msk (0x40UL) 2958 #define GPIO_INTTYPCR_PxITYPE5_Pos (5UL) 2959 #define GPIO_INTTYPCR_PxITYPE5_Msk (0x20UL) 2960 #define GPIO_INTTYPCR_PxITYPE4_Pos (4UL) 2961 #define GPIO_INTTYPCR_PxITYPE4_Msk (0x10UL) 2962 #define GPIO_INTTYPCR_PxITYPE3_Pos (3UL) 2963 #define GPIO_INTTYPCR_PxITYPE3_Msk (0x8UL) 2964 #define GPIO_INTTYPCR_PxITYPE2_Pos (2UL) 2965 #define GPIO_INTTYPCR_PxITYPE2_Msk (0x4UL) 2966 #define GPIO_INTTYPCR_PxITYPE1_Pos (1UL) 2967 #define GPIO_INTTYPCR_PxITYPE1_Msk (0x2UL) 2968 #define GPIO_INTTYPCR_PxITYPE0_Pos (0UL) 2969 #define GPIO_INTTYPCR_PxITYPE0_Msk (0x1UL) 2970 #define GPIO_INTTYPCR_PxITYPE0 GPIO_INTTYPCR_PxITYPE0_Msk 2972 #define GPIO_INTPOLCR_PxIVAL7_Pos (7UL) 2973 #define GPIO_INTPOLCR_PxIVAL7_Msk (0x80UL) 2974 #define GPIO_INTPOLCR_PxIVAL6_Pos (6UL) 2975 #define GPIO_INTPOLCR_PxIVAL6_Msk (0x40UL) 2976 #define GPIO_INTPOLCR_PxIVAL5_Pos (5UL) 2977 #define GPIO_INTPOLCR_PxIVAL5_Msk (0x20UL) 2978 #define GPIO_INTPOLCR_PxIVAL4_Pos (4UL) 2979 #define GPIO_INTPOLCR_PxIVAL4_Msk (0x10UL) 2980 #define GPIO_INTPOLCR_PxIVAL3_Pos (3UL) 2981 #define GPIO_INTPOLCR_PxIVAL3_Msk (0x8UL) 2982 #define GPIO_INTPOLCR_PxIVAL2_Pos (2UL) 2983 #define GPIO_INTPOLCR_PxIVAL2_Msk (0x4UL) 2984 #define GPIO_INTPOLCR_PxIVAL1_Pos (1UL) 2985 #define GPIO_INTPOLCR_PxIVAL1_Msk (0x2UL) 2986 #define GPIO_INTPOLCR_PxIVAL0_Pos (0UL) 2987 #define GPIO_INTPOLCR_PxIVAL0_Msk (0x1UL) 2988 #define GPIO_INTPOLCR_PxIVAL0 GPIO_INTPOLCR_PxIVAL0_Msk 2990 #define GPIO_INTANY_PxIANY7_Pos (7UL) 2991 #define GPIO_INTANY_PxIANY7_Msk (0x80UL) 2992 #define GPIO_INTANY_PxIANY6_Pos (6UL) 2993 #define GPIO_INTANY_PxIANY6_Msk (0x40UL) 2994 #define GPIO_INTANY_PxIANY5_Pos (5UL) 2995 #define GPIO_INTANY_PxIANY5_Msk (0x20UL) 2996 #define GPIO_INTANY_PxIANY4_Pos (4UL) 2997 #define GPIO_INTANY_PxIANY4_Msk (0x10UL) 2998 #define GPIO_INTANY_PxIANY3_Pos (3UL) 2999 #define GPIO_INTANY_PxIANY3_Msk (0x8UL) 3000 #define GPIO_INTANY_PxIANY2_Pos (2UL) 3001 #define GPIO_INTANY_PxIANY2_Msk (0x4UL) 3002 #define GPIO_INTANY_PxIANY1_Pos (1UL) 3003 #define GPIO_INTANY_PxIANY1_Msk (0x2UL) 3004 #define GPIO_INTANY_PxIANY0_Pos (0UL) 3005 #define GPIO_INTANY_PxIANY0_Msk (0x1UL) 3006 #define GPIO_INTANY_PxIANY0 GPIO_INTANY_PxIANY0_Msk 3008 #define GPIO_ODSET_PxODSET7_Pos (7UL) 3009 #define GPIO_ODSET_PxODSET7_Msk (0x80UL) 3010 #define GPIO_ODSET_PxODSET6_Pos (6UL) 3011 #define GPIO_ODSET_PxODSET6_Msk (0x40UL) 3012 #define GPIO_ODSET_PxODSET5_Pos (5UL) 3013 #define GPIO_ODSET_PxODSET5_Msk (0x20UL) 3014 #define GPIO_ODSET_PxODSET4_Pos (4UL) 3015 #define GPIO_ODSET_PxODSET4_Msk (0x10UL) 3016 #define GPIO_ODSET_PxODSET3_Pos (3UL) 3017 #define GPIO_ODSET_PxODSET3_Msk (0x8UL) 3018 #define GPIO_ODSET_PxODSET2_Pos (2UL) 3019 #define GPIO_ODSET_PxODSET2_Msk (0x4UL) 3020 #define GPIO_ODSET_PxODSET1_Pos (1UL) 3021 #define GPIO_ODSET_PxODSET1_Msk (0x2UL) 3022 #define GPIO_ODSET_PxODSET0_Pos (0UL) 3023 #define GPIO_ODSET_PxODSET0_Msk (0x1UL) 3025 #define GPIO_ODCLR_PxODCLR7_Pos (7UL) 3026 #define GPIO_ODCLR_PxODCLR7_Msk (0x80UL) 3027 #define GPIO_ODCLR_PxODCLR6_Pos (6UL) 3028 #define GPIO_ODCLR_PxODCLR6_Msk (0x40UL) 3029 #define GPIO_ODCLR_PxODCLR5_Pos (5UL) 3030 #define GPIO_ODCLR_PxODCLR5_Msk (0x20UL) 3031 #define GPIO_ODCLR_PxODCLR4_Pos (4UL) 3032 #define GPIO_ODCLR_PxODCLR4_Msk (0x10UL) 3033 #define GPIO_ODCLR_PxODCLR3_Pos (3UL) 3034 #define GPIO_ODCLR_PxODCLR3_Msk (0x8UL) 3035 #define GPIO_ODCLR_PxODCLR2_Pos (2UL) 3036 #define GPIO_ODCLR_PxODCLR2_Msk (0x4UL) 3037 #define GPIO_ODCLR_PxODCLR1_Pos (1UL) 3038 #define GPIO_ODCLR_PxODCLR1_Msk (0x2UL) 3039 #define GPIO_ODCLR_PxODCLR0_Pos (0UL) 3040 #define GPIO_ODCLR_PxODCLR0_Msk (0x1UL) 3042 #define GPIO_INDBEN_PxDIDB_Pos (0UL) 3043 #define GPIO_INDBEN_PxDIDB_Msk (0xFFUL) 3044 #define GPIO_INDBEN_PxDIDB GPIO_INDBEN_PxDIDB_Msk 3045 #define GPIO_INDBEN_SYNC_EN_Pos (8UL) 3046 #define GPIO_INDBEN_SYNC_EN_Msk (0x100UL) 3047 #define GPIO_INDBEN_SYNC_EN GPIO_INDBEN_SYNC_EN_Msk 3049 #define GPIO_DBCLKCR_DBCLK_DIV_Pos (0UL) 3050 #define GPIO_DBCLKCR_DBCLK_DIV_Msk (0xFUL) 3051 #define GPIO_DBCLKCR_DBCLK_DIV GPIO_DBCLKCR_DBCLK_DIV_Msk 3052 #define GPIO_DBCLKCR_DBCLKEN_Pos (4UL) 3053 #define GPIO_DBCLKCR_DBCLKEN_Msk (0x10UL) 3054 #define GPIO_DBCLKCR_DBCLKEN GPIO_DBCLKCR_DBCLKEN_Msk 3056 #define GPIO_PUPDR_PxPUPD7_Pos (14UL) 3057 #define GPIO_PUPDR_PxPUPD7_Msk (0xC000UL) 3058 #define GPIO_PUPDR_PxPUPD6_Pos (12UL) 3059 #define GPIO_PUPDR_PxPUPD6_Msk (0x3000UL) 3060 #define GPIO_PUPDR_PxPUPD5_Pos (10UL) 3061 #define GPIO_PUPDR_PxPUPD5_Msk (0xC00UL) 3062 #define GPIO_PUPDR_PxPUPD4_Pos (8UL) 3063 #define GPIO_PUPDR_PxPUPD4_Msk (0x300UL) 3064 #define GPIO_PUPDR_PxPUPD3_Pos (6UL) 3065 #define GPIO_PUPDR_PxPUPD3_Msk (0xC0UL) 3066 #define GPIO_PUPDR_PxPUPD2_Pos (4UL) 3067 #define GPIO_PUPDR_PxPUPD2_Msk (0x30UL) 3068 #define GPIO_PUPDR_PxPUPD1_Pos (2UL) 3069 #define GPIO_PUPDR_PxPUPD1_Msk (0xCUL) 3070 #define GPIO_PUPDR_PxPUPD0_Pos (0UL) 3071 #define GPIO_PUPDR_PxPUPD0_Msk (0x3UL) 3072 #define GPIO_PUPDR_PxPUPD0 GPIO_PUPDR_PxPUPD0_Msk 3074 #define GPIO_SLEWCR_PxSR7_Pos (7UL) 3075 #define GPIO_SLEWCR_PxSR7_Msk (0x80UL) 3076 #define GPIO_SLEWCR_PxSR6_Pos (6UL) 3077 #define GPIO_SLEWCR_PxSR6_Msk (0x40UL) 3078 #define GPIO_SLEWCR_PxSR5_Pos (5UL) 3079 #define GPIO_SLEWCR_PxSR5_Msk (0x20UL) 3080 #define GPIO_SLEWCR_PxSR4_Pos (4UL) 3081 #define GPIO_SLEWCR_PxSR4_Msk (0x10UL) 3082 #define GPIO_SLEWCR_PxSR3_Pos (3UL) 3083 #define GPIO_SLEWCR_PxSR3_Msk (0x8UL) 3084 #define GPIO_SLEWCR_PxSR2_Pos (2UL) 3085 #define GPIO_SLEWCR_PxSR2_Msk (0x4UL) 3086 #define GPIO_SLEWCR_PxSR1_Pos (1UL) 3087 #define GPIO_SLEWCR_PxSR1_Msk (0x2UL) 3088 #define GPIO_SLEWCR_PASR0_Pos (0UL) 3089 #define GPIO_SLEWCR_PASR0_Msk (0x1UL) 3090 #define GPIO_SLEWCR_PASR0 GPIO_SLEWCR_PASR0_Msk 3092 #define GPIO_DRVCR_PxDRV7_Pos (7UL) 3093 #define GPIO_DRVCR_PxDRV7_Msk (0x80UL) 3094 #define GPIO_DRVCR_PxDRV6_Pos (6UL) 3095 #define GPIO_DRVCR_PxDRV6_Msk (0x40UL) 3096 #define GPIO_DRVCR_PxDRV5_Pos (5UL) 3097 #define GPIO_DRVCR_PxDRV5_Msk (0x20UL) 3098 #define GPIO_DRVCR_PxDRV4_Pos (4UL) 3099 #define GPIO_DRVCR_PxDRV4_Msk (0x10UL) 3100 #define GPIO_DRVCR_PxDRV3_Pos (3UL) 3101 #define GPIO_DRVCR_PxDRV3_Msk (0x8UL) 3102 #define GPIO_DRVCR_PxDRV2_Pos (2UL) 3103 #define GPIO_DRVCR_PxDRV2_Msk (0x4UL) 3104 #define GPIO_DRVCR_PxDRV1_Pos (1UL) 3105 #define GPIO_DRVCR_PxDRV1_Msk (0x2UL) 3106 #define GPIO_DRVCR_PxDRV0_Pos (0UL) 3107 #define GPIO_DRVCR_PxDRV0_Msk (0x1UL) 3108 #define GPIO_DRVCR_PxDRV0 GPIO_DRVCR_PxDRV0_Msk 3110 #define GPIO_AFR_PxAFR7_Pos (28UL) 3111 #define GPIO_AFR_PxAFR7_Msk (0xF000000UL) 3112 #define GPIO_AFR_PxAFR6_Pos (24UL) 3113 #define GPIO_AFR_PxAFR6_Msk (0xF000000UL) 3114 #define GPIO_AFR_PxAFR5_Pos (20UL) 3115 #define GPIO_AFR_PxAFR5_Msk (0xF00000UL) 3116 #define GPIO_AFR_PxAFR4_Pos (16UL) 3117 #define GPIO_AFR_PxAFR4_Msk (0xF0000UL) 3118 #define GPIO_AFR_PxAFR3_Pos (12UL) 3119 #define GPIO_AFR_PxAFR3_Msk (0xF000UL) 3120 #define GPIO_AFR_PxAFR2_Pos (8UL) 3121 #define GPIO_AFR_PxAFR2_Msk (0xF00UL) 3122 #define GPIO_AFR_PxAFR1_Pos (4UL) 3123 #define GPIO_AFR_PxAFR1_Msk (0xF0UL) 3124 #define GPIO_AFR_PxAFR0_Pos (0UL) 3125 #define GPIO_AFR_PxAFR0_Msk (0x0FUL) 3126 #define GPIO_AFR_PxAFR0 GPIO_AFR_PxAFR0_Msk 3134 #define SYSCON_CFGR0_LOCKUPEN_Pos (0UL) 3135 #define SYSCON_CFGR0_LOCKUPEN_Msk (0x1UL) 3136 #define SYSCON_CFGR0_LOCKUPEN SYSCON_CFGR0_LOCKUPEN_Msk 3137 #define SYSCON_CFGR0_DBGDLSP_DIS_Pos (1UL) 3138 #define SYSCON_CFGR0_DBGDLSP_DIS_Msk (0x2UL) 3139 #define SYSCON_CFGR0_DBGDLSP_DIS SYSCON_CFGR0_DBGDLSP_DIS_Msk 3140 #define SYSCON_CFGR0_KEY_Pos (16UL) 3141 #define SYSCON_CFGR0_KEY_Msk (0xFFFF0000UL) 3142 #define SYSCON_CFGR0_KEY (0x5A69UL) 3144 #define SYSCON_PORTINTCR_PADINTSEL_Pos (0UL) 3145 #define SYSCON_PORTINTCR_PADINTSEL_Msk (0x1UL) 3146 #define SYSCON_PORTINTCR_PADINTSEL SYSCON_PORTINTCR_PADINTSEL_Msk 3147 #define SYSCON_PORTINTCR_PADDLSPCON_Pos (1UL) 3148 #define SYSCON_PORTINTCR_PADDLSPCON_Msk (0x2UL) 3149 #define SYSCON_PORTINTCR_PADDLSPCON SYSCON_PORTINTCR_PADDLSPCON_Msk 3150 #define SYSCON_PORTINTCR_KEY_Pos (16UL) 3151 #define SYSCON_PORTINTCR_KEY_Msk (0xFFFF0000UL) 3152 #define SYSCON_PORTINTCR_KEY SYSCON_PORTINTCR_KEY_Msk 3155 #define SYSCON_PORTCR_SPINCS_SEL_Pos (0UL) 3156 #define SYSCON_PORTCR_SPINCS_SEL_Msk (0xFUL) 3157 #define SYSCON_PORTCR_SPINCS_SEL SYSCON_PORTCR_SPINCS_SEL_Msk 3158 #elif defined(MG32L003Kx) 3159 #define SYSCON_PORTCR_SPINCS_SEL_Pos (0UL) 3160 #define SYSCON_PORTCR_SPINCS_SEL_Msk (0x40FUL) 3161 #define SYSCON_PORTCR_SPINCS_SEL SYSCON_PORTCR_SPINCS_SEL_Msk 3163 #define SYSCON_PORTCR_TIM10_GATE_SEL_Pos (4UL) 3164 #define SYSCON_PORTCR_TIM10_GATE_SEL_Msk (0x30UL) 3165 #define SYSCON_PORTCR_TIM10_GATE_SEL SYSCON_PORTCR_TIM10_GATE_SEL_Msk 3166 #define SYSCON_PORTCR_TIM11_GATE_SEL_Pos (6UL) 3167 #define SYSCON_PORTCR_TIM11_GATE_SEL_Msk (0xC0UL) 3168 #define SYSCON_PORTCR_TIM11_GATE_SEL SYSCON_PORTCR_TIM11_GATE_SEL_Msk 3169 #define SYSCON_PORTCR_LPTIM_GATE_SEL_Pos (8UL) 3170 #define SYSCON_PORTCR_LPTIM_GATE_SEL_Msk (0x300UL) 3171 #define SYSCON_PORTCR_LPTIM_GATE_SEL SYSCON_PORTCR_LPTIM_GATE_SEL_Msk 3173 #define SYSCON_PCACR_PCA_CAP0_SEL_Pos (0UL) 3174 #define SYSCON_PCACR_PCA_CAP0_SEL_Msk (0x3UL) 3175 #define SYSCON_PCACR_PCA_CAP0_SEL SYSCON_PCACR_PCA_CAP0_SEL_Msk 3176 #define SYSCON_PCACR_PCA_CAP1_SEL_Pos (2UL) 3177 #define SYSCON_PCACR_PCA_CAP1_SEL_Msk (0xCUL) 3178 #define SYSCON_PCACR_PCA_CAP1_SEL SYSCON_PCACR_PCA_CAP1_SEL_Msk 3179 #define SYSCON_PCACR_PCA_CAP2_SEL_Pos (4UL) 3180 #define SYSCON_PCACR_PCA_CAP2_SEL_Msk (0x30UL) 3181 #define SYSCON_PCACR_PCA_CAP2_SEL SYSCON_PCACR_PCA_CAP2_SEL_Msk 3182 #define SYSCON_PCACR_PCA_CAP3_SEL_Pos (6UL) 3183 #define SYSCON_PCACR_PCA_CAP3_SEL_Msk (0xC0UL) 3184 #define SYSCON_PCACR_PCA_CAP3_SEL SYSCON_PCACR_PCA_CAP3_SEL_Msk 3185 #define SYSCON_PCACR_PCA_CAP4_SEL_Pos (8UL) 3186 #define SYSCON_PCACR_PCA_CAP4_SEL_Msk (0x300UL) 3187 #define SYSCON_PCACR_PCA_CAP4_SEL SYSCON_PCACR_PCA_CAP4_SEL_Msk 3189 #define SYSCON_TIM1CR_TIM1CH1IN_SEL_Pos (0UL) 3190 #define SYSCON_TIM1CR_TIM1CH1IN_SEL_Msk (0x7UL) 3191 #define SYSCON_TIM1CR_TIM1CH1IN_SEL SYSCON_TIM1CR_TIM1CH1IN_SEL_Msk 3192 #define SYSCON_TIM1CR_TIM1CH2IN_SEL_Pos (4UL) 3193 #define SYSCON_TIM1CR_TIM1CH2IN_SEL_Msk (0x70UL) 3194 #define SYSCON_TIM1CR_TIM1CH2IN_SEL SYSCON_TIM1CR_TIM1CH2IN_SEL_Msk 3195 #define SYSCON_TIM1CR_TIM1CH3IN_SEL_Pos (8UL) 3196 #define SYSCON_TIM1CR_TIM1CH3IN_SEL_Msk (0x700UL) 3197 #define SYSCON_TIM1CR_TIM1CH3IN_SEL SYSCON_TIM1CR_TIM1CH3IN_SEL_Msk 3198 #define SYSCON_TIM1CR_TIM1CH4IN_SEL_Pos (12UL) 3199 #define SYSCON_TIM1CR_TIM1CH4IN_SEL_Msk (0x7000UL) 3200 #define SYSCON_TIM1CR_TIM1CH4IN_SEL SYSCON_TIM1CR_TIM1CH4IN_SEL_Msk 3202 #define SYSCON_TIM1CR_TIM1ETR_SEL_Pos (16UL) 3203 #define SYSCON_TIM1CR_TIM1ETR_SEL_Msk (0xF0000UL) 3204 #define SYSCON_TIM1CR_TIM1ETR_SEL SYSCON_TIM1CR_TIM1ETR_SEL_Msk 3205 #elif defined(MG32L003Kx) 3206 #define SYSCON_TIM1CR_TIM1ETR_SEL_Pos (16UL) 3207 #define SYSCON_TIM1CR_TIM1ETR_SEL_Msk (0x8F0000UL) 3208 #define SYSCON_TIM1CR_TIM1ETR_SEL SYSCON_TIM1CR_TIM1ETR_SEL_Msk 3210 #define SYSCON_TIM1CR_TIM1BRKOUTCFG_Pos (20UL) 3211 #define SYSCON_TIM1CR_TIM1BRKOUTCFG_Msk (0x100000UL) 3212 #define SYSCON_TIM1CR_TIM1BRKOUTCFG SYSCON_TIM1CR_TIM1BRKOUTCFG_Msk 3213 #define SYSCON_TIM1CR_DSLPBRKEN_Pos (21UL) 3214 #define SYSCON_TIM1CR_DSLPBRKEN_Msk (0x200000UL) 3215 #define SYSCON_TIM1CR_DSLPBRKEN SYSCON_TIM1CR_DSLPBRKEN_Msk 3216 #define SYSCON_TIM1CR_CLKFAILBRKEN_Pos (22UL) 3217 #define SYSCON_TIM1CR_CLKFAILBRKEN_Msk (0x400000UL) 3218 #define SYSCON_TIM1CR_CLKFAILBRKEN SYSCON_TIM1CR_CLKFAILBRKEN_Msk 3220 #define SYSCON_TIM2CR_TIM2CH1IN_SEL_Pos (0UL) 3221 #define SYSCON_TIM2CR_TIM2CH1IN_SEL_Msk (0x7UL) 3222 #define SYSCON_TIM2CR_TIM2CH1IN_SEL SYSCON_TIM2CR_TIM2CH1IN_SEL_Msk 3223 #define SYSCON_TIM2CR_TIM2CH2IN_SEL_Pos (4UL) 3224 #define SYSCON_TIM2CR_TIM2CH2IN_SEL_Msk (0x70UL) 3225 #define SYSCON_TIM2CR_TIM2CH2IN_SEL SYSCON_TIM2CR_TIM2CH2IN_SEL_Msk 3226 #define SYSCON_TIM2CR_TIM2CH3IN_SEL_Pos (8UL) 3227 #define SYSCON_TIM2CR_TIM2CH3IN_SEL_Msk (0x700UL) 3228 #define SYSCON_TIM2CR_TIM2CH3IN_SEL SYSCON_TIM2CR_TIM2CH3IN_SEL_Msk 3229 #define SYSCON_TIM2CR_TIM2CH4IN_SEL_Pos (12UL) 3230 #define SYSCON_TIM2CR_TIM2CH4IN_SEL_Msk (0x7000UL) 3231 #define SYSCON_TIM2CR_TIM2CH4IN_SEL SYSCON_TIM2CR_TIM2CH4IN_SEL_Msk 3233 #define SYSCON_TIM2CR_TIM2ETR_SEL_Pos (16UL) 3234 #define SYSCON_TIM2CR_TIM2ETR_SEL_Msk (0xF0000UL) 3235 #define SYSCON_TIM2CR_TIM2ETR_SEL SYSCON_TIM2CR_TIM2ETR_SEL_Msk 3236 #elif defined(MG32L003Kx) 3237 #define SYSCON_TIM2CR_TIM2ETR_SEL_Pos (16UL) 3238 #define SYSCON_TIM2CR_TIM2ETR_SEL_Msk (0x8F0000UL) 3239 #define SYSCON_TIM2CR_TIM2ETR_SEL SYSCON_TIM2CR_TIM2ETR_SEL_Msk 3242 #define SYSCON_UNLOCK_UNLOCK_Pos (0UL) 3243 #define SYSCON_UNLOCK_UNLOCK_Msk (0x1UL) 3244 #define SYSCON_UNLOCK_UNLOCK SYSCON_UNLOCK_UNLOCK_Msk 3245 #define SYSCON_UNLOCK_KEY_Pos (1UL) 3246 #define SYSCON_UNLOCK_KEY_Msk (0xFFFFFFFEUL) 3247 #define SYSCON_UNLOCK_KEY SYSCON_UNLOCK_KEY_Msk 3255 #define RCC_HCLKDIV_AHBCKDIV_Pos (0UL) 3256 #define RCC_HCLKDIV_AHBCKDIV_Msk (0xFFUL) 3257 #define RCC_HCLKDIV_AHBCKDIV RCC_HCLKDIV_AHBCKDIV_Msk 3258 #define RCC_HCLKDIV_AHBCKDIV_1 (0x00000000) 3260 #define RCC_PCLKDIV_APBCKDIV_Pos (0UL) 3261 #define RCC_PCLKDIV_APBCKDIV_Msk (0xFFUL) 3262 #define RCC_PCLKDIV_APBCKDIV RCC_PCLKDIV_APBCKDIV_Msk 3263 #define RCC_PCLKDIV_APBCKDIV_1 (0x00000000) 3265 #define RCC_HCLKEN_GPIOACKEN_Pos (0UL) 3266 #define RCC_HCLKEN_GPIOACKEN_Msk (0x1UL) 3267 #define RCC_HCLKEN_GPIOACKEN RCC_HCLKEN_GPIOACKEN_Msk 3268 #define RCC_HCLKEN_GPIOBCKEN_Pos (1UL) 3269 #define RCC_HCLKEN_GPIOBCKEN_Msk (0x2UL) 3270 #define RCC_HCLKEN_GPIOBCKEN RCC_HCLKEN_GPIOBCKEN_Msk 3271 #define RCC_HCLKEN_GPIOCCKEN_Pos (2UL) 3272 #define RCC_HCLKEN_GPIOCCKEN_Msk (0x4UL) 3273 #define RCC_HCLKEN_GPIOCCKEN RCC_HCLKEN_GPIOCCKEN_Msk 3274 #define RCC_HCLKEN_GPIODCKEN_Pos (3UL) 3275 #define RCC_HCLKEN_GPIODCKEN_Msk (0x8UL) 3276 #define RCC_HCLKEN_GPIODCKEN RCC_HCLKEN_GPIODCKEN_Msk 3277 #define RCC_HCLKEN_CRCCKEN_Pos (4UL) 3278 #define RCC_HCLKEN_CRCCKEN_Msk (0x10UL) 3279 #define RCC_HCLKEN_CRCCKEN RCC_HCLKEN_CRCCKEN_Msk 3280 #define RCC_HCLKEN_FLASHCKEN_Pos (8UL) 3281 #define RCC_HCLKEN_FLASHCKEN_Msk (0x100UL) 3282 #define RCC_HCLKEN_FLASHCKEN RCC_HCLKEN_FLASHCKEN_Msk 3284 #define RCC_PCLKEN_UART1CKEN_Pos (0UL) 3285 #define RCC_PCLKEN_UART1CKEN_Msk (0x1UL) 3286 #define RCC_PCLKEN_UART1CKEN RCC_PCLKEN_UART1CKEN_Msk 3287 #define RCC_PCLKEN_UART2CKEN_Pos (1UL) 3288 #define RCC_PCLKEN_UART2CKEN_Msk (0x2UL) 3289 #define RCC_PCLKEN_UART2CKEN RCC_PCLKEN_UART2CKEN_Msk 3290 #define RCC_PCLKEN_I2CCKEN_Pos (2UL) 3291 #define RCC_PCLKEN_I2CCKEN_Msk (0x4UL) 3292 #define RCC_PCLKEN_I2CCKEN RCC_PCLKEN_I2CCKEN_Msk 3293 #define RCC_PCLKEN_LPUARTCKEN_Pos (3UL) 3294 #define RCC_PCLKEN_LPUARTCKEN_Msk (0x8UL) 3295 #define RCC_PCLKEN_LPUARTCKEN RCC_PCLKEN_LPUARTCKEN_Msk 3296 #define RCC_PCLKEN_SPICKEN_Pos (4UL) 3297 #define RCC_PCLKEN_SPICKEN_Msk (0x10UL) 3298 #define RCC_PCLKEN_SPICKEN RCC_PCLKEN_SPICKEN_Msk 3299 #define RCC_PCLKEN_LPTIMCKEN_Pos (5UL) 3300 #define RCC_PCLKEN_LPTIMCKEN_Msk (0x20UL) 3301 #define RCC_PCLKEN_LPTIMCKEN RCC_PCLKEN_LPTIMCKEN_Msk 3302 #define RCC_PCLKEN_BASETIMCKEN_Pos (6UL) 3303 #define RCC_PCLKEN_BASETIMCKEN_Msk (0x40UL) 3304 #define RCC_PCLKEN_BASETIMCKEN RCC_PCLKEN_BASETIMCKEN_Msk 3305 #define RCC_PCLKEN_SYSCONCKEN_Pos (7UL) 3306 #define RCC_PCLKEN_SYSCONCKEN_Msk (0x80UL) 3307 #define RCC_PCLKEN_SYSCONCKEN RCC_PCLKEN_SYSCONCKEN_Msk 3308 #define RCC_PCLKEN_PCACKEN_Pos (8UL) 3309 #define RCC_PCLKEN_PCACKEN_Msk (0x100UL) 3310 #define RCC_PCLKEN_PCACKEN RCC_PCLKEN_PCACKEN_Msk 3311 #define RCC_PCLKEN_OWIRECKEN_Pos (9UL) 3312 #define RCC_PCLKEN_OWIRECKEN_Msk (0x200UL) 3313 #define RCC_PCLKEN_OWIRECKEN RCC_PCLKEN_OWIRECKEN_Msk 3314 #define RCC_PCLKEN_TIM1CKEN_Pos (10UL) 3315 #define RCC_PCLKEN_TIM1CKEN_Msk (0x400UL) 3316 #define RCC_PCLKEN_TIM1CKEN RCC_PCLKEN_TIM1CKEN_Msk 3317 #define RCC_PCLKEN_TIM2CKEN_Pos (11UL) 3318 #define RCC_PCLKEN_TIM2CKEN_Msk (0x800UL) 3319 #define RCC_PCLKEN_TIM2CKEN RCC_PCLKEN_TIM2CKEN_Msk 3320 #define RCC_PCLKEN_WWDGCKEN_Pos (12UL) 3321 #define RCC_PCLKEN_WWDGCKEN_Msk (0x1000UL) 3322 #define RCC_PCLKEN_WWDGCKEN RCC_PCLKEN_WWDGCKEN_Msk 3323 #define RCC_PCLKEN_ADCCKEN_Pos (13UL) 3324 #define RCC_PCLKEN_ADCCKEN_Msk (0x2000UL) 3325 #define RCC_PCLKEN_ADCCKEN RCC_PCLKEN_ADCCKEN_Msk 3326 #define RCC_PCLKEN_AWKCKEN_Pos (14UL) 3327 #define RCC_PCLKEN_AWKCKEN_Msk (0x4000UL) 3328 #define RCC_PCLKEN_AWKCKEN RCC_PCLKEN_AWKCKEN_Msk 3329 #define RCC_PCLKEN_RTCCKEN_Pos (15UL) 3330 #define RCC_PCLKEN_RTCCKEN_Msk (0x8000UL) 3331 #define RCC_PCLKEN_RTCCKEN RCC_PCLKEN_RTCCKEN_Msk 3332 #define RCC_PCLKEN_CLKCTRIMCKEN_Pos (16UL) 3333 #define RCC_PCLKEN_CLKCTRIMCKEN_Msk (0x10000UL) 3334 #define RCC_PCLKEN_CLKCTRIMCKEN RCC_PCLKEN_CLKCTRIMCKEN_Msk 3335 #define RCC_PCLKEN_IWDGCKEN_Pos (17UL) 3336 #define RCC_PCLKEN_IWDGCKEN_Msk (0x20000UL) 3337 #define RCC_PCLKEN_IWDGCKEN RCC_PCLKEN_IWDGCKEN_Msk 3338 #define RCC_PCLKEN_LVDVCCKEN_Pos (18UL) 3339 #define RCC_PCLKEN_LVDVCCKEN_Msk (0x40000UL) 3340 #define RCC_PCLKEN_LVDVCCKEN RCC_PCLKEN_LVDVCCKEN_Msk 3341 #define RCC_PCLKEN_BEEPCKEN_Pos (19UL) 3342 #define RCC_PCLKEN_BEEPCKEN_Msk (0x80000UL) 3343 #define RCC_PCLKEN_BEEPCKEN RCC_PCLKEN_BEEPCKEN_Msk 3344 #define RCC_PCLKEN_DBGCKEN_Pos (20UL) 3345 #define RCC_PCLKEN_DBGCKEN_Msk (0x100000UL) 3346 #define RCC_PCLKEN_DBGCKEN RCC_PCLKEN_DBGCKEN_Msk 3348 #define RCC_MCOCR_MCODIV_Pos (0UL) 3349 #define RCC_MCOCR_MCODIV_Msk (0xFFUL) 3350 #define RCC_MCOCR_MCODIV RCC_MCOCR_MCODIV_Msk 3351 #define RCC_MCOCR_MCOSEL_Pos (8UL) 3352 #define RCC_MCOCR_MCOSEL_Msk (0x700UL) 3353 #define RCC_MCOCR_MCOSEL RCC_MCOCR_MCOSEL_Msk 3354 #define RCC_MCOCR_MCOSEL_0 (0x1 << RCC_MCOCR_MCOSEL_Pos) 3355 #define RCC_MCOCR_MCOSEL_1 (0x2 << RCC_MCOCR_MCOSEL_Pos) 3356 #define RCC_MCOCR_MCOSEL_2 (0x4 << RCC_MCOCR_MCOSEL_Pos) 3357 #define RCC_MCOCR_MCOEN_Pos (12UL) 3358 #define RCC_MCOCR_MCOEN_Msk (0x1000UL) 3359 #define RCC_MCOCR_MCOEN RCC_MCOCR_MCOEN_Msk 3361 #define RCC_RSTCR_MCURST_Pos (0UL) 3362 #define RCC_RSTCR_MCURST_Msk (0x1UL) 3363 #define RCC_RSTCR_CPURST_Pos (1UL) 3364 #define RCC_RSTCR_CPURST_Msk (0x2UL) 3365 #define RCC_RSTCR_RSTKEY_Pos (2UL) 3366 #define RCC_RSTCR_RSTKEY_Msk (0xFFFFFFFCUL) 3368 #define RCC_RSTSR_MCURST_Pos (0UL) 3369 #define RCC_RSTSR_MCURST_Msk (0x1UL) 3370 #define RCC_RSTSR_MCURST RCC_RSTSR_MCURST_Msk 3371 #define RCC_RSTSR_CPURST_Pos (1UL) 3372 #define RCC_RSTSR_CPURST_Msk (0x2UL) 3373 #define RCC_RSTSR_CPURST RCC_RSTSR_CPURST_Msk 3374 #define RCC_RSTSR_WWDGRST_Pos (2UL) 3375 #define RCC_RSTSR_WWDGRST_Msk (0x4UL) 3376 #define RCC_RSTSR_WWDGRST RCC_RSTSR_WWDGRST_Msk 3377 #define RCC_RSTSR_IWDGRST_Pos (3UL) 3378 #define RCC_RSTSR_IWDGRST_Msk (0x8UL) 3379 #define RCC_RSTSR_IWDGRST RCC_RSTSR_IWDGRST_Msk 3380 #define RCC_RSTSR_LVDRST_Pos (4UL) 3381 #define RCC_RSTSR_LVDRST_Msk (0x10UL) 3382 #define RCC_RSTSR_LVDRST RCC_RSTSR_LVDRST_Msk 3383 #define RCC_RSTSR_PORRST_Pos (5UL) 3384 #define RCC_RSTSR_PORRST_Msk (0x20UL) 3385 #define RCC_RSTSR_PORRST RCC_RSTSR_PORRST_Msk 3386 #define RCC_RSTSR_LOCKUPRST_Pos (6UL) 3387 #define RCC_RSTSR_LOCKUPRST_Msk (0x40UL) 3388 #define RCC_RSTSR_LOCKUPRST RCC_RSTSR_LOCKUPRST_Msk 3389 #define RCC_RSTSR_PADRST_Pos (7UL) 3390 #define RCC_RSTSR_PADRST_Msk (0x80UL) 3391 #define RCC_RSTSR_PADRST RCC_RSTSR_PADRST_Msk 3392 #define RCC_RSTSR_SFTRST_Pos (8UL) 3393 #define RCC_RSTSR_SFTRST_Msk (0x100UL) 3394 #define RCC_RSTSR_SFTRST RCC_RSTSR_SFTRST_Msk 3396 #define RCC_SYSCLKCR_HSIEN_Pos (0UL) 3397 #define RCC_SYSCLKCR_HSIEN_Msk (0x1UL) 3398 #define RCC_SYSCLKCR_HSIEN RCC_SYSCLKCR_HSIEN_Msk 3399 #define RCC_SYSCLKCR_HSEEN_Pos (1UL) 3400 #define RCC_SYSCLKCR_HSEEN_Msk (0x2UL) 3401 #define RCC_SYSCLKCR_HSEEN RCC_SYSCLKCR_HSEEN_Msk 3402 #define RCC_SYSCLKCR_LSIEN_Pos (2UL) 3403 #define RCC_SYSCLKCR_LSIEN_Msk (0x4UL) 3404 #define RCC_SYSCLKCR_LSIEN RCC_SYSCLKCR_LSIEN_Msk 3405 #define RCC_SYSCLKCR_HSEBYP_Pos (5UL) 3406 #define RCC_SYSCLKCR_HSEBYP_Msk (0x20UL) 3407 #define RCC_SYSCLKCR_HSEBYP RCC_SYSCLKCR_HSEBYP_Msk 3408 #define RCC_SYSCLKCR_HSEPORT_Pos (6UL) 3409 #define RCC_SYSCLKCR_HSEPORT_Msk (0x40UL) 3410 #define RCC_SYSCLKCR_HSEPORT RCC_SYSCLKCR_HSEPORT_Msk 3411 #define RCC_SYSCLKCR_CLKFAILEN_Pos (8UL) 3412 #define RCC_SYSCLKCR_CLKFAILEN_Msk (0x100UL) 3413 #define RCC_SYSCLKCR_CLKFAILEN RCC_SYSCLKCR_CLKFAILEN_Msk 3414 #define RCC_SYSCLKCR_WKBYHSI_Pos (15UL) 3415 #define RCC_SYSCLKCR_WKBYHSI_Msk (0x8000UL) 3416 #define RCC_SYSCLKCR_WKBYHSI RCC_SYSCLKCR_WKBYHSI_Msk 3417 #define RCC_SYSCLKCR_KEY_Pos (16UL) 3418 #define RCC_SYSCLKCR_KEY_Msk (0xFFFF0000UL) 3419 #define RCC_SYSCLKCR_KEY RCC_SYSCLKCR_KEY_Msk 3421 #define RCC_SYSCLKSEL_CLKSW_Pos (0UL) 3422 #define RCC_SYSCLKSEL_CLKSW_Msk (0xFUL) 3423 #define RCC_SYSCLKSEL_CLKSW RCC_SYSCLKSEL_CLKSW_Msk 3424 #define RCC_SYSCLKSEL_CLKSW_0 (0x1U << RCC_SYSCLKSEL_CLKSW_Pos) 3425 #define RCC_SYSCLKSEL_CLKSW_1 (0x2U << RCC_SYSCLKSEL_CLKSW_Pos) 3426 #define RCC_SYSCLKSEL_CLKSW_2 (0x4U << RCC_SYSCLKSEL_CLKSW_Pos) 3427 #define RCC_SYSCLKSEL_CLKSW_3 (0x8U << RCC_SYSCLKSEL_CLKSW_Pos) 3428 #define RCC_SYSCLKSEL_KEY_Pos (16UL) 3429 #define RCC_SYSCLKSEL_KEY_Msk (0xFFFF0000UL) 3430 #define RCC_SYSCLKSEL_KEY RCC_SYSCLKSEL_KEY_Msk 3432 #define RCC_HSICR_HSITRIM_Pos (0UL) 3433 #define RCC_HSICR_HSITRIM_Msk (0xFFFUL) 3434 #define RCC_HSICR_HSITRIM RCC_HSICR_HSITRIM_Msk 3435 #define RCC_HSICR_HSITRIM_0_8_Mask (0x1FFUL) 3436 #define RCC_HSICR_HSITRIM_9 (0x200 << RCC_HSICR_HSITRIM_Pos) 3437 #define RCC_HSICR_HSITRIM_10 (0x400 << RCC_HSICR_HSITRIM_Pos) 3438 #define RCC_HSICR_HSITRIM_11 (0x800 << RCC_HSICR_HSITRIM_Pos) 3439 #define RCC_HSICR_HSITCTRIM_Pos (0UL) 3440 #define RCC_HSICR_HSITCTRIM_Msk (0xFFFUL) 3441 #define RCC_HSICR_HSITCTRIM_0_3_Mask (0xFUL) 3442 #define RCC_HSICR_HSITCTRIM_9_15 (0) 3443 #define RCC_HSICR_HSIRDY_Pos (12UL) 3444 #define RCC_HSICR_HSIRDY_Msk (0x1000UL) 3445 #define RCC_HSICR_HSIRDY RCC_HSICR_HSIRDY_Msk 3446 #define RCC_HSICR_KEY_Pos (16UL) 3447 #define RCC_HSICR_KEY_Msk (0xFFFF0000UL) 3448 #define RCC_HSICR_KEY RCC_HSICR_KEY_Msk 3450 #define RCC_HSECR_HSEDRV_Pos (0UL) 3451 #define RCC_HSECR_HSEDRV_Msk (0x7UL) 3452 #define RCC_HSECR_HSEDRV RCC_HSECR_HSEDRV_Msk 3453 #define RCC_HSECR_HSESTARTUP_Pos (4UL) 3454 #define RCC_HSECR_HSESTARTUP_Msk (0x30UL) 3455 #define RCC_HSECR_HSESTARTUP RCC_HSECR_HSESTARTUP_Msk 3456 #define RCC_HSECR_HSERDY_Pos (6UL) 3457 #define RCC_HSECR_HSERDY_Msk (0x40UL) 3458 #define RCC_HSECR_HSERDY RCC_HSECR_HSERDY_Msk 3460 #define RCC_LSICR_LSITRIM_Pos (0UL) 3461 #define RCC_LSICR_LSITRIM_Msk (0x1FFUL) 3462 #define RCC_LSICR_LSITRIM RCC_LSICR_LSITRIM_Msk 3463 #define RCC_LSICR_LSISTARTUP_Pos (10UL) 3464 #define RCC_LSICR_LSISTARTUP_Msk (0xC00UL) 3465 #define RCC_LSICR_LSISTARTUP RCC_LSICR_LSISTARTUP_Msk 3466 #define RCC_LSICR_LSISTARTUP_0 (0x01 << RCC_LSICR_LSISTARTUP_Pos) 3467 #define RCC_LSICR_LSISTARTUP_1 (0x02 << RCC_LSICR_LSISTARTUP_Pos) 3468 #define RCC_LSICR_LSIRDY_Pos (12UL) 3469 #define RCC_LSICR_LSIRDY_Msk (0x1000UL) 3470 #define RCC_LSICR_LSIRDY RCC_LSICR_LSIRDY_Msk 3471 #define RCC_LSICR_KEY_Pos (16UL) 3472 #define RCC_LSICR_KEY_Msk (0xFFFF0000UL) 3473 #define RCC_LSICR_KEY RCC_LSICR_KEY_Msk 3475 #define RCC_LSECR_LSEDRV_Pos (0UL) 3476 #define RCC_LSECR_LSEDRV_Msk (0xFUL) 3477 #define RCC_LSECR_LSEDRV RCC_LSECR_LSEDRV_Msk 3478 #define RCC_LSECR_LSESTARTUP_Pos (4UL) 3479 #define RCC_LSECR_LSESTARTUP_Msk (0x30UL) 3480 #define RCC_LSECR_LSESTARTUP RCC_LSECR_LSESTARTUP_Msk 3481 #define RCC_LSECR_LSERDY_Pos (6UL) 3482 #define RCC_LSECR_LSERDY_Msk (0x40UL) 3483 #define RCC_LSECR_LSERDY RCC_LSECR_LSERDY_Msk 3484 #define RCC_LSECR_LSEEN_Pos (8UL) 3485 #define RCC_LSECR_LSEEN_Msk (0x100UL) 3486 #define RCC_LSECR_LSEEN RCC_LSECR_LSEEN_Msk 3487 #define RCC_LSECR_LSEBYP_Pos (9UL) 3488 #define RCC_LSECR_LSEBYP_Msk (0x200UL) 3489 #define RCC_LSECR_LSEBYP RCC_LSECR_LSEBYP_Msk 3490 #define RCC_LSECR_LSEAON_Pos (10UL) 3491 #define RCC_LSECR_LSEAON_Msk (0x400UL) 3492 #define RCC_LSECR_LSEAON RCC_LSECR_LSEAON_Msk 3493 #define RCC_LSECR_LSEPORT_Pos (11UL) 3494 #define RCC_LSECR_LSEPORT_Msk (0x800UL) 3495 #define RCC_LSECR_LSEPORT RCC_LSECR_LSEPORT_Msk 3496 #define RCC_LSECR_KEY_Pos (16UL) 3497 #define RCC_LSECR_KEY_Msk (0xFFFF0000UL) 3498 #define RCC_LSECR_KEY RCC_LSECR_KEY_Msk 3500 #define RCC_IRQLATENCY_IRQLATENCY_Pos (0UL) 3501 #define RCC_IRQLATENCY_IRQLATENCY_Msk (0xFFUL) 3503 #define RCC_STICKCR_STCALIB_Pos (0UL) 3504 #define RCC_STICKCR_STCALIB_Msk (0xFFFFFFUL) 3505 #define RCC_STICKCR_SKEW_Pos (24UL) 3506 #define RCC_STICKCR_SKEW_Msk (0x1000000UL) 3507 #define RCC_STICKCR_NOREF_Pos (25UL) 3508 #define RCC_STICKCR_NOREF_Msk (0x2000000UL) 3510 #define RCC_SWDIOCR_SWDPORT_Pos (0UL) 3511 #define RCC_SWDIOCR_SWDPORT_Msk (0x1UL) 3512 #define RCC_SWDIOCR_KEY_Pos (16UL) 3513 #define RCC_SWDIOCR_KEY_Msk (0xFFFF0000UL) 3515 #define RCC_PERIRST_UART1RST_Pos (0UL) 3516 #define RCC_PERIRST_UART1RST_Msk (0x1UL) 3517 #define RCC_PERIRST_UART1RST RCC_PERIRST_UART1RST_Msk 3518 #define RCC_PERIRST_UART2RST_Pos (1UL) 3519 #define RCC_PERIRST_UART2RST_Msk (0x2UL) 3520 #define RCC_PERIRST_UART2RST RCC_PERIRST_UART2RST_Msk 3521 #define RCC_PERIRST_I2CRST_Pos (2UL) 3522 #define RCC_PERIRST_I2CRST_Msk (0x4UL) 3523 #define RCC_PERIRST_I2CRST RCC_PERIRST_I2CRST_Msk 3524 #define RCC_PERIRST_LPUARTRST_Pos (3UL) 3525 #define RCC_PERIRST_LPUARTRST_Msk (0x8UL) 3526 #define RCC_PERIRST_LPUARTRST RCC_PERIRST_LPUARTRST_Msk 3527 #define RCC_PERIRST_SPIRST_Pos (4UL) 3528 #define RCC_PERIRST_SPIRST_Msk (0x10UL) 3529 #define RCC_PERIRST_SPIRST RCC_PERIRST_SPIRST_Msk 3530 #define RCC_PERIRST_LPTIMRST_Pos (5UL) 3531 #define RCC_PERIRST_LPTIMRST_Msk (0x20UL) 3532 #define RCC_PERIRST_LPTIMRST RCC_PERIRST_LPTIMRST_Msk 3533 #define RCC_PERIRST_BASETIMRST_Pos (6UL) 3534 #define RCC_PERIRST_BASETIMRST_Msk (0x40UL) 3535 #define RCC_PERIRST_BASETIMRST RCC_PERIRST_BASETIMRST_Msk 3536 #define RCC_PERIRST_SYSCONRST_Pos (7UL) 3537 #define RCC_PERIRST_SYSCONRST_Msk (0x80UL) 3538 #define RCC_PERIRST_SYSCONRST RCC_PERIRST_SYSCONRST_Msk 3539 #define RCC_PERIRST_PCARST_Pos (8UL) 3540 #define RCC_PERIRST_PCARST_Msk (0x100UL) 3541 #define RCC_PERIRST_PCARST RCC_PERIRST_PCARST_Msk 3542 #define RCC_PERIRST_OWIRERST_Pos (9UL) 3543 #define RCC_PERIRST_OWIRERST_Msk (0x200UL) 3544 #define RCC_PERIRST_OWIRERST RCC_PERIRST_OWIRERST_Msk 3545 #define RCC_PERIRST_TIM1RST_Pos (10UL) 3546 #define RCC_PERIRST_TIM1RST_Msk (0x400UL) 3547 #define RCC_PERIRST_TIM1RST RCC_PERIRST_TIM1RST_Msk 3548 #define RCC_PERIRST_TIM2RST_Pos (11UL) 3549 #define RCC_PERIRST_TIM2RST_Msk (0x800UL) 3550 #define RCC_PERIRST_TIM2RST RCC_PERIRST_TIM2RST_Msk 3551 #define RCC_PERIRST_WWDGRST_Pos (12UL) 3552 #define RCC_PERIRST_WWDGRST_Msk (0x1000UL) 3553 #define RCC_PERIRST_WWDGRST RCC_PERIRST_WWDGRST_Msk 3554 #define RCC_PERIRST_ADCRST_Pos (13UL) 3555 #define RCC_PERIRST_ADCRST_Msk (0x2000UL) 3556 #define RCC_PERIRST_ADCRST RCC_PERIRST_ADCRST_Msk 3557 #define RCC_PERIRST_AWKRST_Pos (14UL) 3558 #define RCC_PERIRST_AWKRST_Msk (0x4000UL) 3559 #define RCC_PERIRST_AWKRST RCC_PERIRST_AWKRST_Msk 3560 #define RCC_PERIRST_CLKTRIMRST_Pos (16UL) 3561 #define RCC_PERIRST_CLKTRIMRST_Msk (0x10000UL) 3562 #define RCC_PERIRST_CLKTRIMRST RCC_PERIRST_CLKTRIMRST_Msk 3563 #define RCC_PERIRST_LVDVCRST_Pos (18UL) 3564 #define RCC_PERIRST_LVDVCRST_Msk (0x40000UL) 3565 #define RCC_PERIRST_LVDVCRST RCC_PERIRST_LVDVCRST_Msk 3566 #define RCC_PERIRST_BEEPRST_Pos (19UL) 3567 #define RCC_PERIRST_BEEPRST_Msk (0x80000UL) 3568 #define RCC_PERIRST_BEEPRST RCC_PERIRST_BEEPRST_Msk 3569 #define RCC_PERIRST_DBGRST_Pos (20UL) 3570 #define RCC_PERIRST_DBGRST_Msk (0x100000UL) 3571 #define RCC_PERIRST_DBGRST RCC_PERIRST_DBGRST_Msk 3572 #define RCC_PERIRST_GPIOARST_Pos (24UL) 3573 #define RCC_PERIRST_GPIOARST_Msk (0x1000000UL) 3574 #define RCC_PERIRST_GPIOARST RCC_PERIRST_GPIOARST_Msk 3575 #define RCC_PERIRST_GPIOBRST_Pos (25UL) 3576 #define RCC_PERIRST_GPIOBRST_Msk (0x2000000UL) 3577 #define RCC_PERIRST_GPIOBRST RCC_PERIRST_GPIOBRST_Msk 3578 #define RCC_PERIRST_GPIOCRST_Pos (26UL) 3579 #define RCC_PERIRST_GPIOCRST_Msk (0x4000000UL) 3580 #define RCC_PERIRST_GPIOCRST RCC_PERIRST_GPIOCRST_Msk 3581 #define RCC_PERIRST_GPIODRST_Pos (27UL) 3582 #define RCC_PERIRST_GPIODRST_Msk (0x8000000UL) 3583 #define RCC_PERIRST_GPIODRST RCC_PERIRST_GPIODRST_Msk 3584 #define RCC_PERIRST_CRCRST_Pos (28UL) 3585 #define RCC_PERIRST_CRCRST_Msk (0x10000000UL) 3586 #define RCC_PERIRST_CRCRST RCC_PERIRST_CRCRST_Msk 3588 #define RCC_RTCRST_RTCRST_Pos (0UL) 3589 #define RCC_RTCRST_RTCRST_Msk (0x1UL) 3590 #define RCC_RTCRST_RTCRST RCC_RTCRST_RTCRST_Msk 3591 #define RCC_RTCRST_KEY_Pos (16UL) 3592 #define RCC_RTCRST_KEY_Msk (0xFFFF0000UL) 3593 #define RCC_RTCRST_KEY RCC_RTCRST_KEY_Msk 3595 #define RCC_UNLOCK_UNLOCK_Pos (0UL) 3596 #define RCC_UNLOCK_UNLOCK_Msk (0x1UL) 3597 #define RCC_UNLOCK_UNLOCK RCC_UNLOCK_UNLOCK_Msk 3598 #define RCC_UNLOCK_KEY_Pos (1UL) 3599 #define RCC_UNLOCK_KEY_Msk (0xFFFFFFFEUL) 3600 #define RCC_UNLOCK_KEY RCC_UNLOCK_KEY_Msk 3604 #define M8(adr) (*((volatile uint8_t *) (adr))) 3605 #define M16(adr) (*((volatile uint16_t *) (adr))) 3606 #define M32(adr) (*((volatile uint32_t *) (adr))) 3609 #ifdef USE_STDPERIPH_DRIVER 3610 #include "mg32l003_conf.h" 3618 #define SET_BIT(REG, BIT) ((REG) |= (BIT)) 3620 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) 3622 #define READ_BIT(REG, BIT) ((REG) & (BIT)) 3624 #define CLEAR_REG(REG) ((REG) = (0x0)) 3626 #define WRITE_REG(REG, VAL) ((REG) = (VAL)) 3628 #define READ_REG(REG) ((REG)) 3630 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) 3632 #define CLEAR_WPBIT(REG, CLEARMASK, WPKEY) WRITE_REG((REG), ((READ_REG(REG)) & (~(CLEARMASK))) | WPKEY) Definition: mg32l003.h:309
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CMSIS Cortex-M0+ Core Peripheral Access Layer Header File.
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