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#define | ADC_EXTTRIG2_TIM10 (ADC_CR1_TRIGS1_0) |
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#define | ADC_EXTTRIG2_TIM11 (ADC_CR1_TRIGS1_1) |
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#define | ADC_EXTTRIG2_TIM1 (ADC_CR1_TRIGS1_1 | ADC_CR1_TRIGS1_0) |
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#define | ADC_EXTTRIG2_LPTIM (ADC_CR1_TRIGS1_2 |) |
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#define | ADC_EXTTRIG2_TIM1_TRGO (ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_0) |
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#define | ADC_EXTTRIG2_TIM2_TRGO (ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_1) |
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#define | ADC_EXTTRIG2_TIM2_INT (ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_1 | ADC_CR1_TRIGS1_0) |
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#define | ADC_EXTTRIG2_UART0_INT (ADC_CR1_TRIGS1_3) |
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#define | ADC_EXTTRIG2_UART1_INT (ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_0) |
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#define | ADC_EXTTRIG2_LPUART_INT (ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_1) |
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#define | ADC_EXTTRIG2_VC0_INT (ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_1 | ADC_CR1_TRIGS1_0) |
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#define | ADC_EXTTRIG2_NC (ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_2) |
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#define | ADC_EXTTRIG2_RTC_INT (ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_0) |
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#define | ADC_EXTTRIG2_PCA_INT (ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_1) |
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#define | ADC_EXTTRIG2_SPI_INT (ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_1 | ADC_CR1_TRIGS1_0) |
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#define | ADC_EXTTRIG2_PA1_INT (ADC_CR1_TRIGS1_4) |
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#define | ADC_EXTTRIG2_PA2_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_0) |
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#define | ADC_EXTTRIG2_PA3_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_1) |
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#define | ADC_EXTTRIG2_PB4_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_1 | ADC_CR1_TRIGS1_0) |
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#define | ADC_EXTTRIG2_PB5_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_2) |
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#define | ADC_EXTTRIG2_PC3_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_0) |
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#define | ADC_EXTTRIG2_PC4_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_0) |
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#define | ADC_EXTTRIG2_PC5_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_1) |
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#define | ADC_EXTTRIG2_PC6_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_3) |
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#define | ADC_EXTTRIG2_PC7_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_0) |
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#define | ADC_EXTTRIG2_PD1_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_1) |
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#define | ADC_EXTTRIG2_PD2_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_1 | ADC_CR1_TRIGS1_0) |
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#define | ADC_EXTTRIG2_PD3_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_2) |
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#define | ADC_EXTTRIG2_PD4_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_0) |
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#define | ADC_EXTTRIG2_PD5_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_1) |
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#define | ADC_EXTTRIG2_PD6_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_1 | ADC_CR1_TRIGS1_0) |
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#define | ADC_EXTTRIG2_PA4_INT (ADC_CR1_TRIGS1_5 | ADC_CR1_TRIGS1_0) |
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#define | ADC_EXTTRIG2_PB0_INT (ADC_CR1_TRIGS1_5 | ADC_CR1_TRIGS1_1) |
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#define | ADC_EXTTRIG2_PB1_INT (ADC_CR1_TRIGS1_5 | ADC_CR1_TRIGS1_1 | ADC_CR1_TRIGS1_0) |
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#define | ADC_EXTTRIG2_PB2_INT (ADC_CR1_TRIGS1_5 | ADC_CR1_TRIGS1_2) |
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#define | ADC_EXTTRIG2_PB3_INT (ADC_CR1_TRIGS1_5 | ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_0) |
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#define | ADC_EXTTRIG2_PB6_INT (ADC_CR1_TRIGS1_5 | ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_1) |
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#define | ADC_EXTTRIG2_PB7_INT (ADC_CR1_TRIGS1_5 | ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_1 | ADC_CR1_TRIGS1_0) |
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#define | ADC_EXTTRIG2_PC0_INT (ADC_CR1_TRIGS1_5 | ADC_CR1_TRIGS1_3) |
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#define | ADC_EXTTRIG2_PC1_INT (ADC_CR1_TRIGS1_5 | ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_0) |
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#define | ADC_EXTTRIG2_PC2_INT (ADC_CR1_TRIGS1_5 | ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_1) |
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#define | ADC_EXTTRIG2_PD0_INT (ADC_CR1_TRIGS1_5 | ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_1 | ADC_CR1_TRIGS1_0) |
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#define | ADC_EXTTRIG2_PD7_INT (ADC_CR1_TRIGS1_5 | ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_2) |
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#define | ADC_EXTTRIG2_MASK (0x3E0 | 0x20000) |
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#define | IS_ADC_EXTRIG2(EXTRIG) ((((EXTRIG) & ADC_EXTTRIG2_MASK) != 0x0000) || ((EXTRIG) == ADC_SOFTWARE_START)) |
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