MG32L003 Standard Peripherals Firmware Library
Macros
mg32l003_syscon.h File Reference

This file contains all the functions prototypes for the SYSCON firmware library. More...

#include "mg32l003.h"

Go to the source code of this file.

Macros

#define SYSCON_KEY_UNLOCK   (0x5A69)
 
#define SYSCON_DEFAULT   (0x00U)
 
#define SYSCON_UART1_RXD   (0x01U)
 
#define SYSCON_UART2_RXD   (0x02U)
 
#define SYSCON_LPUART_RXD   (0x03U)
 
#define SYSCON_LSI   (0x04U)
 
#define SYSCON_SPINCS_SEL_0   (0x01U << 0)
 
#define SYSCON_SPINCS_SEL_1   (0x01U << 1)
 
#define SYSCON_SPINCS_SEL_2   (0x01U << 2)
 
#define SYSCON_SPINCS_SEL_3   (0x01U << 3)
 
#define SYSCON_SPINCS_SEL_4   (0x01U << 10)
 
#define SYSCON_TIMETR_SEL_0   (0x01U << 16)
 
#define SYSCON_TIMETR_SEL_1   (0x01U << 17)
 
#define SYSCON_TIMETR_SEL_2   (0x01U << 18)
 
#define SYSCON_TIMETR_SEL_3   (0x01U << 19)
 
#define SYSCON_TIMETR_SEL_4   (0x01U << 23)
 
#define SYSCON_TIM_ETR_LOWLEVEL   (0x00000000U)
 
#define SYSCON_TIM_ETR_PA1   (SYSCON_TIMETR_SEL_0)
 
#define SYSCON_TIM_ETR_PA2   (SYSCON_TIMETR_SEL_1)
 
#define SYSCON_TIM_ETR_PA3   (SYSCON_TIMETR_SEL_1 | SYSCON_TIMETR_SEL_0)
 
#define SYSCON_TIM_ETR_PB4   (SYSCON_TIMETR_SEL_2)
 
#define SYSCON_TIM_ETR_PB5   (SYSCON_TIMETR_SEL_2 | SYSCON_TIMETR_SEL_0)
 
#define SYSCON_TIM_ETR_PC3   (SYSCON_TIMETR_SEL_2 | SYSCON_TIMETR_SEL_1)
 
#define SYSCON_TIM_ETR_PC4   (SYSCON_TIMETR_SEL_2 | SYSCON_TIMETR_SEL_1 | SYSCON_TIMETR_SEL_0)
 
#define SYSCON_TIM_ETR_PC5   (SYSCON_TIMETR_SEL_3)
 
#define SYSCON_TIM_ETR_PC6   (SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_0)
 
#define SYSCON_TIM_ETR_PC7   (SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_1)
 
#define SYSCON_TIM_ETR_PD1   (SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_1 | SYSCON_TIMETR_SEL_0)
 
#define SYSCON_TIM_ETR_PD2   (SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_2)
 
#define SYSCON_TIM_ETR_PD3   (SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_2 | SYSCON_TIMETR_SEL_0)
 
#define SYSCON_TIM_ETR_PD4   (SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_2 | SYSCON_TIMETR_SEL_1)
 
#define SYSCON_TIM_ETR_PD6   (SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_2 | SYSCON_TIMETR_SEL_1 | SYSCON_TIMETR_SEL_0)
 
#define SYSCON_TIM_ETR_PA4   (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_0)
 
#define SYSCON_TIM_ETR_PB0   (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_1)
 
#define SYSCON_TIM_ETR_PB1   (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_1 | SYSCON_TIMETR_SEL_0)
 
#define SYSCON_TIM_ETR_PB2   (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_2)
 
#define SYSCON_TIM_ETR_PB3   (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_2 | SYSCON_TIMETR_SEL_0)
 
#define SYSCON_TIM_ETR_PB6   (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_2 | SYSCON_TIMETR_SEL_1)
 
#define SYSCON_TIM_ETR_PB7   (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_2 | SYSCON_TIMETR_SEL_1 | SYSCON_TIMETR_SEL_0)
 
#define SYSCON_TIM_ETR_PC0   (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_3)
 
#define SYSCON_TIM_ETR_PC1   (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_0)
 
#define SYSCON_TIM_ETR_PC2   (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_1)
 
#define SYSCON_TIM_ETR_PD0   (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_1 | SYSCON_TIMETR_SEL_0)
 
#define SYSCON_TIM_ETR_PD7   (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_2)
 
#define SYSCON_SPI_NCS_HIGHLEVEL   (0x00000000U)
 
#define SYSCON_SPI_NCS_PA1   (SYSCON_SPINCS_SEL_0)
 
#define SYSCON_SPI_NCS_PA2   (SYSCON_SPINCS_SEL_1)
 
#define SYSCON_SPI_NCS_PA3   (SYSCON_SPINCS_SEL_1 | SYSCON_SPINCS_SEL_0)
 
#define SYSCON_SPI_NCS_PB4   (SYSCON_SPINCS_SEL_2)
 
#define SYSCON_SPI_NCS_PB5   (SYSCON_SPINCS_SEL_2 | SYSCON_SPINCS_SEL_0)
 
#define SYSCON_SPI_NCS_PC3   (SYSCON_SPINCS_SEL_2 | SYSCON_SPINCS_SEL_1)
 
#define SYSCON_SPI_NCS_PC4   (SYSCON_SPINCS_SEL_2 | SYSCON_SPINCS_SEL_1 | SYSCON_SPINCS_SEL_0)
 
#define SYSCON_SPI_NCS_PC5   (SYSCON_SPINCS_SEL_3)
 
#define SYSCON_SPI_NCS_PC6   (SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_0)
 
#define SYSCON_SPI_NCS_PC7   (SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_1)
 
#define SYSCON_SPI_NCS_PD1   (SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_1 | SYSCON_SPINCS_SEL_0)
 
#define SYSCON_SPI_NCS_PD2   (SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_2)
 
#define SYSCON_SPI_NCS_PD3   (SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_2 | SYSCON_SPINCS_SEL_0)
 
#define SYSCON_SPI_NCS_PD4   (SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_2 | SYSCON_SPINCS_SEL_1)
 
#define SYSCON_SPI_NCS_PD6   (SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_2 | SYSCON_SPINCS_SEL_1 | SYSCON_SPINCS_SEL_0)
 
#define SYSCON_SPI_NCS_PA4   (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_0)
 
#define SYSCON_SPI_NCS_PB0   (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_1)
 
#define SYSCON_SPI_NCS_PB1   (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_1 | SYSCON_SPINCS_SEL_0)
 
#define SYSCON_SPI_NCS_PB2   (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_2)
 
#define SYSCON_SPI_NCS_PB3   (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_2 | SYSCON_SPINCS_SEL_0)
 
#define SYSCON_SPI_NCS_PB6   (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_2 | SYSCON_SPINCS_SEL_1)
 
#define SYSCON_SPI_NCS_PB7   (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_2 | SYSCON_SPINCS_SEL_1 | SYSCON_SPINCS_SEL_0)
 
#define SYSCON_SPI_NCS_PC0   (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_3)
 
#define SYSCON_SPI_NCS_PC1   (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_0)
 
#define SYSCON_SPI_NCS_PC2   (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_1)
 
#define SYSCON_SPI_NCS_PD0   (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_1 | SYSCON_SPINCS_SEL_0)
 
#define SYSCON_SPI_NCS_PD7   (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_2)
 
#define SYSCON_CLKFAILBRKEN   SYSCON_TIM1CR_CLKFAILBRKEN
 
#define SYSCON_DSLPBRKEN   SYSCON_TIM1CR_DSLPBRKEN
 
#define SYSCON_OCOUT_LOWLEVEL   SYSCON_TIM1CR_TIM1BRKOUTCFG
 
#define SYSCON_OCOUT_BYTIM1   (0x00U)
 
#define SYSCON_REGWR_LOCK()   (SYSCON->UNLOCK = (0x2AD5334C << SYSCON_UNLOCK_KEY_Pos) & SYSCON_UNLOCK_KEY)
 
#define SYSCON_REGWR_UNLOCK()   (SYSCON->UNLOCK = SYSCON_UNLOCK_UNLOCK | (0x2AD5334C << SYSCON_UNLOCK_KEY_Pos))
 
#define SYSCON_DBGDEEPSLEEP_ENABLE()
 Macro to disable deep sleep mode in debug mode, allow to debug deep sleep mode. More...
 
#define SYSCON_DBGDEEPSLEEP_DISABLE()
 Macro to enable deep sleep mode in debug mode, debug mode will quit in deep sleep mode. More...
 
#define SYSCON_LOCKUP_ENABLE()
 Macro to enable cpu lock up function. More...
 
#define SYSCON_LOCKUP_DISABLE()
 Macro to disable cpu lock up function. More...
 
#define SYSCON_DEEPSLEEP_PADINT_AUTO()
 Macro to config PAD interrupt mode as AUTO for deep sleep:. More...
 
#define SYSCON_DEEPSLEEP_PADINT_ACTIVE()
 Macro to config PAD interrupt mode as ACTIVE for deep sleep. More...
 
#define SYSCON_LPTIM_GATE(SOURCE)
 Macro to select low power timer gate signal input source from gpio. More...
 
#define SYSCON_TIM11_GATE(SOURCE)
 Macro to select timer11 gate signal input source from gpio. More...
 
#define SYSCON_TIM10_GATE(SOURCE)
 Macro to select timer10 gate signal input source from gpio. More...
 
#define SYSCON_SPINCS(SOURCE)
 Macro to select spi slave mode NCS signal input source from gpio. More...
 
#define SYSCON_PCA_CAP4(SOURCE)
 Macro to select pca cap4 signal input source from gpio. More...
 
#define SYSCON_PCA_CAP3(SOURCE)
 Macro to select pca cap3 signal input source from gpio. More...
 
#define SYSCON_PCA_CAP2(SOURCE)
 Macro to select pca cap2 signal input source from gpio. More...
 
#define SYSCON_PCA_CAP1(SOURCE)
 Macro to select pca cap1 signal input source from gpio. More...
 
#define SYSCON_PCA_CAP0(SOURCE)
 Macro to select pca cap0 signal input source from gpio. More...
 
#define SYSCON_TIM1_BREAKIN_SEL(SOURCE)
 Macro to select timer1 break signal input source from other peripheral. More...
 
#define SYSCON_TIM1_BREAKOUT_CFG(CONFIG)
 Macro to configure timer1 ocxp/ocxnp output signal when break. More...
 
#define SYSCON_TIM1ETR_SEL(SOURCE)
 Macro to select timer1 etr signal input source from gpio. More...
 
#define SYSCON_TIM1CH4IN_SEL(SOURCE)
 Macro to select tim1 ch4 signal input source from gpio. More...
 
#define SYSCON_TIM1CH3IN_SEL(SOURCE)
 Macro to select tim1 ch3 signal input source from gpio. More...
 
#define SYSCON_TIM1CH2IN_SEL(SOURCE)
 Macro to select tim1 ch2 signal input source from gpio. More...
 
#define SYSCON_TIM1CH1IN_SEL(SOURCE)
 Macro to select tim1 ch1 signal input source from gpio. More...
 
#define SYSCON_TIM2ETR_SEL(SOURCE)
 Macro to select timer2 etr signal input source from gpio. More...
 
#define SYSCON_TIM2CH4IN_SEL(SOURCE)
 Macro to select tim2 ch4 signal input source from gpio. More...
 
#define SYSCON_TIM2CH3IN_SEL(SOURCE)
 Macro to select tim2 ch3 signal input source from gpio. More...
 
#define SYSCON_TIM2CH2IN_SEL(SOURCE)
 Macro to select tim2 ch2 signal input source from gpio. More...
 
#define SYSCON_TIM2CH1IN_SEL(SOURCE)
 Macro to select tim2 ch1 signal input source from gpio. More...
 

Detailed Description

This file contains all the functions prototypes for the SYSCON firmware library.

Author
megawin Application Team
Version
V0.0.5
Date
13-August-2024