
/*
 * Auto generated Run-Time-Environment Configuration File
 *      *** Do not modify ! ***
 *
 * Project: 'Standard_Project' 
 * Target:  'Target 1' 
 */

#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H

// ----------------------------------------------------------------------------
/* Package : The IC package selection for GPIO & EXIC. */
// ----------------------------------------------------------------------------
#define PackageLQFP80     0
#define PackageLQFP64     1
#define PackageLQFP48     2
#define PackageQFN32      3
#define PackageTSSOP20    4
#define PackageLQFP32     5
#define PackageLQFP80U    6
#define PackageLQFP64U    7
#define PackageLQFP48U    8

/*
 * Define the Device Header File: 
 * User don't need to care about this definitions.
 */
#include "MG32_ChipInit.h"
#define CMSIS_device_header 'MG32.h'

// ----------------------------------------------------------------------------
#if Initial_ADC_Module == 1
  /* Megawin::ChipInit_Wizard:ADC:1.0.0 */
  #define MG32_ConfigerWizard_ADC
#endif
// ----------------------------------------------------------------------------
#if Initial_APB_Module == 1
  /* Megawin::ChipInit_Wizard:APB:1.0.0 */
  #define MG32_ConfigerWizard_APB
#endif
// ----------------------------------------------------------------------------
#if Initial_APX_CCL_Module == 1
  #if defined(MG32_3RD) || defined(MG32_4TH)
		/* Megawin::ChipInit_Wizard:APX_CCL:1.0.0 */
		#define MG32_ConfigerWizard_APX_CCL
	#endif
#endif
// ----------------------------------------------------------------------------
#if Initial_CMP_Module == 1
  #if defined(MG32_4TH)
	#else
    /* Megawin::ChipInit_Wizard:CMP:1.0.0 */
    #define MG32_ConfigerWizard_CMP
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_CSC_Module == 1
  /* Megawin::ChipInit_Wizard:CSC:1.0.4 */
  #define MG32_ConfigerWizard_CSC
#endif
// ----------------------------------------------------------------------------
#if Initial_DAC_Module == 1
  #if defined(MG32_1ST) || defined(MG32_3RD)
    /* Megawin::ChipInit_Wizard:DAC:1.0.0 */
    #define MG32_ConfigerWizard_DAC
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_EMB_Module == 1
  #if defined(MG32_1ST) || defined(MG32_3RD)
    /* Megawin::ChipInit_Wizard:EMB:1.0.2 */
    #define MG32_ConfigerWizard_EMB
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_GPIO_Module == 1
	#if GPIO_PackageOption == PackageLQFP80
		/* Megawin::ChipInit_Wizard:GPIO:LQFP80:1.0.0 */
		#define MG32_Package_LQFP80         
		#define MG32_ConfigerWizard_GPIO
		#define MG32_GPIO_FILENAME  "MG32_GPIO_LQFP80_Init.h"
	#endif

	#if GPIO_PackageOption == PackageLQFP64
		/* Megawin::ChipInit_Wizard:GPIO:LQFP64:1.0.0 */
		#define MG32_Package_LQFP64        
		#define MG32_ConfigerWizard_GPIO
		#define MG32_GPIO_FILENAME  "MG32_GPIO_LQFP64_Init.h"   
	#endif

	#if GPIO_PackageOption == PackageLQFP48
		/* Megawin::ChipInit_Wizard:GPIO:LQFP48:1.0.0 */
		#define MG32_Package_LQFP48        
		#define MG32_ConfigerWizard_GPIO
		#define MG32_GPIO_FILENAME  "MG32_GPIO_LQFP48_Init.h"   
	#endif

	#if GPIO_PackageOption == PackageQFN32
		/* Megawin::ChipInit_Wizard:GPIO:QFN32:1.0.0 */
		#define MG32_Package_QFN32        
		#define MG32_ConfigerWizard_GPIO
		#define MG32_GPIO_FILENAME  "MG32_GPIO_QFN32_Init.h"   
	#endif

	#if GPIO_PackageOption == PackageTSSOP20
		/* Megawin::ChipInit_Wizard:GPIO:TSSOP20:1.0.0 */
		#define MG32_Package_TSSOP20        
		#define MG32_ConfigerWizard_GPIO
		#define MG32_GPIO_FILENAME  "MG32_GPIO_TSSOP20_Init.h"   
	#endif

	#if GPIO_PackageOption == PackageLQFP32
		/* Megawin::ChipInit_Wizard:GPIO:LQFP32:1.0.0 */
		#define MG32_Package_LQFP32        
		#define MG32_ConfigerWizard_GPIO
		#define MG32_GPIO_FILENAME  "MG32_GPIO_LQFP32_Init.h"   
	#endif

	#if GPIO_PackageOption == PackageLQFP80U
		/* Megawin::ChipInit_Wizard:GPIO:LQFP80U:1.0.0 */
		#define MG32_Package_LQFP80U         
		#define MG32_ConfigerWizard_GPIO
		#define MG32_GPIO_FILENAME  "MG32_GPIO_LQFP80U_Init.h"
	#endif

	#if GPIO_PackageOption == PackageLQFP64U
		/* Megawin::ChipInit_Wizard:GPIO:LQFP64U:1.0.0 */
		#define MG32_Package_LQFP64U        
		#define MG32_ConfigerWizard_GPIO
		#define MG32_GPIO_FILENAME  "MG32_GPIO_LQFP64U_Init.h"   
	#endif

	#if GPIO_PackageOption == PackageLQFP48U
		/* Megawin::ChipInit_Wizard:GPIO:LQFP48U:1.0.0 */
		#define MG32_Package_LQFP48U        
		#define MG32_ConfigerWizard_GPIO
		#define MG32_GPIO_FILENAME  "MG32_GPIO_LQFP48U_Init.h"   
	#endif
#endif 
// ----------------------------------------------------------------------------
#if Initial_EXIC_Module == 1
	#if EXIC_PackageOption == PackageLQFP80
		/* Megawin::ChipInit_Wizard:EXIC:LQFP80:1.0.0 */
		#define MG32_ConfigerWizard_EXIC          
		#define MG32_EXIC_FILENAME  "MG32_EXIC_LQFP80_Init.h"
	#endif

	#if EXIC_PackageOption == PackageLQFP64
		/* Megawin::ChipInit_Wizard:EXIC:LQFP64:1.0.0 */
		#define MG32_ConfigerWizard_EXIC          
		#define MG32_EXIC_FILENAME  "MG32_EXIC_LQFP64_Init.h"   
	#endif

	#if EXIC_PackageOption == PackageLQFP48
		/* Megawin::ChipInit_Wizard:EXIC:LQFP48:1.0.0 */
		#define MG32_ConfigerWizard_EXIC          
		#define MG32_EXIC_FILENAME  "MG32_EXIC_LQFP48_Init.h"   
	#endif

	#if EXIC_PackageOption == PackageQFN32
		/* Megawin::ChipInit_Wizard:EXIC:QFN32:1.0.0 */
		#define MG32_ConfigerWizard_EXIC          
		#define MG32_EXIC_FILENAME  "MG32_EXIC_QFN32_Init.h"   
	#endif

	#if EXIC_PackageOption == PackageTSSOP20
		/* Megawin::ChipInit_Wizard:EXIC:TSSOP20:1.0.0 */
		#define MG32_ConfigerWizard_EXIC          
		#define MG32_EXIC_FILENAME  "MG32_EXIC_TSSOP20_Init.h"   
	#endif

	#if EXIC_PackageOption == PackageLQFP32
		/* Megawin::ChipInit_Wizard:EXIC:LQFP32:1.0.0 */
		#define MG32_ConfigerWizard_EXIC          
		#define MG32_EXIC_FILENAME  "MG32_EXIC_LQFP32_Init.h"   
	#endif

	#if EXIC_PackageOption == PackageLQFP80U
		/* Megawin::ChipInit_Wizard:EXIC:LQFP80U:1.0.0 */
		#define MG32_ConfigerWizard_EXIC          
		#define MG32_EXIC_FILENAME  "MG32_EXIC_LQFP80U_Init.h"
	#endif

	#if EXIC_PackageOption == PackageLQFP64U
		/* Megawin::ChipInit_Wizard:EXIC:LQFP64U:1.0.0 */
		#define MG32_ConfigerWizard_EXIC          
		#define MG32_EXIC_FILENAME  "MG32_EXIC_LQFP64U_Init.h"   
	#endif

	#if EXIC_PackageOption == PackageLQFP48U
		/* Megawin::ChipInit_Wizard:EXIC:LQFP48U:1.0.0 */
		#define MG32_ConfigerWizard_EXIC          
		#define MG32_EXIC_FILENAME  "MG32_EXIC_LQFP48U_Init.h"   
	#endif
#endif 
// ----------------------------------------------------------------------------
#if Initial_GPL_Module == 1
  /* Megawin::ChipInit_Wizard:GPL:1.0.1 */
  #define MG32_ConfigerWizard_GPL
#endif
// ----------------------------------------------------------------------------
#if Initial_I2C_Module == 1
  /* Megawin::ChipInit_Wizard:I2C:1.0.0 */
  #define MG32_ConfigerWizard_I2C
#endif
// ----------------------------------------------------------------------------
#if Initial_IWDT_Module == 1
  /* Megawin::ChipInit_Wizard:IWDT:1.0.0 */
  #define MG32_ConfigerWizard_IWDT
#endif
// ----------------------------------------------------------------------------
#if Initial_MEM_Module == 1
  /* Megawin::ChipInit_Wizard:MEM:1.0.1 */
  #define MG32_ConfigerWizard_MEM
#endif
// ----------------------------------------------------------------------------
#if Initial_PW_Module == 1
  /* Megawin::ChipInit_Wizard:PW:1.0.1 */
  #define MG32_ConfigerWizard_PW
#endif
// ----------------------------------------------------------------------------
#if Initial_SPI_Module == 1
  /* Megawin::ChipInit_Wizard:SPI:1.0.1 */
  #define MG32_ConfigerWizard_SPI
#endif
// ----------------------------------------------------------------------------
#if Initial_RST_Module == 1
  /* Megawin::ChipInit_Wizard:RST:1.0.1 */
  #define MG32_ConfigerWizard_RST
#endif
// ----------------------------------------------------------------------------
#if Initial_RTC_Module == 1
  /* Megawin::ChipInit_Wizard:RTC:1.0.0 */
  #define MG32_ConfigerWizard_RTC
#endif
// ----------------------------------------------------------------------------
#if Initial_TM_Module == 1
  /* Megawin::ChipInit_Wizard:Timer:1.0.0 */
  #define MG32_ConfigerWizard_TM
#endif
// ----------------------------------------------------------------------------
#if Initial_URT_Module == 1
  /* Megawin::ChipInit_Wizard:URT:1.0.1 */
  #define MG32_ConfigerWizard_URT
#endif
// ----------------------------------------------------------------------------
#if defined(MG32F02A132)
  /* Megawin::Device:Startup:1.0.4 */
  #define RTE_DEVICE_STARTUP_MG32F02A132    /* Device Startup for MG32F02A132 */
#endif
// ----------------------------------------------------------------------------
#if Initial_WWDT_Module == 1
  /* Megawin::ChipInit_Wizard:WWDT:1.0.0 */
  #define MG32_ConfigerWizard_WWDT
#endif

#if defined(MG32F02A072)
  /* Megawin::Device:Startup:1.0.4 */
  #define RTE_DEVICE_STARTUP_MG32F02A072    /* Device Startup for MG32F02A072 */
#endif

#if defined(MG32F02A032)
  /* Megawin::Device:Startup:1.0.4 */
  #define RTE_DEVICE_STARTUP_MG32F02A032    /* Device Startup for MG32F02A032 */
#endif

#if defined(MG32F02A128)
  /* Megawin::Device:Startup:1.0.4 */
  #define RTE_DEVICE_STARTUP_MG32F02A128    /* Device Startup for MG32F02A128 */
#endif

#if defined(MG32F02U128)
  /* Megawin::Device:Startup:1.0.4 */
  #define RTE_DEVICE_STARTUP_MG32F02U128    /* Device Startup for MG32F02U128 */
#endif

#if defined(MG32F02A064)
  /* Megawin::Device:Startup:1.0.4 */
  #define RTE_DEVICE_STARTUP_MG32F02A064    /* Device Startup for MG32F02A064 */
#endif

#if defined(MG32F02U064)
  /* Megawin::Device:Startup:1.0.4 */
  #define RTE_DEVICE_STARTUP_MG32F02U064    /* Device Startup for MG32F02U064 */
#endif

#if defined(MG32F02V032)
  /* Megawin::Device:Startup:1.0.4 */
  #define RTE_DEVICE_STARTUP_MG32F02V032    /* Device Startup for MG32F02V032 */
#endif

// ----------------------------------------------------------------------------
#if Use_Driver_Code == 1
  /* Megawin::Driver:Driver-All:1.0.0 */
  #define IRQHandler_Driver_Level_
#endif

#if Use_Middleware_Code == 1
  /* Megawin::Middleware:Middleware-All:1.0.0 */
  #define IRQHandler_Middleware_Level_
#endif
// ----------------------------------------------------------------------------
#if Initial_SVC_IRQ > 0
  #if Initial_SVC_IRQ == 1
    /* Megawin::IRQ_Handler:11. SVC priority:Level-0 (High):1.0.0 */
    #define MG32_SVC_IRQ_
    #define MG32_SVC_IRQ_Priority0
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_SVC_IRQ == 2
    /* Megawin::IRQ_Handler:11. SVC priority:Level-1:1.0.0 */
    #define MG32_SVC_IRQ_
    #define MG32_SVC_IRQ_Priority1
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_SVC_IRQ == 3
    /* Megawin::IRQ_Handler:11. SVC priority:Level-2:1.0.0 */
    #define MG32_SVC_IRQ_
    #define MG32_SVC_IRQ_Priority2
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_SVC_IRQ == 4
    /* Megawin::IRQ_Handler:11. SVC priority:Level-3 (Low):1.0.0 */
    #define MG32_SVC_IRQ_
    #define MG32_SVC_IRQ_Priority3
    #define MG32_IRQ_Handler_
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_PendSV_IRQ > 0
  #if Initial_PendSV_IRQ == 1
    /* Megawin::IRQ_Handler:14. PendSV priority:Level-0 (High):1.0.0 */
    #define MG32_PENDSV_IRQ_
    #define MG32_PENDSV_IRQ_Priority0
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_PendSV_IRQ == 2
    /* Megawin::IRQ_Handler:14. PendSV priority:Level-1:1.0.0 */
    #define MG32_PENDSV_IRQ_
    #define MG32_PENDSV_IRQ_Priority1
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_PendSV_IRQ == 3
    /* Megawin::IRQ_Handler:14. PendSV priority:Level-2:1.0.0 */
    #define MG32_PENDSV_IRQ_
    #define MG32_PENDSV_IRQ_Priority2
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_PendSV_IRQ == 4
    /* Megawin::IRQ_Handler:14. PendSV priority:Level-3 (Low):1.0.0 */
    #define MG32_PENDSV_IRQ_
    #define MG32_PENDSV_IRQ_Priority3
    #define MG32_IRQ_Handler_
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_SysTick_IRQ > 0
  #if Initial_SysTick_IRQ == 1
    /* Megawin::IRQ_Handler:15. SysTick priority:Level-0 (High):1.0.0 */
    #define MG32_SYSTICK_IRQ_
    #define MG32_SYSTICK_IRQ_Priority0
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_SysTick_IRQ == 2
    /* Megawin::IRQ_Handler:15. SysTick priority:Level-1:1.0.0 */
    #define MG32_SYSTICK_IRQ_
    #define MG32_SYSTICK_IRQ_Priority1
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_SysTick_IRQ == 3
    /* Megawin::IRQ_Handler:15. SysTick priority:Level-2:1.0.0 */
    #define MG32_SYSTICK_IRQ_
    #define MG32_SYSTICK_IRQ_Priority2
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_SysTick_IRQ == 4
    /* Megawin::IRQ_Handler:15. SysTick priority:Level-3 (Low):1.0.0 */
    #define MG32_SYSTICK_IRQ_
    #define MG32_SYSTICK_IRQ_Priority3
    #define MG32_IRQ_Handler_
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_WWDT_IRQ > 0
  #if Initial_WWDT_IRQ == 1
    /* Megawin::IRQ_Handler:16. Enable WWDT NVIC:Level-0 (High):1.0.0 */
    #define MG32_WWDT_IRQ_
    #define MG32_WWDT_IRQ_Priority0
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_WWDT_IRQ == 2
    /* Megawin::IRQ_Handler:16. Enable WWDT NVIC:Level-1:1.0.0 */
    #define MG32_WWDT_IRQ_
    #define MG32_WWDT_IRQ_Priority1
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_WWDT_IRQ == 3
    /* Megawin::IRQ_Handler:16. Enable WWDT NVIC:Level-2:1.0.0 */
    #define MG32_WWDT_IRQ_
    #define MG32_WWDT_IRQ_Priority2
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_WWDT_IRQ == 4
    /* Megawin::IRQ_Handler:16. Enable WWDT NVIC:Level-3 (Low):1.0.0 */
    #define MG32_WWDT_IRQ_
    #define MG32_WWDT_IRQ_Priority3
    #define MG32_IRQ_Handler_
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_SYS_IRQ > 0
  #if Initial_SYS_IRQ == 1
    /* Megawin::IRQ_Handler:21. Enable SYS NVIC:Level-0 (High):1.0.0 */
    #define MG32_SYS_IRQ_
    #define MG32_SYS_IRQ_Priority0
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_SYS_IRQ == 2
    /* Megawin::IRQ_Handler:21. Enable SYS NVIC:Level-1:1.0.0 */
    #define MG32_SYS_IRQ_
    #define MG32_SYS_IRQ_Priority1
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_SYS_IRQ == 3
    /* Megawin::IRQ_Handler:21. Enable SYS NVIC:Level-2:1.0.0 */
    #define MG32_SYS_IRQ_
    #define MG32_SYS_IRQ_Priority2
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_SYS_IRQ == 4
    /* Megawin::IRQ_Handler:21. Enable SYS NVIC:Level-3 (Low):1.0.0 */
    #define MG32_SYS_IRQ_
    #define MG32_SYS_IRQ_Priority3
    #define MG32_IRQ_Handler_
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_EXINT0_IRQ > 0
  #if Initial_EXINT0_IRQ == 1
    /* Megawin::IRQ_Handler:19. Enable EXINT0 NVIC:Level-0 (High):1.0.0 */
    #define MG32_EXINT0_IRQ_
    #define MG32_EXINT0_IRQ_Priority0
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_EXINT0_IRQ == 2
    /* Megawin::IRQ_Handler:19. Enable EXINT0 NVIC:Level-1:1.0.0 */
    #define MG32_EXINT0_IRQ_
    #define MG32_EXINT0_IRQ_Priority1
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_EXINT0_IRQ == 3
    /* Megawin::IRQ_Handler:19. Enable EXINT0 NVIC:Level-2:1.0.0 */
    #define MG32_EXINT0_IRQ_
    #define MG32_EXINT0_IRQ_Priority2
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_EXINT0_IRQ == 4
    /* Megawin::IRQ_Handler:19. Enable EXINT0 NVIC:Level-3 (Low):1.0.0 */
    #define MG32_EXINT0_IRQ_
    #define MG32_EXINT0_IRQ_Priority3
    #define MG32_IRQ_Handler_
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_EXINT1_IRQ > 0
  #if Initial_EXINT1_IRQ == 1
    /* Megawin::IRQ_Handler:20. Enable EXINT1 NVIC:Level-0 (High):1.0.0 */
    #define MG32_EXINT1_IRQ_
    #define MG32_EXINT1_IRQ_Priority0
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_EXINT1_IRQ == 2
    /* Megawin::IRQ_Handler:20. Enable EXINT1 NVIC:Level-1:1.0.0 */
    #define MG32_EXINT1_IRQ_
    #define MG32_EXINT1_IRQ_Priority1
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_EXINT1_IRQ == 3
    /* Megawin::IRQ_Handler:20. Enable EXINT1 NVIC:Level-2:1.0.0 */
    #define MG32_EXINT1_IRQ_
    #define MG32_EXINT1_IRQ_Priority2
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_EXINT1_IRQ == 4
    /* Megawin::IRQ_Handler:20. Enable EXINT1 NVIC:Level-3 (Low):1.0.0 */
    #define MG32_EXINT1_IRQ_
    #define MG32_EXINT1_IRQ_Priority3
    #define MG32_IRQ_Handler_
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_EXINT2_IRQ > 0
  #if Initial_EXINT2_IRQ == 1
    /* Megawin::IRQ_Handler:21. Enable EXINT2 NVIC:Level-0 (High):1.0.0 */
    #define MG32_EXINT2_IRQ_
    #define MG32_EXINT2_IRQ_Priority0
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_EXINT2_IRQ == 2
    /* Megawin::IRQ_Handler:21. Enable EXINT2 NVIC:Level-1:1.0.0 */
    #define MG32_EXINT2_IRQ_
    #define MG32_EXINT2_IRQ_Priority1
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_EXINT2_IRQ == 3
    /* Megawin::IRQ_Handler:21. Enable EXINT2 NVIC:Level-2:1.0.0 */
    #define MG32_EXINT2_IRQ_
    #define MG32_EXINT2_IRQ_Priority2
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_EXINT2_IRQ == 4
    /* Megawin::IRQ_Handler:21. Enable EXINT2 NVIC:Level-3 (Low):1.0.0 */
    #define MG32_EXINT2_IRQ_
    #define MG32_EXINT2_IRQ_Priority3
    #define MG32_IRQ_Handler_
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_EXINT3_IRQ > 0
  #if Initial_EXINT3_IRQ == 1
    /* Megawin::IRQ_Handler:22. Enable EXINT3 NVIC:Level-0 (High):1.0.0 */
    #define MG32_EXINT3_IRQ_
    #define MG32_EXINT3_IRQ_Priority0
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_EXINT3_IRQ == 2
    /* Megawin::IRQ_Handler:22. Enable EXINT3 NVIC:Level-1:1.0.0 */
    #define MG32_EXINT3_IRQ_
    #define MG32_EXINT3_IRQ_Priority1
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_EXINT3_IRQ == 3
    /* Megawin::IRQ_Handler:22. Enable EXINT3 NVIC:Level-2:1.0.0 */
    #define MG32_EXINT3_IRQ_
    #define MG32_EXINT3_IRQ_Priority2
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_EXINT3_IRQ == 4
    /* Megawin::IRQ_Handler:22. Enable EXINT3 NVIC:Level-3 (Low):1.0.0 */
    #define MG32_EXINT3_IRQ_
    #define MG32_EXINT3_IRQ_Priority3
    #define MG32_IRQ_Handler_
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_COMP_IRQ > 0
  #if Initial_COMP_IRQ == 1
    /* Megawin::IRQ_Handler:23. Enable COMP NVIC:Level-0 (High):1.0.0 */
    #define MG32_COMP_IRQ_
    #define MG32_COMP_IRQ_Priority0
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_COMP_IRQ == 2
    /* Megawin::IRQ_Handler:23. Enable COMP NVIC:Level-1:1.0.0 */
    #define MG32_COMP_IRQ_
    #define MG32_COMP_IRQ_Priority1
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_COMP_IRQ == 3
    /* Megawin::IRQ_Handler:23. Enable COMP NVIC:Level-2:1.0.0 */
    #define MG32_COMP_IRQ_
    #define MG32_COMP_IRQ_Priority2
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_COMP_IRQ == 4
    /* Megawin::IRQ_Handler:23. Enable COMP NVIC:Level-3 (Low):1.0.0 */
    #define MG32_COMP_IRQ_
    #define MG32_COMP_IRQ_Priority3
    #define MG32_IRQ_Handler_
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_DMA_IRQ > 0
  #if Initial_DMA_IRQ == 1
    /* Megawin::IRQ_Handler:24. Enable DMA NVIC:Level-0 (High):1.0.0 */
    #define MG32_DMA_IRQ_
    #define MG32_DMA_IRQ_Priority0
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_DMA_IRQ == 2
    /* Megawin::IRQ_Handler:24. Enable DMA NVIC:Level-1:1.0.0 */
    #define MG32_DMA_IRQ_
    #define MG32_DMA_IRQ_Priority1
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_DMA_IRQ == 3
    /* Megawin::IRQ_Handler:24. Enable DMA NVIC:Level-2:1.0.0 */
    #define MG32_DMA_IRQ_
    #define MG32_DMA_IRQ_Priority2
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_DMA_IRQ == 4
    /* Megawin::IRQ_Handler:24. Enable DMA NVIC:Level-3 (Low):1.0.0 */
    #define MG32_DMA_IRQ_
    #define MG32_DMA_IRQ_Priority3
    #define MG32_IRQ_Handler_
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_ADC_IRQ > 0
  #if Initial_ADC_IRQ == 1
    /* Megawin::IRQ_Handler:26. Enable ADC NVIC:Level-0 (High):1.0.0 */
    #define MG32_ADC_IRQ_
    #define MG32_ADC_IRQ_Priority0
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_ADC_IRQ == 2
    /* Megawin::IRQ_Handler:26. Enable ADC NVIC:Level-1:1.0.0 */
    #define MG32_ADC_IRQ_
    #define MG32_ADC_IRQ_Priority1
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_ADC_IRQ == 3
    /* Megawin::IRQ_Handler:26. Enable ADC NVIC:Level-2:1.0.0 */
    #define MG32_ADC_IRQ_
    #define MG32_ADC_IRQ_Priority2
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_ADC_IRQ == 4
    /* Megawin::IRQ_Handler:26. Enable ADC NVIC:Level-3 (Low):1.0.0 */
    #define MG32_ADC_IRQ_
    #define MG32_ADC_IRQ_Priority3
    #define MG32_IRQ_Handler_
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_DAC_IRQ > 0
  #if Initial_DAC_IRQ == 1
    /* Megawin::IRQ_Handler:27. Enable DAC NVIC:Level-0 (High):1.0.0 */
    #define MG32_DAC_IRQ_
    #define MG32_DAC_IRQ_Priority0
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_DAC_IRQ == 2
    /* Megawin::IRQ_Handler:27. Enable DAC NVIC:Level-1:1.0.0 */
    #define MG32_DAC_IRQ_
    #define MG32_DAC_IRQ_Priority1
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_DAC_IRQ == 3
    /* Megawin::IRQ_Handler:27. Enable DAC NVIC:Level-2:1.0.0 */
    #define MG32_DAC_IRQ_
    #define MG32_DAC_IRQ_Priority2
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_DAC_IRQ == 4
    /* Megawin::IRQ_Handler:27. Enable DAC NVIC:Level-3 (Low):1.0.0 */
    #define MG32_DAC_IRQ_
    #define MG32_DAC_IRQ_Priority3
    #define MG32_IRQ_Handler_
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_TM0x_IRQ > 0
  #if Initial_TM0x_IRQ == 1
    /* Megawin::IRQ_Handler:28. Enable TM0x NVIC:Level-0 (High):1.0.0 */
    #define MG32_TM0x_IRQ_
    #define MG32_TM0x_IRQ_Priority0
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_TM0x_IRQ == 2
    /* Megawin::IRQ_Handler:28. Enable TM0x NVIC:Level-1:1.0.0 */
    #define MG32_TM0x_IRQ_
    #define MG32_TM0x_IRQ_Priority1
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_TM0x_IRQ == 3
    /* Megawin::IRQ_Handler:28. Enable TM0x NVIC:Level-2:1.0.0 */
    #define MG32_TM0x_IRQ_
    #define MG32_TM0x_IRQ_Priority2
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_TM0x_IRQ == 4
    /* Megawin::IRQ_Handler:28. Enable TM0x NVIC:Level-3 (Low):1.0.0 */
    #define MG32_TM0x_IRQ_
    #define MG32_TM0x_IRQ_Priority3
    #define MG32_IRQ_Handler_
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_TM10_IRQ > 0
  #if Initial_TM10_IRQ == 1
    /* Megawin::IRQ_Handler:29. Enable TM10 NVIC:Level-0 (High):1.0.0 */
    #define MG32_TM10_IRQ_
    #define MG32_TM10_IRQ_Priority0
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_TM10_IRQ == 2
    /* Megawin::IRQ_Handler:29. Enable TM10 NVIC:Level-1:1.0.0 */
    #define MG32_TM10_IRQ_
    #define MG32_TM10_IRQ_Priority1
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_TM10_IRQ == 3
    /* Megawin::IRQ_Handler:29. Enable TM10 NVIC:Level-2:1.0.0 */
    #define MG32_TM10_IRQ_
    #define MG32_TM10_IRQ_Priority2
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_TM10_IRQ == 4
    /* Megawin::IRQ_Handler:29. Enable TM10 NVIC:Level-3 (Low):1.0.0 */
    #define MG32_TM10_IRQ_
    #define MG32_TM10_IRQ_Priority3
    #define MG32_IRQ_Handler_
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_TM1x_IRQ > 0
  #if Initial_TM1x_IRQ == 1
    /* Megawin::IRQ_Handler:30. Enable TM1x NVIC:Level-0 (High):1.0.0 */
    #define MG32_TM1x_IRQ_
    #define MG32_TM1x_IRQ_Priority0
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_TM1x_IRQ == 2
    /* Megawin::IRQ_Handler:30. Enable TM1x NVIC:Level-1:1.0.0 */
    #define MG32_TM1x_IRQ_
    #define MG32_TM1x_IRQ_Priority1
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_TM1x_IRQ == 3
    /* Megawin::IRQ_Handler:30. Enable TM1x NVIC:Level-2:1.0.0 */
    #define MG32_TM1x_IRQ_
    #define MG32_TM1x_IRQ_Priority2
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_TM1x_IRQ == 4
    /* Megawin::IRQ_Handler:30. Enable TM1x NVIC:Level-3 (Low):1.0.0 */
    #define MG32_TM1x_IRQ_
    #define MG32_TM1x_IRQ_Priority3
    #define MG32_IRQ_Handler_
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_TM20_IRQ > 0
  #if Initial_TM20_IRQ == 1
    /* Megawin::IRQ_Handler:31. Enable TM20 NVIC:Level-0 (High):1.0.0 */
    #define MG32_TM20_IRQ_
    #define MG32_TM20_IRQ_Priority0
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_TM20_IRQ == 2
    /* Megawin::IRQ_Handler:31. Enable TM20 NVIC:Level-1:1.0.0 */
    #define MG32_TM20_IRQ_
    #define MG32_TM20_IRQ_Priority1
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_TM20_IRQ == 3
    /* Megawin::IRQ_Handler:31. Enable TM20 NVIC:Level-2:1.0.0 */
    #define MG32_TM20_IRQ_
    #define MG32_TM20_IRQ_Priority2
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_TM20_IRQ == 4
    /* Megawin::IRQ_Handler:31. Enable TM20 NVIC:Level-3 (Low):1.0.0 */
    #define MG32_TM20_IRQ_
    #define MG32_TM20_IRQ_Priority3
    #define MG32_IRQ_Handler_
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_TM2x_IRQ > 0
  #if Initial_TM2x_IRQ == 1
    /* Megawin::IRQ_Handler:32. Enable TM2x NVIC:Level-0 (High):1.0.0 */
    #define MG32_TM2x_IRQ_
    #define MG32_TM2x_IRQ_Priority0
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_TM2x_IRQ == 2
    /* Megawin::IRQ_Handler:32. Enable TM2x NVIC:Level-1:1.0.0 */
    #define MG32_TM2x_IRQ_
    #define MG32_TM2x_IRQ_Priority1
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_TM2x_IRQ == 3
    /* Megawin::IRQ_Handler:32. Enable TM2x NVIC:Level-2:1.0.0 */
    #define MG32_TM2x_IRQ_
    #define MG32_TM2x_IRQ_Priority2
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_TM2x_IRQ == 4
    /* Megawin::IRQ_Handler:32. Enable TM2x NVIC:Level-3 (Low):1.0.0 */
    #define MG32_TM2x_IRQ_
    #define MG32_TM2x_IRQ_Priority3
    #define MG32_IRQ_Handler_
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_TM3x_IRQ > 0
  #if Initial_TM3x_IRQ == 1
    /* Megawin::IRQ_Handler:33. Enable TM3x NVIC:Level-0 (High):1.0.0 */
    #define MG32_TM3x_IRQ_
    #define MG32_TM3x_IRQ_Priority0
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_TM3x_IRQ == 2
    /* Megawin::IRQ_Handler:33. Enable TM3x NVIC:Level-1:1.0.0 */
    #define MG32_TM3x_IRQ_
    #define MG32_TM3x_IRQ_Priority1
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_TM3x_IRQ == 3
    /* Megawin::IRQ_Handler:33. Enable TM3x NVIC:Level-2:1.0.0 */
    #define MG32_TM3x_IRQ_
    #define MG32_TM3x_IRQ_Priority2
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_TM3x_IRQ == 4
    /* Megawin::IRQ_Handler:33. Enable TM3x NVIC:Level-3 (Low):1.0.0 */
    #define MG32_TM3x_IRQ_
    #define MG32_TM3x_IRQ_Priority3
    #define MG32_IRQ_Handler_
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_URT0_IRQ > 0
  #if Initial_URT0_IRQ == 1
    /* Megawin::IRQ_Handler:36. Enable URT0 NVIC:Level-0 (High):1.0.0 */
    #define MG32_URT0_IRQ_
    #define MG32_URT0_IRQ_Priority0
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_URT0_IRQ == 2
    /* Megawin::IRQ_Handler:36. Enable URT0 NVIC:Level-1:1.0.0 */
    #define MG32_URT0_IRQ_
    #define MG32_URT0_IRQ_Priority1
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_URT0_IRQ == 3
    /* Megawin::IRQ_Handler:36. Enable URT0 NVIC:Level-2:1.0.0 */
    #define MG32_URT0_IRQ_
    #define MG32_URT0_IRQ_Priority2
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_URT0_IRQ == 4
    /* Megawin::IRQ_Handler:36. Enable URT0 NVIC:Level-3 (Low):1.0.0 */
    #define MG32_URT0_IRQ_
    #define MG32_URT0_IRQ_Priority3
    #define MG32_IRQ_Handler_
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_URT123_IRQ > 0
  #if Initial_URT123_IRQ == 1
    /* Megawin::IRQ_Handler:37. Enable URT123 NVIC:Level-0 (High):1.0.0 */
    #define MG32_URT123_IRQ_
    #define MG32_URT123_IRQ_Priority0
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_URT123_IRQ == 2
    /* Megawin::IRQ_Handler:37. Enable URT123 NVIC:Level-1:1.0.0 */
    #define MG32_URT123_IRQ_
    #define MG32_URT123_IRQ_Priority1
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_URT123_IRQ == 3
    /* Megawin::IRQ_Handler:37. Enable URT123 NVIC:Level-2:1.0.0 */
    #define MG32_URT123_IRQ_
    #define MG32_URT123_IRQ_Priority2
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_URT123_IRQ == 4
    /* Megawin::IRQ_Handler:37. Enable URT123 NVIC:Level-3 (Low):1.0.0 */
    #define MG32_URT123_IRQ_
    #define MG32_URT123_IRQ_Priority3
    #define MG32_IRQ_Handler_
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_URT4x_IRQ > 0
  #if Initial_URT4x_IRQ == 1
    /* Megawin::IRQ_Handler:38. Enable URT4x NVIC:Level-0 (High):1.0.0 */
    #define MG32_URT4x_IRQ_
    #define MG32_URT4x_IRQ_Priority0
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_URT4x_IRQ == 2
    /* Megawin::IRQ_Handler:38. Enable URT4x NVIC:Level-1:1.0.0 */
    #define MG32_URT4x_IRQ_
    #define MG32_URT4x_IRQ_Priority1
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_URT4x_IRQ == 3
    /* Megawin::IRQ_Handler:38. Enable URT4x NVIC:Level-2:1.0.0 */
    #define MG32_URT4x_IRQ_
    #define MG32_URT4x_IRQ_Priority2
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_URT4x_IRQ == 4
    /* Megawin::IRQ_Handler:38. Enable URT4x NVIC:Level-3 (Low):1.0.0 */
    #define MG32_URT4x_IRQ_
    #define MG32_URT4x_IRQ_Priority3
    #define MG32_IRQ_Handler_
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_SPI0_IRQ > 0
  #if Initial_SPI0_IRQ == 1
    /* Megawin::IRQ_Handler:40. Enable SPI0 NVIC:Level-0 (High):1.0.0 */
    #define MG32_SPI0_IRQ_
    #define MG32_SPI0_IRQ_Priority0
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_SPI0_IRQ == 2
    /* Megawin::IRQ_Handler:40. Enable SPI0 NVIC:Level-1:1.0.0 */
    #define MG32_SPI0_IRQ_
    #define MG32_SPI0_IRQ_Priority1
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_SPI0_IRQ == 3
    /* Megawin::IRQ_Handler:40. Enable SPI0 NVIC:Level-2:1.0.0 */
    #define MG32_SPI0_IRQ_
    #define MG32_SPI0_IRQ_Priority2
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_SPI0_IRQ == 4
    /* Megawin::IRQ_Handler:40. Enable SPI0 NVIC:Level-3 (Low):1.0.0 */
    #define MG32_SPI0_IRQ_
    #define MG32_SPI0_IRQ_Priority3
    #define MG32_IRQ_Handler_
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_I2C0_IRQ > 0
  #if Initial_I2C0_IRQ == 1
    /* Megawin::IRQ_Handler:44. Enable I2C0 NVIC:Level-0 (High):1.0.0 */
    #define MG32_I2C0_IRQ_
    #define MG32_I2C0_IRQ_Priority0
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_I2C0_IRQ == 2
    /* Megawin::IRQ_Handler:44. Enable I2C0 NVIC:Level-1:1.0.0 */
    #define MG32_I2C0_IRQ_
    #define MG32_I2C0_IRQ_Priority1
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_I2C0_IRQ == 3
    /* Megawin::IRQ_Handler:44. Enable I2C0 NVIC:Level-2:1.0.0 */
    #define MG32_I2C0_IRQ_
    #define MG32_I2C0_IRQ_Priority2
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_I2C0_IRQ == 4
    /* Megawin::IRQ_Handler:44. Enable I2C0 NVIC:Level-3 (Low):1.0.0 */
    #define MG32_I2C0_IRQ_
    #define MG32_I2C0_IRQ_Priority3
    #define MG32_IRQ_Handler_
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_I2Cx_IRQ > 0
  #if Initial_I2Cx_IRQ == 1
    /* Megawin::IRQ_Handler:45. Enable I2Cx NVIC:Level-0 (High):1.0.0 */
    #define MG32_I2Cx_IRQ_
    #define MG32_I2Cx_IRQ_Priority0
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_I2Cx_IRQ == 2
    /* Megawin::IRQ_Handler:45. Enable I2Cx NVIC:Level-1:1.0.0 */
    #define MG32_I2Cx_IRQ_
    #define MG32_I2Cx_IRQ_Priority1
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_I2Cx_IRQ == 3
    /* Megawin::IRQ_Handler:45. Enable I2Cx NVIC:Level-2:1.0.0 */
    #define MG32_I2Cx_IRQ_
    #define MG32_I2Cx_IRQ_Priority2
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_I2Cx_IRQ == 4
    /* Megawin::IRQ_Handler:45. Enable I2Cx NVIC:Level-3 (Low):1.0.0 */
    #define MG32_I2Cx_IRQ_
    #define MG32_I2Cx_IRQ_Priority3
    #define MG32_IRQ_Handler_
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_USB_IRQ > 0
  #if Initial_USB_IRQ == 1
    /* Megawin::IRQ_Handler:46. Enable USB NVIC:Level-0 (High):1.0.0 */
    #define MG32_USB_IRQ_
    #define MG32_USB_IRQ_Priority0
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_USB_IRQ == 2
    /* Megawin::IRQ_Handler:46. Enable USB NVIC:Level-1:1.0.0 */
    #define MG32_USB_IRQ_
    #define MG32_USB_IRQ_Priority1
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_USB_IRQ == 3
    /* Megawin::IRQ_Handler:46. Enable USB NVIC:Level-2:1.0.0 */
    #define MG32_USB_IRQ_
    #define MG32_USB_IRQ_Priority2
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_USB_IRQ == 4
    /* Megawin::IRQ_Handler:46. Enable USB NVIC:Level-3 (Low):1.0.0 */
    #define MG32_USB_IRQ_
    #define MG32_USB_IRQ_Priority3
    #define MG32_IRQ_Handler_
  #endif
#endif
// ----------------------------------------------------------------------------
#if Initial_APX_IRQ > 0
  #if Initial_APX_IRQ == 1
    /* Megawin::IRQ_Handler:47. Enable APX NVIC:Level-0 (High):1.0.0 */
    #define MG32_APX_IRQ_
    #define MG32_APX_IRQ_Priority0
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_APX_IRQ == 2
    /* Megawin::IRQ_Handler:47. Enable APX NVIC:Level-1:1.0.0 */
    #define MG32_APX_IRQ_
    #define MG32_APX_IRQ_Priority1
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_APX_IRQ == 3
    /* Megawin::IRQ_Handler:47. Enable APX NVIC:Level-2:1.0.0 */
    #define MG32_APX_IRQ_
    #define MG32_APX_IRQ_Priority2
    #define MG32_IRQ_Handler_
  #endif
  #if Initial_APX_IRQ == 4
    /* Megawin::IRQ_Handler:47. Enable APX NVIC:Level-3 (Low):1.0.0 */
    #define MG32_APX_IRQ_
    #define MG32_APX_IRQ_Priority3
    #define MG32_IRQ_Handler_
  #endif
#endif
// ----------------------------------------------------------------------------


#endif /* RTE_COMPONENTS_H */
