11 #ifndef __MG32F157_QSPI_H 12 #define __MG32F157_QSPI_H 36 uint32_t QSPI_ComConfig_FMode;
39 uint32_t QSPI_ComConfig_DDRMode;
42 uint32_t QSPI_ComConfig_DHHC;
45 uint32_t QSPI_ComConfig_SIOOMode;
48 uint32_t QSPI_ComConfig_DMode;
51 uint32_t QSPI_ComConfig_DummyCycles;
54 uint32_t QSPI_ComConfig_ABSize;
57 uint32_t QSPI_ComConfig_ABMode;
60 uint32_t QSPI_ComConfig_ADSize;
63 uint32_t QSPI_ComConfig_ADMode;
66 uint32_t QSPI_ComConfig_IMode;
69 uint32_t QSPI_ComConfig_Ins;
82 uint32_t QSPI_Prescaler;
88 uint32_t QSPI_CSHTime;
97 uint32_t QSPI_FSelect;
100 uint32_t QSPI_DFlash;
113 #define QSPI_SShift_NoShift ((uint32_t)0x00000000) 114 #define QSPI_SShift_HalfCycleShift ((uint32_t)QUADSPI_CR_SSHIFT) 116 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SShift_NoShift) || ((SSHIFT) == QSPI_SShift_HalfCycleShift)) 118 #define QUADSPI_CR_SSHIFT_0 QUADSPI_CR_SSHIFT 126 #define IS_QSPI_PRESCALER(PRESCALER) (((PRESCALER) <= 0xFF)) 134 #define QSPI_CKMode_Mode0 ((uint32_t)0x00000000) 135 #define QSPI_CKMode_Mode3 ((uint32_t)QUADSPI_DCR_CKMODE) 137 #define IS_QSPI_CKMODE(CKMode) (((CKMode) == QSPI_CKMode_Mode0) || ((CKMode) == QSPI_CKMode_Mode3)) 145 #define QSPI_CSHTime_1Cycle ((uint32_t)0x00000000) 146 #define QSPI_CSHTime_2Cycle ((uint32_t)QUADSPI_DCR_CSHT_0) 147 #define QSPI_CSHTime_3Cycle ((uint32_t)QUADSPI_DCR_CSHT_1) 148 #define QSPI_CSHTime_4Cycle ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) 149 #define QSPI_CSHTime_5Cycle ((uint32_t)QUADSPI_DCR_CSHT_2) 150 #define QSPI_CSHTime_6Cycle ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) 151 #define QSPI_CSHTime_7Cycle ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) 152 #define QSPI_CSHTime_8Cycle ((uint32_t)QUADSPI_DCR_CSHT) 154 #define IS_QSPI_CSHTIME(CSHTIME) (((CSHTIME) == QSPI_CSHTime_1Cycle) || \ 155 ((CSHTIME) == QSPI_CSHTime_2Cycle) || \ 156 ((CSHTIME) == QSPI_CSHTime_3Cycle) || \ 157 ((CSHTIME) == QSPI_CSHTime_4Cycle) || \ 158 ((CSHTIME) == QSPI_CSHTime_5Cycle) || \ 159 ((CSHTIME) == QSPI_CSHTime_6Cycle) || \ 160 ((CSHTIME) == QSPI_CSHTime_7Cycle) || \ 161 ((CSHTIME) == QSPI_CSHTime_8Cycle)) 169 #define IS_QSPI_FSIZE(FSIZE) (((FSIZE) <= 0x1F)) 177 #define QSPI_FSelect_1 ((uint32_t)0x00000000) 178 #define QSPI_FSelect_2 ((uint32_t)QUADSPI_CR_FSEL) 180 #define IS_QSPI_FSEL(FLA) (((FLA) == QSPI_FSelect_1) || ((FLA) == QSPI_FSelect_2)) 188 #define QSPI_DFlash_Disable ((uint32_t)0x00000000) 189 #define QSPI_DFlash_Enable ((uint32_t)QUADSPI_CR_DFM) 191 #define IS_QSPI_DFM(FLA) (((FLA) == QSPI_DFlash_Enable) || ((FLA) == QSPI_DFlash_Disable)) 199 #define QSPI_ComConfig_FMode_Indirect_Write ((uint32_t)0x00000000) 200 #define QSPI_ComConfig_FMode_Indirect_Read ((uint32_t)QUADSPI_CCR_FMODE_0) 201 #define QSPI_ComConfig_FMode_Auto_Polling ((uint32_t)QUADSPI_CCR_FMODE_1) 202 #define QSPI_ComConfig_FMode_Memory_Mapped ((uint32_t)QUADSPI_CCR_FMODE) 204 #define IS_QSPI_FMODE(FMODE) (((FMODE) == QSPI_ComConfig_FMode_Indirect_Write) || \ 205 ((FMODE) == QSPI_ComConfig_FMode_Indirect_Read) || \ 206 ((FMODE) == QSPI_ComConfig_FMode_Auto_Polling) || \ 207 ((FMODE) == QSPI_ComConfig_FMode_Memory_Mapped)) 215 #define QSPI_ComConfig_DDRMode_Disable ((uint32_t)0x00000000) 216 #define QSPI_ComConfig_DDRMode_Enable ((uint32_t)QUADSPI_CCR_DDRM) 218 #define IS_QSPI_DDRMODE(DDRMODE) (((DDRMODE) == QSPI_ComConfig_DDRMode_Disable) || \ 219 ((DDRMODE) == QSPI_ComConfig_DDRMode_Enable)) 227 #define QSPI_ComConfig_DHHC_Disable ((uint32_t)0x00000000) 228 #define QSPI_ComConfig_DHHC_Enable ((uint32_t)QUADSPI_CCR_DHHC) 230 #define IS_QSPI_DHHC(DHHC) (((DHHC) == QSPI_ComConfig_DHHC_Disable) || \ 231 ((DHHC) == QSPI_ComConfig_DHHC_Enable)) 239 #define QSPI_ComConfig_SIOOMode_Disable ((uint32_t)0x00000000) 240 #define QSPI_ComConfig_SIOOMode_Enable ((uint32_t)QUADSPI_CCR_SIOO) 242 #define IS_QSPI_SIOOMODE(SIOOMODE) (((SIOOMODE) == QSPI_ComConfig_SIOOMode_Disable) || \ 243 ((SIOOMODE) == QSPI_ComConfig_SIOOMode_Enable)) 251 #define QSPI_ComConfig_DMode_NoData ((uint32_t)0x00000000) 252 #define QSPI_ComConfig_DMode_1Line ((uint32_t)QUADSPI_CCR_DMODE_0) 253 #define QSPI_ComConfig_DMode_2Line ((uint32_t)QUADSPI_CCR_DMODE_1) 254 #define QSPI_ComConfig_DMode_4Line ((uint32_t)QUADSPI_CCR_DMODE) 256 #define IS_QSPI_DMODE(DMODE) (((DMODE) == QSPI_ComConfig_DMode_NoData) || \ 257 ((DMODE) == QSPI_ComConfig_DMode_1Line) || \ 258 ((DMODE) == QSPI_ComConfig_DMode_2Line) || \ 259 ((DMODE) == QSPI_ComConfig_DMode_4Line)) 267 #define QSPI_ComConfig_ABSize_8bit ((uint32_t)0x00000000) 268 #define QSPI_ComConfig_ABSize_16bit ((uint32_t)QUADSPI_CCR_ABSIZE_0) 269 #define QSPI_ComConfig_ABSize_24bit ((uint32_t)QUADSPI_CCR_ABSIZE_1) 270 #define QSPI_ComConfig_ABSize_32bit ((uint32_t)QUADSPI_CCR_ABSIZE) 272 #define IS_QSPI_ABSIZE(ABSIZE) (((ABSIZE) == QSPI_ComConfig_ABSize_8bit) || \ 273 ((ABSIZE) == QSPI_ComConfig_ABSize_16bit) || \ 274 ((ABSIZE) == QSPI_ComConfig_ABSize_24bit) || \ 275 ((ABSIZE) == QSPI_ComConfig_ABSize_32bit)) 283 #define QSPI_ComConfig_ABMode_NoAlternateByte ((uint32_t)0x00000000) 284 #define QSPI_ComConfig_ABMode_1Line ((uint32_t)QUADSPI_CCR_ABMODE_0) 285 #define QSPI_ComConfig_ABMode_2Line ((uint32_t)QUADSPI_CCR_ABMODE_1) 286 #define QSPI_ComConfig_ABMode_4Line ((uint32_t)QUADSPI_CCR_ABMODE) 288 #define IS_QSPI_ABMODE(ABMODE) (((ABMODE) == QSPI_ComConfig_ABMode_NoAlternateByte) || \ 289 ((ABMODE) == QSPI_ComConfig_ABMode_1Line) || \ 290 ((ABMODE) == QSPI_ComConfig_ABMode_2Line) || \ 291 ((ABMODE) == QSPI_ComConfig_ABMode_4Line)) 299 #define QSPI_ComConfig_ADSize_8bit ((uint32_t)0x00000000) 300 #define QSPI_ComConfig_ADSize_16bit ((uint32_t)QUADSPI_CCR_ADSIZE_0) 301 #define QSPI_ComConfig_ADSize_24bit ((uint32_t)QUADSPI_CCR_ADSIZE_1) 302 #define QSPI_ComConfig_ADSize_32bit ((uint32_t)QUADSPI_CCR_ADSIZE) 304 #define IS_QSPI_ADSIZE(ADSIZE) (((ADSIZE) == QSPI_ComConfig_ADSize_8bit) || \ 305 ((ADSIZE) == QSPI_ComConfig_ADSize_16bit) || \ 306 ((ADSIZE) == QSPI_ComConfig_ADSize_24bit) || \ 307 ((ADSIZE) == QSPI_ComConfig_ADSize_32bit)) 315 #define QSPI_ComConfig_ADMode_NoAddress ((uint32_t)0x00000000) 316 #define QSPI_ComConfig_ADMode_1Line ((uint32_t)QUADSPI_CCR_ADMODE_0) 317 #define QSPI_ComConfig_ADMode_2Line ((uint32_t)QUADSPI_CCR_ADMODE_1) 318 #define QSPI_ComConfig_ADMode_4Line ((uint32_t)QUADSPI_CCR_ADMODE) 320 #define IS_QSPI_ADMODE(ADMODE) (((ADMODE) == QSPI_ComConfig_ADMode_NoAddress) || \ 321 ((ADMODE) == QSPI_ComConfig_ADMode_1Line) || \ 322 ((ADMODE) == QSPI_ComConfig_ADMode_2Line) || \ 323 ((ADMODE) == QSPI_ComConfig_ADMode_4Line)) 331 #define QSPI_ComConfig_IMode_NoInstruction ((uint32_t)0x00000000) 332 #define QSPI_ComConfig_IMode_1Line ((uint32_t)QUADSPI_CCR_IMODE_0) 333 #define QSPI_ComConfig_IMode_2Line ((uint32_t)QUADSPI_CCR_IMODE_1) 334 #define QSPI_ComConfig_IMode_4Line ((uint32_t)QUADSPI_CCR_IMODE) 336 #define IS_QSPI_IMODE(IMODE) (((IMODE) == QSPI_ComConfig_IMode_NoInstruction) || \ 337 ((IMODE) == QSPI_ComConfig_IMode_1Line) || \ 338 ((IMODE) == QSPI_ComConfig_IMode_2Line) || \ 339 ((IMODE) == QSPI_ComConfig_IMode_4Line)) 347 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF) 355 #define QSPI_IT_TO (uint32_t)(QUADSPI_CR_TOIE | QUADSPI_SR_TOF) 356 #define QSPI_IT_SM (uint32_t)(QUADSPI_CR_SMIE | QUADSPI_SR_SMF) 357 #define QSPI_IT_FT (uint32_t)(QUADSPI_CR_FTIE | QUADSPI_SR_FTF) 358 #define QSPI_IT_TC (uint32_t)(QUADSPI_CR_TCIE | QUADSPI_SR_TCF) 359 #define QSPI_IT_TE (uint32_t)(QUADSPI_CR_TEIE | QUADSPI_SR_TEF) 361 #define IS_QSPI_IT(IT) ((((IT) & 0xFFE0FFE0) == 0) && ((IT) != 0)) 362 #define IS_QSPI_CLEAR_IT(IT) ((((IT) & 0xFFE4FFE4) == 0) && ((IT) != 0)) 370 #define QSPI_FLAG_TO QUADSPI_SR_TOF 371 #define QSPI_FLAG_SM QUADSPI_SR_SMF 372 #define QSPI_FLAG_FT QUADSPI_SR_FTF 373 #define QSPI_FLAG_TC QUADSPI_SR_TCF 374 #define QSPI_FLAG_TE QUADSPI_SR_TEF 375 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY 377 #define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_TO) || ((FLAG) == QSPI_FLAG_SM) || \ 378 ((FLAG) == QSPI_FLAG_FT) || ((FLAG) == QSPI_FLAG_TC) || \ 379 ((FLAG) == QSPI_FLAG_TE) || ((FLAG) == QSPI_FLAG_BUSY)) 380 #define IS_QSPI_CLEAR_FLAG(FLAG) (((FLAG) == QSPI_FLAG_TO) || ((FLAG) == QSPI_FLAG_SM) || \ 381 ((FLAG) == QSPI_FLAG_TC) || ((FLAG) == QSPI_FLAG_TE)) 390 #define QSPI_PMM_AND ((uint32_t)0x00000000) 391 #define QSPI_PMM_OR ((uint32_t)QUADSPI_CR_PMM) 393 #define IS_QSPI_PMM(PMM) (((PMM) == QSPI_PMM_AND) || ((PMM) == QSPI_PMM_OR)) 401 #define IS_QSPI_PIR(PIR) ((PIR) <= QUADSPI_PIR_INTERVAL) 409 #define IS_QSPI_TIMEOUT(TIMEOUT) ((TIMEOUT) <= QUADSPI_LPTR_TIMEOUT) 417 #define IS_QSPI_DCY(DCY) ((DCY) <= 0x1F) 425 #define IS_QSPI_FIFOTHRESHOLD(FIFOTHRESHOLD) ((FIFOTHRESHOLD) <= 0x0F) 438 void QSPI_DeInit(
void);
443 void QSPI_Cmd(FunctionalState NewState);
468 void QSPI_ITConfig(uint32_t QSPI_IT, FunctionalState NewState);
void QSPI_ClearITPendingBit(uint32_t QSPI_IT)
Clears the QSPI's interrupt pending bits.
Definition: mg32f157_qspi.c:729
void QSPI_ITConfig(uint32_t QSPI_IT, FunctionalState NewState)
Enables or disables the specified QSPI interrupts.
Definition: mg32f157_qspi.c:571
void QSPI_AutoPollingMode_Config(uint32_t QSPI_Match, uint32_t QSPI_Mask, uint32_t QSPI_Match_Mode)
Configure the QSPI Automatic Polling Mode.
Definition: mg32f157_qspi.c:236
void QSPI_AutoPollingModeStopCmd(FunctionalState NewState)
Enables or disables Automatic Polling Mode Stop when a match occurs.
Definition: mg32f157_qspi.c:421
void QSPI_SetDataLength(uint32_t QSPI_DataLength)
Sets number of Bytes to be transferred.
Definition: mg32f157_qspi.c:384
QSPI Communication Configuration Init structure definition.
Definition: mg32f157_qspi.h:34
void QSPI_ComConfig_Init(QSPI_ComConfig_InitTypeDef *QSPI_ComConfig_InitStruct)
Initializes the QSPI CCR according to the specified parameters in the QSPI_ComConfig_InitStruct.
Definition: mg32f157_qspi.c:157
uint32_t QSPI_GetFIFOLevel(void)
Returns the current QSPI FIFO filled level.
Definition: mg32f157_qspi.c:604
void QSPI_StructInit(QSPI_InitTypeDef *QSPI_InitStruct)
Fills each QSPI_InitStruct member with its default value.
Definition: mg32f157_qspi.c:49
FlagStatus QSPI_GetFlagStatus(uint32_t QSPI_FLAG)
Checks whether the specified QSPI flag is set or not.
Definition: mg32f157_qspi.c:637
ITStatus QSPI_GetITStatus(uint32_t QSPI_IT)
Checks whether the specified QSPI interrupt has occurred or not.
Definition: mg32f157_qspi.c:688
void QSPI_SetAddress(uint32_t QSPI_Address)
Sets the value of the Address.
Definition: mg32f157_qspi.c:319
uint32_t QSPI_GetFMode(void)
Returns the QSPI functional mode.
Definition: mg32f157_qspi.c:619
void QSPI_ClearFlag(uint32_t QSPI_FLAG)
Clears the QSPI flag.
Definition: mg32f157_qspi.c:668
void QSPI_SetAlternateByte(uint32_t QSPI_AlternateByte)
Sets the value of the Alternate Bytes.
Definition: mg32f157_qspi.c:332
void QSPI_MemoryMappedMode_SetTimeout(uint32_t QSPI_Timeout)
Sets the value of the Timeout in Memory Mapped mode.
Definition: mg32f157_qspi.c:295
void QSPI_SetFIFOThreshold(uint32_t QSPI_FIFOThreshold)
Sets the FIFO Threshold.
Definition: mg32f157_qspi.c:347
void QSPI_ComConfig_StructInit(QSPI_ComConfig_InitTypeDef *QSPI_ComConfig_InitStruct)
Fills each QSPI_ComConfig_InitStruct member with its default value.
Definition: mg32f157_qspi.c:73
void QSPI_AbortRequest(void)
Abort the on-going command sequence.
Definition: mg32f157_qspi.c:443
void QSPI_SendData16(uint16_t Data)
Transmits a 16bit Data through the QSPI peripheral.
Definition: mg32f157_qspi.c:471
void QSPI_SendData8(uint8_t Data)
Transmits a 8bit Data through the QSPI peripheral.
Definition: mg32f157_qspi.c:456
uint32_t QSPI_ReceiveData32(void)
Returns the most recent received 32bit data by the QSPI peripheral.
Definition: mg32f157_qspi.c:526
void QSPI_DMACmd(FunctionalState NewState)
Enables or disables DMA for Indirect Mode.
Definition: mg32f157_qspi.c:539
uint16_t QSPI_ReceiveData16(void)
Returns the most recent received 16bit data by the QSPI peripheral.
Definition: mg32f157_qspi.c:511
void QSPI_Cmd(FunctionalState NewState)
Enables or disables QSPI peripheral.
Definition: mg32f157_qspi.c:203
void QSPI_TimeoutCounterCmd(FunctionalState NewState)
Enables or disables The Timeout Counter.
Definition: mg32f157_qspi.c:397
void QSPI_DualFlashMode_Cmd(FunctionalState NewState)
Enables or disables QSPI Dual Flash Mode.
Definition: mg32f157_qspi.c:743
QSPI Init structure definition.
Definition: mg32f157_qspi.h:77
uint8_t QSPI_ReceiveData8(void)
Returns the most recent received 8bit data by the QSPI peripheral.
Definition: mg32f157_qspi.c:496
void QSPI_SendData32(uint32_t Data)
Transmits a 32bit Data through the QSPI peripheral.
Definition: mg32f157_qspi.c:486
void QSPI_Init(QSPI_InitTypeDef *QSPI_InitStruct)
Initializes the QSPI peripheral according to the specified parameters in the QSPI_InitStruct.
Definition: mg32f157_qspi.c:111
void QSPI_AutoPollingMode_SetInterval(uint32_t QSPI_Interval)
Sets the number of CLK cycle between two read during automatic polling phases.
Definition: mg32f157_qspi.c:269