MG32F157 Standard Peripherals Firmware Library
mg32f157_qspi.h
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1 
10 /* Define to prevent recursive inclusion -------------------------------------*/
11 #ifndef __MG32F157_QSPI_H
12 #define __MG32F157_QSPI_H
13 
14 #ifdef __cplusplus
15  extern "C" {
16 #endif
17 
18 /* Includes ------------------------------------------------------------------*/
19 #include "mg32f157.h"
20 
29 /* Exported types ------------------------------------------------------------*/
30 
34 typedef struct
35 {
36  uint32_t QSPI_ComConfig_FMode; /* Specifies the Functional Mode
37  This parameter can be a value of @ref QSPI_ComConfig_Functional_Mode*/
38 
39  uint32_t QSPI_ComConfig_DDRMode; /* Specifies the Double Data Rate Mode
40  This parameter can be a value of @ref QSPI_ComConfig_DoubleDataRateMode*/
41 
42  uint32_t QSPI_ComConfig_DHHC; /* Specifies the Delay Half Hclk Cycle
43  This parameter can be a value of @ref QSPI_ComConfig_DelayHalfHclkCycle*/
44 
45  uint32_t QSPI_ComConfig_SIOOMode; /* Specifies the Send Instruction Only Once Mode
46  This parameter can be a value of @ref QSPI_ComConfig_SendInstructionOnlyOnceMode*/
47 
48  uint32_t QSPI_ComConfig_DMode; /* Specifies the Data Mode
49  This parameter can be a value of @ref QSPI_ComConfig_DataMode*/
50 
51  uint32_t QSPI_ComConfig_DummyCycles; /* Specifies the Number of Dummy Cycles.
52  This parameter can be a number between 0x00 and 0x1F */
53 
54  uint32_t QSPI_ComConfig_ABSize; /* Specifies the Alternate Bytes Size
55  This parameter can be a value of @ref QSPI_ComConfig_AlternateBytesSize*/
56 
57  uint32_t QSPI_ComConfig_ABMode; /* Specifies the Alternate Bytes Mode
58  This parameter can be a value of @ref QSPI_ComConfig_AlternateBytesMode*/
59 
60  uint32_t QSPI_ComConfig_ADSize; /* Specifies the Address Size
61  This parameter can be a value of @ref QSPI_ComConfig_AddressSize*/
62 
63  uint32_t QSPI_ComConfig_ADMode; /* Specifies the Address Mode
64  This parameter can be a value of @ref QSPI_ComConfig_AddressMode*/
65 
66  uint32_t QSPI_ComConfig_IMode; /* Specifies the Instruction Mode
67  This parameter can be a value of @ref QSPI_ComConfig_InstructionMode*/
68 
69  uint32_t QSPI_ComConfig_Ins; /* Specifies the Instruction Mode
70  This parameter can be a value of @ref QSPI_ComConfig_Instruction*/
71 
73 
77 typedef struct
78 {
79  uint32_t QSPI_SShift; /* Specifies the Sample Shift
80  This parameter can be a value of @ref QSPI_Sample_Shift*/
81 
82  uint32_t QSPI_Prescaler; /* Specifies the prescaler value used to divide the QSPI clock.
83  This parameter can be a number between 0x00 and 0xFF */
84 
85  uint32_t QSPI_CKMode; /* Specifies the Clock Mode
86  This parameter can be a value of @ref QSPI_Clock_Mode*/
87 
88  uint32_t QSPI_CSHTime; /* Specifies the Chip Select High Time
89  This parameter can be a value of @ref QSPI_ChipSelectHighTime*/
90 
91  uint32_t QSPI_FSize; /* Specifies the Flash Size.
92  QSPI_FSize+1 is effectively the number of address bits required to address the flash memory.
93  The flash capacity can be up to 4GB (addressed using 32 bits) in indirect mode, but the
94  addressable space in memory-mapped mode is limited to 512MB
95  This parameter can be a number between 0x00 and 0x1F */
96 
97  uint32_t QSPI_FSelect; /* Specifies the Flash which will be used,
98  This parameter can be a value of @ref QSPI_Fash_Select*/
99 
100  uint32_t QSPI_DFlash; /* Specifies the Dual Flash Mode State
101  This parameter can be a value of @ref QSPI_Dual_Flash*/
103 
104 /* Exported constants --------------------------------------------------------*/
105 
113 #define QSPI_SShift_NoShift ((uint32_t)0x00000000)
114 #define QSPI_SShift_HalfCycleShift ((uint32_t)QUADSPI_CR_SSHIFT)
115 
116 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SShift_NoShift) || ((SSHIFT) == QSPI_SShift_HalfCycleShift))
117 
118 #define QUADSPI_CR_SSHIFT_0 QUADSPI_CR_SSHIFT /* Legacy Defines */
119 
126 #define IS_QSPI_PRESCALER(PRESCALER) (((PRESCALER) <= 0xFF))
127 
134 #define QSPI_CKMode_Mode0 ((uint32_t)0x00000000)
135 #define QSPI_CKMode_Mode3 ((uint32_t)QUADSPI_DCR_CKMODE)
136 
137 #define IS_QSPI_CKMODE(CKMode) (((CKMode) == QSPI_CKMode_Mode0) || ((CKMode) == QSPI_CKMode_Mode3))
138 
145 #define QSPI_CSHTime_1Cycle ((uint32_t)0x00000000)
146 #define QSPI_CSHTime_2Cycle ((uint32_t)QUADSPI_DCR_CSHT_0)
147 #define QSPI_CSHTime_3Cycle ((uint32_t)QUADSPI_DCR_CSHT_1)
148 #define QSPI_CSHTime_4Cycle ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1)
149 #define QSPI_CSHTime_5Cycle ((uint32_t)QUADSPI_DCR_CSHT_2)
150 #define QSPI_CSHTime_6Cycle ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0)
151 #define QSPI_CSHTime_7Cycle ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1)
152 #define QSPI_CSHTime_8Cycle ((uint32_t)QUADSPI_DCR_CSHT)
153 
154 #define IS_QSPI_CSHTIME(CSHTIME) (((CSHTIME) == QSPI_CSHTime_1Cycle) || \
155  ((CSHTIME) == QSPI_CSHTime_2Cycle) || \
156  ((CSHTIME) == QSPI_CSHTime_3Cycle) || \
157  ((CSHTIME) == QSPI_CSHTime_4Cycle) || \
158  ((CSHTIME) == QSPI_CSHTime_5Cycle) || \
159  ((CSHTIME) == QSPI_CSHTime_6Cycle) || \
160  ((CSHTIME) == QSPI_CSHTime_7Cycle) || \
161  ((CSHTIME) == QSPI_CSHTime_8Cycle))
162 
169 #define IS_QSPI_FSIZE(FSIZE) (((FSIZE) <= 0x1F))
170 
177 #define QSPI_FSelect_1 ((uint32_t)0x00000000)
178 #define QSPI_FSelect_2 ((uint32_t)QUADSPI_CR_FSEL)
179 
180 #define IS_QSPI_FSEL(FLA) (((FLA) == QSPI_FSelect_1) || ((FLA) == QSPI_FSelect_2))
181 
188 #define QSPI_DFlash_Disable ((uint32_t)0x00000000)
189 #define QSPI_DFlash_Enable ((uint32_t)QUADSPI_CR_DFM)
190 
191 #define IS_QSPI_DFM(FLA) (((FLA) == QSPI_DFlash_Enable) || ((FLA) == QSPI_DFlash_Disable))
192 
199 #define QSPI_ComConfig_FMode_Indirect_Write ((uint32_t)0x00000000)
200 #define QSPI_ComConfig_FMode_Indirect_Read ((uint32_t)QUADSPI_CCR_FMODE_0)
201 #define QSPI_ComConfig_FMode_Auto_Polling ((uint32_t)QUADSPI_CCR_FMODE_1)
202 #define QSPI_ComConfig_FMode_Memory_Mapped ((uint32_t)QUADSPI_CCR_FMODE)
203 
204 #define IS_QSPI_FMODE(FMODE) (((FMODE) == QSPI_ComConfig_FMode_Indirect_Write) || \
205  ((FMODE) == QSPI_ComConfig_FMode_Indirect_Read) || \
206  ((FMODE) == QSPI_ComConfig_FMode_Auto_Polling) || \
207  ((FMODE) == QSPI_ComConfig_FMode_Memory_Mapped))
208 
215 #define QSPI_ComConfig_DDRMode_Disable ((uint32_t)0x00000000)
216 #define QSPI_ComConfig_DDRMode_Enable ((uint32_t)QUADSPI_CCR_DDRM)
217 
218 #define IS_QSPI_DDRMODE(DDRMODE) (((DDRMODE) == QSPI_ComConfig_DDRMode_Disable) || \
219  ((DDRMODE) == QSPI_ComConfig_DDRMode_Enable))
220 
227 #define QSPI_ComConfig_DHHC_Disable ((uint32_t)0x00000000)
228 #define QSPI_ComConfig_DHHC_Enable ((uint32_t)QUADSPI_CCR_DHHC)
229 
230 #define IS_QSPI_DHHC(DHHC) (((DHHC) == QSPI_ComConfig_DHHC_Disable) || \
231  ((DHHC) == QSPI_ComConfig_DHHC_Enable))
232 
239 #define QSPI_ComConfig_SIOOMode_Disable ((uint32_t)0x00000000)
240 #define QSPI_ComConfig_SIOOMode_Enable ((uint32_t)QUADSPI_CCR_SIOO)
241 
242 #define IS_QSPI_SIOOMODE(SIOOMODE) (((SIOOMODE) == QSPI_ComConfig_SIOOMode_Disable) || \
243  ((SIOOMODE) == QSPI_ComConfig_SIOOMode_Enable))
244 
251 #define QSPI_ComConfig_DMode_NoData ((uint32_t)0x00000000)
252 #define QSPI_ComConfig_DMode_1Line ((uint32_t)QUADSPI_CCR_DMODE_0)
253 #define QSPI_ComConfig_DMode_2Line ((uint32_t)QUADSPI_CCR_DMODE_1)
254 #define QSPI_ComConfig_DMode_4Line ((uint32_t)QUADSPI_CCR_DMODE)
255 
256 #define IS_QSPI_DMODE(DMODE) (((DMODE) == QSPI_ComConfig_DMode_NoData) || \
257  ((DMODE) == QSPI_ComConfig_DMode_1Line) || \
258  ((DMODE) == QSPI_ComConfig_DMode_2Line) || \
259  ((DMODE) == QSPI_ComConfig_DMode_4Line))
260 
267 #define QSPI_ComConfig_ABSize_8bit ((uint32_t)0x00000000)
268 #define QSPI_ComConfig_ABSize_16bit ((uint32_t)QUADSPI_CCR_ABSIZE_0)
269 #define QSPI_ComConfig_ABSize_24bit ((uint32_t)QUADSPI_CCR_ABSIZE_1)
270 #define QSPI_ComConfig_ABSize_32bit ((uint32_t)QUADSPI_CCR_ABSIZE)
271 
272 #define IS_QSPI_ABSIZE(ABSIZE) (((ABSIZE) == QSPI_ComConfig_ABSize_8bit) || \
273  ((ABSIZE) == QSPI_ComConfig_ABSize_16bit) || \
274  ((ABSIZE) == QSPI_ComConfig_ABSize_24bit) || \
275  ((ABSIZE) == QSPI_ComConfig_ABSize_32bit))
276 
283 #define QSPI_ComConfig_ABMode_NoAlternateByte ((uint32_t)0x00000000)
284 #define QSPI_ComConfig_ABMode_1Line ((uint32_t)QUADSPI_CCR_ABMODE_0)
285 #define QSPI_ComConfig_ABMode_2Line ((uint32_t)QUADSPI_CCR_ABMODE_1)
286 #define QSPI_ComConfig_ABMode_4Line ((uint32_t)QUADSPI_CCR_ABMODE)
287 
288 #define IS_QSPI_ABMODE(ABMODE) (((ABMODE) == QSPI_ComConfig_ABMode_NoAlternateByte) || \
289  ((ABMODE) == QSPI_ComConfig_ABMode_1Line) || \
290  ((ABMODE) == QSPI_ComConfig_ABMode_2Line) || \
291  ((ABMODE) == QSPI_ComConfig_ABMode_4Line))
292 
299 #define QSPI_ComConfig_ADSize_8bit ((uint32_t)0x00000000)
300 #define QSPI_ComConfig_ADSize_16bit ((uint32_t)QUADSPI_CCR_ADSIZE_0)
301 #define QSPI_ComConfig_ADSize_24bit ((uint32_t)QUADSPI_CCR_ADSIZE_1)
302 #define QSPI_ComConfig_ADSize_32bit ((uint32_t)QUADSPI_CCR_ADSIZE)
303 
304 #define IS_QSPI_ADSIZE(ADSIZE) (((ADSIZE) == QSPI_ComConfig_ADSize_8bit) || \
305  ((ADSIZE) == QSPI_ComConfig_ADSize_16bit) || \
306  ((ADSIZE) == QSPI_ComConfig_ADSize_24bit) || \
307  ((ADSIZE) == QSPI_ComConfig_ADSize_32bit))
308 
315 #define QSPI_ComConfig_ADMode_NoAddress ((uint32_t)0x00000000)
316 #define QSPI_ComConfig_ADMode_1Line ((uint32_t)QUADSPI_CCR_ADMODE_0)
317 #define QSPI_ComConfig_ADMode_2Line ((uint32_t)QUADSPI_CCR_ADMODE_1)
318 #define QSPI_ComConfig_ADMode_4Line ((uint32_t)QUADSPI_CCR_ADMODE)
319 
320 #define IS_QSPI_ADMODE(ADMODE) (((ADMODE) == QSPI_ComConfig_ADMode_NoAddress) || \
321  ((ADMODE) == QSPI_ComConfig_ADMode_1Line) || \
322  ((ADMODE) == QSPI_ComConfig_ADMode_2Line) || \
323  ((ADMODE) == QSPI_ComConfig_ADMode_4Line))
324 
331 #define QSPI_ComConfig_IMode_NoInstruction ((uint32_t)0x00000000)
332 #define QSPI_ComConfig_IMode_1Line ((uint32_t)QUADSPI_CCR_IMODE_0)
333 #define QSPI_ComConfig_IMode_2Line ((uint32_t)QUADSPI_CCR_IMODE_1)
334 #define QSPI_ComConfig_IMode_4Line ((uint32_t)QUADSPI_CCR_IMODE)
335 
336 #define IS_QSPI_IMODE(IMODE) (((IMODE) == QSPI_ComConfig_IMode_NoInstruction) || \
337  ((IMODE) == QSPI_ComConfig_IMode_1Line) || \
338  ((IMODE) == QSPI_ComConfig_IMode_2Line) || \
339  ((IMODE) == QSPI_ComConfig_IMode_4Line))
340 
347 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF)
348 
355 #define QSPI_IT_TO (uint32_t)(QUADSPI_CR_TOIE | QUADSPI_SR_TOF)
356 #define QSPI_IT_SM (uint32_t)(QUADSPI_CR_SMIE | QUADSPI_SR_SMF)
357 #define QSPI_IT_FT (uint32_t)(QUADSPI_CR_FTIE | QUADSPI_SR_FTF)
358 #define QSPI_IT_TC (uint32_t)(QUADSPI_CR_TCIE | QUADSPI_SR_TCF)
359 #define QSPI_IT_TE (uint32_t)(QUADSPI_CR_TEIE | QUADSPI_SR_TEF)
360 
361 #define IS_QSPI_IT(IT) ((((IT) & 0xFFE0FFE0) == 0) && ((IT) != 0))
362 #define IS_QSPI_CLEAR_IT(IT) ((((IT) & 0xFFE4FFE4) == 0) && ((IT) != 0))
363 
370 #define QSPI_FLAG_TO QUADSPI_SR_TOF
371 #define QSPI_FLAG_SM QUADSPI_SR_SMF
372 #define QSPI_FLAG_FT QUADSPI_SR_FTF
373 #define QSPI_FLAG_TC QUADSPI_SR_TCF
374 #define QSPI_FLAG_TE QUADSPI_SR_TEF
375 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY
376 
377 #define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_TO) || ((FLAG) == QSPI_FLAG_SM) || \
378  ((FLAG) == QSPI_FLAG_FT) || ((FLAG) == QSPI_FLAG_TC) || \
379  ((FLAG) == QSPI_FLAG_TE) || ((FLAG) == QSPI_FLAG_BUSY))
380 #define IS_QSPI_CLEAR_FLAG(FLAG) (((FLAG) == QSPI_FLAG_TO) || ((FLAG) == QSPI_FLAG_SM) || \
381  ((FLAG) == QSPI_FLAG_TC) || ((FLAG) == QSPI_FLAG_TE))
382 
390 #define QSPI_PMM_AND ((uint32_t)0x00000000)
391 #define QSPI_PMM_OR ((uint32_t)QUADSPI_CR_PMM)
392 
393 #define IS_QSPI_PMM(PMM) (((PMM) == QSPI_PMM_AND) || ((PMM) == QSPI_PMM_OR))
394 
401 #define IS_QSPI_PIR(PIR) ((PIR) <= QUADSPI_PIR_INTERVAL)
402 
409 #define IS_QSPI_TIMEOUT(TIMEOUT) ((TIMEOUT) <= QUADSPI_LPTR_TIMEOUT)
410 
417 #define IS_QSPI_DCY(DCY) ((DCY) <= 0x1F)
418 
425 #define IS_QSPI_FIFOTHRESHOLD(FIFOTHRESHOLD) ((FIFOTHRESHOLD) <= 0x0F)
426 
434 /* Exported macro ------------------------------------------------------------*/
435 /* Exported functions ------------------------------------------------------- */
436 
437 /* Initialization and Configuration functions *********************************/
438 void QSPI_DeInit(void);
439 void QSPI_Init(QSPI_InitTypeDef* QSPI_InitStruct);
440 void QSPI_StructInit(QSPI_InitTypeDef* QSPI_InitStruct);
441 void QSPI_ComConfig_Init(QSPI_ComConfig_InitTypeDef* QSPI_ComConfig_InitStruct);
442 void QSPI_ComConfig_StructInit(QSPI_ComConfig_InitTypeDef* QSPI_ComConfig_InitStruct);
443 void QSPI_Cmd(FunctionalState NewState);
444 void QSPI_AutoPollingMode_Config(uint32_t QSPI_Match, uint32_t QSPI_Mask , uint32_t QSPI_Match_Mode);
445 void QSPI_AutoPollingMode_SetInterval(uint32_t QSPI_Interval);
446 void QSPI_MemoryMappedMode_SetTimeout(uint32_t QSPI_Timeout);
447 void QSPI_SetAddress(uint32_t QSPI_Address);
448 void QSPI_SetAlternateByte(uint32_t QSPI_AlternateByte);
449 void QSPI_SetFIFOThreshold(uint32_t QSPI_FIFOThreshold);
450 void QSPI_SetDataLength(uint32_t QSPI_DataLength);
451 void QSPI_TimeoutCounterCmd(FunctionalState NewState);
452 void QSPI_AutoPollingModeStopCmd(FunctionalState NewState);
453 void QSPI_AbortRequest(void);
454 void QSPI_DualFlashMode_Cmd(FunctionalState NewState);
455 
456 /* Data transfers functions ***************************************************/
457 void QSPI_SendData8(uint8_t Data);
458 void QSPI_SendData16(uint16_t Data);
459 void QSPI_SendData32(uint32_t Data);
460 uint8_t QSPI_ReceiveData8(void);
461 uint16_t QSPI_ReceiveData16(void);
462 uint32_t QSPI_ReceiveData32(void);
463 
464 /* DMA transfers management functions *****************************************/
465 void QSPI_DMACmd(FunctionalState NewState);
466 
467 /* Interrupts and flags management functions **********************************/
468 void QSPI_ITConfig(uint32_t QSPI_IT, FunctionalState NewState);
469 uint32_t QSPI_GetFIFOLevel(void);
470 FlagStatus QSPI_GetFlagStatus(uint32_t QSPI_FLAG);
471 void QSPI_ClearFlag(uint32_t QSPI_FLAG);
472 ITStatus QSPI_GetITStatus(uint32_t QSPI_IT);
473 void QSPI_ClearITPendingBit(uint32_t QSPI_IT);
474 uint32_t QSPI_GetFMode(void);
475 
484 #ifdef __cplusplus
485 }
486 #endif
487 
488 #endif /*__MG32F157_QSPI_H */
void QSPI_ClearITPendingBit(uint32_t QSPI_IT)
Clears the QSPI's interrupt pending bits.
Definition: mg32f157_qspi.c:729
void QSPI_ITConfig(uint32_t QSPI_IT, FunctionalState NewState)
Enables or disables the specified QSPI interrupts.
Definition: mg32f157_qspi.c:571
void QSPI_AutoPollingMode_Config(uint32_t QSPI_Match, uint32_t QSPI_Mask, uint32_t QSPI_Match_Mode)
Configure the QSPI Automatic Polling Mode.
Definition: mg32f157_qspi.c:236
void QSPI_AutoPollingModeStopCmd(FunctionalState NewState)
Enables or disables Automatic Polling Mode Stop when a match occurs.
Definition: mg32f157_qspi.c:421
void QSPI_SetDataLength(uint32_t QSPI_DataLength)
Sets number of Bytes to be transferred.
Definition: mg32f157_qspi.c:384
QSPI Communication Configuration Init structure definition.
Definition: mg32f157_qspi.h:34
void QSPI_ComConfig_Init(QSPI_ComConfig_InitTypeDef *QSPI_ComConfig_InitStruct)
Initializes the QSPI CCR according to the specified parameters in the QSPI_ComConfig_InitStruct.
Definition: mg32f157_qspi.c:157
uint32_t QSPI_GetFIFOLevel(void)
Returns the current QSPI FIFO filled level.
Definition: mg32f157_qspi.c:604
void QSPI_StructInit(QSPI_InitTypeDef *QSPI_InitStruct)
Fills each QSPI_InitStruct member with its default value.
Definition: mg32f157_qspi.c:49
FlagStatus QSPI_GetFlagStatus(uint32_t QSPI_FLAG)
Checks whether the specified QSPI flag is set or not.
Definition: mg32f157_qspi.c:637
ITStatus QSPI_GetITStatus(uint32_t QSPI_IT)
Checks whether the specified QSPI interrupt has occurred or not.
Definition: mg32f157_qspi.c:688
void QSPI_SetAddress(uint32_t QSPI_Address)
Sets the value of the Address.
Definition: mg32f157_qspi.c:319
uint32_t QSPI_GetFMode(void)
Returns the QSPI functional mode.
Definition: mg32f157_qspi.c:619
void QSPI_ClearFlag(uint32_t QSPI_FLAG)
Clears the QSPI flag.
Definition: mg32f157_qspi.c:668
void QSPI_SetAlternateByte(uint32_t QSPI_AlternateByte)
Sets the value of the Alternate Bytes.
Definition: mg32f157_qspi.c:332
void QSPI_MemoryMappedMode_SetTimeout(uint32_t QSPI_Timeout)
Sets the value of the Timeout in Memory Mapped mode.
Definition: mg32f157_qspi.c:295
void QSPI_SetFIFOThreshold(uint32_t QSPI_FIFOThreshold)
Sets the FIFO Threshold.
Definition: mg32f157_qspi.c:347
void QSPI_ComConfig_StructInit(QSPI_ComConfig_InitTypeDef *QSPI_ComConfig_InitStruct)
Fills each QSPI_ComConfig_InitStruct member with its default value.
Definition: mg32f157_qspi.c:73
void QSPI_AbortRequest(void)
Abort the on-going command sequence.
Definition: mg32f157_qspi.c:443
void QSPI_SendData16(uint16_t Data)
Transmits a 16bit Data through the QSPI peripheral.
Definition: mg32f157_qspi.c:471
void QSPI_SendData8(uint8_t Data)
Transmits a 8bit Data through the QSPI peripheral.
Definition: mg32f157_qspi.c:456
uint32_t QSPI_ReceiveData32(void)
Returns the most recent received 32bit data by the QSPI peripheral.
Definition: mg32f157_qspi.c:526
void QSPI_DMACmd(FunctionalState NewState)
Enables or disables DMA for Indirect Mode.
Definition: mg32f157_qspi.c:539
uint16_t QSPI_ReceiveData16(void)
Returns the most recent received 16bit data by the QSPI peripheral.
Definition: mg32f157_qspi.c:511
void QSPI_Cmd(FunctionalState NewState)
Enables or disables QSPI peripheral.
Definition: mg32f157_qspi.c:203
void QSPI_TimeoutCounterCmd(FunctionalState NewState)
Enables or disables The Timeout Counter.
Definition: mg32f157_qspi.c:397
void QSPI_DualFlashMode_Cmd(FunctionalState NewState)
Enables or disables QSPI Dual Flash Mode.
Definition: mg32f157_qspi.c:743
QSPI Init structure definition.
Definition: mg32f157_qspi.h:77
uint8_t QSPI_ReceiveData8(void)
Returns the most recent received 8bit data by the QSPI peripheral.
Definition: mg32f157_qspi.c:496
void QSPI_SendData32(uint32_t Data)
Transmits a 32bit Data through the QSPI peripheral.
Definition: mg32f157_qspi.c:486
void QSPI_Init(QSPI_InitTypeDef *QSPI_InitStruct)
Initializes the QSPI peripheral according to the specified parameters in the QSPI_InitStruct.
Definition: mg32f157_qspi.c:111
void QSPI_AutoPollingMode_SetInterval(uint32_t QSPI_Interval)
Sets the number of CLK cycle between two read during automatic polling phases.
Definition: mg32f157_qspi.c:269