MG32F157 Standard Peripherals Firmware Library
Data Fields
AES_TypeDef Struct Reference

Data Fields

__IO uint32_t CR
 
__IO uint32_t SR
 
__IO uint32_t DINR
 
__IO uint32_t DOUTR
 
__IO uint32_t KEYR0
 
__IO uint32_t KEYR1
 
__IO uint32_t KEYR2
 
__IO uint32_t KEYR3
 
__IO uint32_t IVR0
 
__IO uint32_t IVR1
 
__IO uint32_t IVR2
 
__IO uint32_t IVR3
 

Field Documentation

◆ CR

__IO uint32_t CR

AES control register, Address offset: 0x00

◆ DINR

__IO uint32_t DINR

AES data input register, Address offset: 0x08

◆ DOUTR

__IO uint32_t DOUTR

AES data output register, Address offset: 0x0C

◆ IVR0

__IO uint32_t IVR0

AES initialization vector register 0, Address offset: 0x20

◆ IVR1

__IO uint32_t IVR1

AES initialization vector register 1, Address offset: 0x24

◆ IVR2

__IO uint32_t IVR2

AES initialization vector register 2, Address offset: 0x28

◆ IVR3

__IO uint32_t IVR3

AES initialization vector register 3, Address offset: 0x2C

◆ KEYR0

__IO uint32_t KEYR0

AES key register 0, Address offset: 0x10

◆ KEYR1

__IO uint32_t KEYR1

AES key register 1, Address offset: 0x14

◆ KEYR2

__IO uint32_t KEYR2

AES key register 2, Address offset: 0x18

◆ KEYR3

__IO uint32_t KEYR3

AES key register 3, Address offset: 0x1C

◆ SR

__IO uint32_t SR

AES status register, Address offset: 0x04


The documentation for this struct was generated from the following file: