◆ BACK_END_POWER
__IO uint32_t BACK_END_POWER |
Back end power register, Address offset: 0x104
◆ BLKSIZ
Block sizeregister, Address offset: 0x1C
◆ BMOD
Bus mode register, Address offset: 0x80
◆ BUFADDR
Current host buffer register, Address offset: 0x98
◆ BYTCNT
Byte count register, Address offset: 0x20
◆ CARDTHRCTL
Card read threshold enable register, Address offset: 0x100
◆ CDETECT
Card detect register, Address offset: 0x50
◆ CLKDIV
Clock divider register, Address offset: 0x08
◆ CLKENA
Clock enable register, Address offset: 0x10
◆ CMD
Command register, Address offset: 0x2C
◆ CMDARG
Command argument register, Address offset: 0x28
◆ CTRL
Control register, Address offset: 0x00
◆ CTYPE
Card type register, Address offset: 0x18
◆ DBADDR
Descriptor list base address register, Address offset: 0x88
◆ DSCADDR
Current host descriptor address register, Address offset: 0x94
◆ EMMC_DDR_REG
__IO uint32_t EMMC_DDR_REG |
Emmc DDR START bit dection register, Address offset: 0x10C
◆ ENABLE_SHIFT
__IO uint32_t ENABLE_SHIFT |
Phase shift control register, Address offset: 0x110
◆ FIFO
SDIO data FIFO register, Address offset: 0x200
◆ FIFOTH
FIFO threshold register, Address offset: 0x4C
◆ IDINTEN
Internal DMAC interrupt enable register, Address offset: 0x90
◆ IDSTS
Internal DMAC status register, Address offset: 0x8C
◆ INTMASK
Interrupt mask register, Address offset: 0x24
◆ MINTSTS
Masked interrupt status register, Address offset: 0x40
◆ PLDMND
Poll memand register, Address offset: 0x84
◆ PWREN
Power enable register, Address offset: 0x04
◆ RESERVED0
◆ RESERVED1
◆ RESERVED2
__IO uint32_t RESERVED2[7] |
◆ RESERVED3
__IO uint32_t RESERVED3[25] |
◆ RESERVED4
◆ RESP0
Response 0 register, Address offset: 0x30
◆ RESP1
Response 1 register, Address offset: 0x34
◆ RESP2
Response 2 register, Address offset: 0x38
◆ RESP3
Response 3 register, Address offset: 0x3C
◆ RINTSTS
Raw interrupt status register, Address offset: 0x44
◆ STATUS
Status register, Address offset: 0x48
◆ TBBCNT
Transferred host/DMA to/from BIU-FIFO byte count register, Address offset: 0x60
◆ TCBCNT
Transferred CIU card byte count register, Address offset: 0x5C
◆ TMOUT
Time out register, Address offset: 0x14
◆ UHS_REG_EXT
__IO uint32_t UHS_REG_EXT |
Emmc 4.5 1.2V register, Address offset: 0x108
◆ WRTPRT
Write protect register, Address offset: 0x54
The documentation for this struct was generated from the following file: