◆ CR
AES control register, Address offset: 0x00
◆ DINR
AES data input register, Address offset: 0x08
◆ DOUTR
AES data output register, Address offset: 0x0C
◆ IVR0
AES initialization vector register 0, Address offset: 0x20
◆ IVR1
AES initialization vector register 1, Address offset: 0x24
◆ IVR2
AES initialization vector register 2, Address offset: 0x28
◆ IVR3
AES initialization vector register 3, Address offset: 0x2C
◆ KEYR0
AES key register 0, Address offset: 0x10
◆ KEYR1
AES key register 1, Address offset: 0x14
◆ KEYR2
AES key register 2, Address offset: 0x18
◆ KEYR3
AES key register 3, Address offset: 0x1C
◆ SR
AES status register, Address offset: 0x04
The documentation for this struct was generated from the following file: