MG32F157 Standard Peripherals Firmware Library
Data Fields
DAC_TypeDef Struct Reference

Data Fields

__IO uint32_t CR
 
__IO uint32_t SWTRIGR
 
__IO uint32_t DHR12R1
 
__IO uint32_t DHR12L1
 
__IO uint32_t DHR8R1
 
__IO uint32_t DHR12R2
 
__IO uint32_t DHR12L2
 
__IO uint32_t DHR8R2
 
__IO uint32_t DHR12RD
 
__IO uint32_t DHR12LD
 
__IO uint32_t DHR8RD
 
__IO uint32_t DOR1
 
__IO uint32_t DOR2
 

Field Documentation

◆ CR

__IO uint32_t CR

DAC control register, Address offset: 0x000

◆ DHR12L1

__IO uint32_t DHR12L1

DAC channel1 12-bit left aligned data holding register, Address offset: 0x00C

◆ DHR12L2

__IO uint32_t DHR12L2

DAC channel2 12-bit left aligned data holding register, Address offset: 0x018

◆ DHR12LD

__IO uint32_t DHR12LD

DUAL DAC 12-bit left aligned data holding register, Address offset: 0x024

◆ DHR12R1

__IO uint32_t DHR12R1

DAC channel1 12-bit right-aligned data holding register, Address offset: 0x008

◆ DHR12R2

__IO uint32_t DHR12R2

DAC channel2 12-bit right aligned data holding register, Address offset: 0x014

◆ DHR12RD

__IO uint32_t DHR12RD

DUAL DAC 12-bit right-aligned data holding register, Address offset: 0x020

◆ DHR8R1

__IO uint32_t DHR8R1

DAC channel1 8-bit right aligned data holding register, Address offset: 0x010

◆ DHR8R2

__IO uint32_t DHR8R2

DAC channel2 8-bit right-aligned data holding register, Address offset: 0x01C

◆ DHR8RD

__IO uint32_t DHR8RD

DUAL DAC 8-bit right aligned data holding register, Address offset: 0x028

◆ DOR1

__IO uint32_t DOR1

DAC channel1 data output register, Address offset: 0x02C

◆ DOR2

__IO uint32_t DOR2

DAC channel2 data output register, Address offset: 0x030

◆ SWTRIGR

__IO uint32_t SWTRIGR

DAC software trigger register, Address offset: 0x004


The documentation for this struct was generated from the following file: