MG32F157 Standard Peripherals Firmware Library
Data Fields
RCC_TypeDef Struct Reference

Data Fields

__IO uint32_t CR
 
__IO uint32_t CFGR
 
__IO uint32_t CIR
 
__IO uint32_t APB2RSTR
 
__IO uint32_t APB1RSTR
 
__IO uint32_t AHBENR
 
__IO uint32_t APB2ENR
 
__IO uint32_t APB1ENR
 
__IO uint32_t BDCR
 
__IO uint32_t CSR
 

Field Documentation

◆ AHBENR

__IO uint32_t AHBENR

AHB Peripheral Clock enable register, Address offset: 0x014

◆ APB1ENR

__IO uint32_t APB1ENR

APB1 peripheral clock enable register, Address offset: 0x01C

◆ APB1RSTR

__IO uint32_t APB1RSTR

APB1 peripheral reset register, Address offset: 0x010

◆ APB2ENR

__IO uint32_t APB2ENR

APB2 peripheral clock enable register, Address offset: 0x018

◆ APB2RSTR

__IO uint32_t APB2RSTR

APB2 peripheral reset register, Address offset: 0x00C

◆ BDCR

__IO uint32_t BDCR

Backup domain control register, Address offset: 0x020

◆ CFGR

__IO uint32_t CFGR

Clock configuration register, Address offset: 0x004

◆ CIR

__IO uint32_t CIR

Clock interrupt register, Address offset: 0x008

◆ CR

__IO uint32_t CR

Clock control register, Address offset: 0x000

◆ CSR

__IO uint32_t CSR

Control/status register, Address offset: 0x024


The documentation for this struct was generated from the following file: