◆ ACR
CAN Acceptance Code register, Address offset: 0x010
◆ ALC_TXERR_RXERR_ECC
__IO uint32_t ALC_TXERR_RXERR_ECC |
CAN ALC TXERR RXERR ECC register, Address offset: 0x018
◆ AMR
CAN Acceptance Mask register, Address offset: 0x014
◆ APERR_DPERR_FDSR_FDCFG
__IO uint32_t APERR_DPERR_FDSR_FDCFG |
CAN FD APERR DPERR FDSR FDCFG register, Address offset: 0x024
◆ BT1_BT0_RMC_IMR
__IO uint32_t BT1_BT0_RMC_IMR |
CAN BT0 BT1 RMC IMR register, Address offset: 0x004
◆ ISR_SR_CMR_MR
__IO uint32_t ISR_SR_CMR_MR |
CAN ISR SR CMR MR register, Address offset: 0x000
◆ NBT
CAN FD Arbitration Phase Bit Timming register, Address offset: 0x01C
◆ RXBUF
CAN Receive Buffer register, Address offset: 0x00C
◆ SSPP_TDCR_DBT
__IO uint32_t SSPP_TDCR_DBT |
CAN FD SSPP TDCR status register, Address offset: 0x020
◆ TEST
CAN test register, Address offset: 0x028
◆ TXBUF
CAN Transmit Buffer register, Address offset: 0x008
The documentation for this struct was generated from the following file: