◆ CR1
ADC control register 1, Address offset: 0x004
◆ CR2
ADC control register 2, Address offset: 0x008
◆ DR
ADC regular data register, Address offset: 0x04C
◆ HTR
ADC watchdog high threshold register, Address offset: 0x024
◆ JDR1
ADC injected data register 1, Address offset: 0x03C
◆ JDR2
ADC injected data register 2, Address offset: 0x040
◆ JDR3
ADC injected data register 3, Address offset: 0x044
◆ JDR4
ADC injected data register 4, Address offset: 0x048
◆ JOFR1
ADC injected channel data offset register 1, Address offset: 0x014
◆ JOFR2
ADC injected channel data offset register 2, Address offset: 0x018
◆ JOFR3
ADC injected channel data offset register 3, Address offset: 0x01C
◆ JOFR4
ADC injected channel data offset register 4, Address offset: 0x020
◆ JSQR
ADC injected sequence register, Address offset: 0x038
◆ LTR
ADC watchdog low threshold register, Address offset: 0x028
◆ SMPR1
ADC sample time register 1, Address offset: 0x00C
◆ SMPR2
ADC sample time register 2, Address offset: 0x010
◆ SQR1
ADC regular sequence register 1, Address offset: 0x02C
◆ SQR2
ADC regular sequence register 2, Address offset: 0x030
◆ SQR3
ADC regular sequence register 3, Address offset: 0x034
◆ SR
ADC status register, Address offset: 0x000
The documentation for this struct was generated from the following file: