11 #ifndef __MG32F157_TIM_H 12 #define __MG32F157_TIM_H 155 #define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 156 ((PERIPH) == TIM2) || \ 157 ((PERIPH) == TIM3) || \ 158 ((PERIPH) == TIM4) || \ 159 ((PERIPH) == TIM5) || \ 160 ((PERIPH) == TIM6) || \ 161 ((PERIPH) == TIM7) || \ 165 #define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 169 #define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 173 #define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 174 ((PERIPH) == TIM2) || \ 175 ((PERIPH) == TIM3) || \ 176 ((PERIPH) == TIM4) || \ 177 ((PERIPH) == TIM5) || \ 181 #define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 182 ((PERIPH) == TIM2) || \ 183 ((PERIPH) == TIM3) || \ 184 ((PERIPH) == TIM4) || \ 185 ((PERIPH) == TIM5) || \ 189 #define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 190 ((PERIPH) == TIM2) || \ 191 ((PERIPH) == TIM3) || \ 192 ((PERIPH) == TIM4) || \ 193 ((PERIPH) == TIM5) || \ 197 #define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 198 ((PERIPH) == TIM2) || \ 199 ((PERIPH) == TIM3) || \ 200 ((PERIPH) == TIM4) || \ 201 ((PERIPH) == TIM5) || \ 205 #define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 206 ((PERIPH) == TIM2) || \ 207 ((PERIPH) == TIM3) || \ 208 ((PERIPH) == TIM4) || \ 209 ((PERIPH) == TIM5) || \ 210 ((PERIPH) == TIM6) || \ 211 ((PERIPH) == TIM7) || \ 215 #define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 216 ((PERIPH) == TIM2) || \ 217 ((PERIPH) == TIM3) || \ 218 ((PERIPH) == TIM4) || \ 219 ((PERIPH) == TIM5) || \ 223 #define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 224 ((PERIPH) == TIM2) || \ 225 ((PERIPH) == TIM3) || \ 226 ((PERIPH) == TIM4) || \ 227 ((PERIPH) == TIM5) || \ 228 ((PERIPH) == TIM6) || \ 229 ((PERIPH) == TIM7) || \ 236 #define TIM_OCMode_Timing ((uint16_t)0x0000) 237 #define TIM_OCMode_Active ((uint16_t)0x0010) 238 #define TIM_OCMode_Inactive ((uint16_t)0x0020) 239 #define TIM_OCMode_Toggle ((uint16_t)0x0030) 240 #define TIM_OCMode_PWM1 ((uint16_t)0x0060) 241 #define TIM_OCMode_PWM2 ((uint16_t)0x0070) 242 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ 243 ((MODE) == TIM_OCMode_Active) || \ 244 ((MODE) == TIM_OCMode_Inactive) || \ 245 ((MODE) == TIM_OCMode_Toggle)|| \ 246 ((MODE) == TIM_OCMode_PWM1) || \ 247 ((MODE) == TIM_OCMode_PWM2)) 248 #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ 249 ((MODE) == TIM_OCMode_Active) || \ 250 ((MODE) == TIM_OCMode_Inactive) || \ 251 ((MODE) == TIM_OCMode_Toggle)|| \ 252 ((MODE) == TIM_OCMode_PWM1) || \ 253 ((MODE) == TIM_OCMode_PWM2) || \ 254 ((MODE) == TIM_ForcedAction_Active) || \ 255 ((MODE) == TIM_ForcedAction_InActive)) 264 #define TIM_OPMode_Single ((uint16_t)0x0008) 265 #define TIM_OPMode_Repetitive ((uint16_t)0x0000) 266 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ 267 ((MODE) == TIM_OPMode_Repetitive)) 276 #define TIM_Channel_1 ((uint16_t)0x0000) 277 #define TIM_Channel_2 ((uint16_t)0x0004) 278 #define TIM_Channel_3 ((uint16_t)0x0008) 279 #define TIM_Channel_4 ((uint16_t)0x000C) 280 #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ 281 ((CHANNEL) == TIM_Channel_2) || \ 282 ((CHANNEL) == TIM_Channel_3) || \ 283 ((CHANNEL) == TIM_Channel_4)) 284 #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ 285 ((CHANNEL) == TIM_Channel_2)) 286 #define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ 287 ((CHANNEL) == TIM_Channel_2) || \ 288 ((CHANNEL) == TIM_Channel_3)) 297 #define TIM_CKD_DIV1 ((uint16_t)0x0000) 298 #define TIM_CKD_DIV2 ((uint16_t)0x0100) 299 #define TIM_CKD_DIV4 ((uint16_t)0x0200) 300 #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ 301 ((DIV) == TIM_CKD_DIV2) || \ 302 ((DIV) == TIM_CKD_DIV4)) 311 #define TIM_CounterMode_Up ((uint16_t)0x0000) 312 #define TIM_CounterMode_Down ((uint16_t)0x0010) 313 #define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) 314 #define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) 315 #define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) 316 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ 317 ((MODE) == TIM_CounterMode_Down) || \ 318 ((MODE) == TIM_CounterMode_CenterAligned1) || \ 319 ((MODE) == TIM_CounterMode_CenterAligned2) || \ 320 ((MODE) == TIM_CounterMode_CenterAligned3)) 329 #define TIM_OCPolarity_High ((uint16_t)0x0000) 330 #define TIM_OCPolarity_Low ((uint16_t)0x0002) 331 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ 332 ((POLARITY) == TIM_OCPolarity_Low)) 341 #define TIM_OCNPolarity_High ((uint16_t)0x0000) 342 #define TIM_OCNPolarity_Low ((uint16_t)0x0008) 343 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ 344 ((POLARITY) == TIM_OCNPolarity_Low)) 353 #define TIM_OutputState_Disable ((uint16_t)0x0000) 354 #define TIM_OutputState_Enable ((uint16_t)0x0001) 355 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ 356 ((STATE) == TIM_OutputState_Enable)) 365 #define TIM_OutputNState_Disable ((uint16_t)0x0000) 366 #define TIM_OutputNState_Enable ((uint16_t)0x0004) 367 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ 368 ((STATE) == TIM_OutputNState_Enable)) 377 #define TIM_CCx_Enable ((uint16_t)0x0001) 378 #define TIM_CCx_Disable ((uint16_t)0x0000) 379 #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ 380 ((CCX) == TIM_CCx_Disable)) 389 #define TIM_CCxN_Enable ((uint16_t)0x0004) 390 #define TIM_CCxN_Disable ((uint16_t)0x0000) 391 #define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ 392 ((CCXN) == TIM_CCxN_Disable)) 401 #define TIM_Break_Enable ((uint16_t)0x1000) 402 #define TIM_Break_Disable ((uint16_t)0x0000) 403 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ 404 ((STATE) == TIM_Break_Disable)) 413 #define TIM_BreakPolarity_Low ((uint16_t)0x0000) 414 #define TIM_BreakPolarity_High ((uint16_t)0x2000) 415 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ 416 ((POLARITY) == TIM_BreakPolarity_High)) 425 #define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) 426 #define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) 427 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ 428 ((STATE) == TIM_AutomaticOutput_Disable)) 437 #define TIM_LOCKLevel_OFF ((uint16_t)0x0000) 438 #define TIM_LOCKLevel_1 ((uint16_t)0x0100) 439 #define TIM_LOCKLevel_2 ((uint16_t)0x0200) 440 #define TIM_LOCKLevel_3 ((uint16_t)0x0300) 441 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ 442 ((LEVEL) == TIM_LOCKLevel_1) || \ 443 ((LEVEL) == TIM_LOCKLevel_2) || \ 444 ((LEVEL) == TIM_LOCKLevel_3)) 453 #define TIM_OSSIState_Enable ((uint16_t)0x0400) 454 #define TIM_OSSIState_Disable ((uint16_t)0x0000) 455 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ 456 ((STATE) == TIM_OSSIState_Disable)) 465 #define TIM_OSSRState_Enable ((uint16_t)0x0800) 466 #define TIM_OSSRState_Disable ((uint16_t)0x0000) 467 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ 468 ((STATE) == TIM_OSSRState_Disable)) 477 #define TIM_OCIdleState_Set ((uint16_t)0x0100) 478 #define TIM_OCIdleState_Reset ((uint16_t)0x0000) 479 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ 480 ((STATE) == TIM_OCIdleState_Reset)) 489 #define TIM_OCNIdleState_Set ((uint16_t)0x0200) 490 #define TIM_OCNIdleState_Reset ((uint16_t)0x0000) 491 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ 492 ((STATE) == TIM_OCNIdleState_Reset)) 501 #define TIM_ICPolarity_Rising ((uint16_t)0x0000) 502 #define TIM_ICPolarity_Falling ((uint16_t)0x0002) 503 #define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) 504 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ 505 ((POLARITY) == TIM_ICPolarity_Falling)) 506 #define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ 507 ((POLARITY) == TIM_ICPolarity_Falling)|| \ 508 ((POLARITY) == TIM_ICPolarity_BothEdge)) 516 #define TIM_ICSelection_DirectTI ((uint16_t)0x0001) 518 #define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) 520 #define TIM_ICSelection_TRC ((uint16_t)0x0003) 521 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ 522 ((SELECTION) == TIM_ICSelection_IndirectTI) || \ 523 ((SELECTION) == TIM_ICSelection_TRC)) 532 #define TIM_ICPSC_DIV1 ((uint16_t)0x0000) 533 #define TIM_ICPSC_DIV2 ((uint16_t)0x0004) 534 #define TIM_ICPSC_DIV4 ((uint16_t)0x0008) 535 #define TIM_ICPSC_DIV8 ((uint16_t)0x000C) 536 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ 537 ((PRESCALER) == TIM_ICPSC_DIV2) || \ 538 ((PRESCALER) == TIM_ICPSC_DIV4) || \ 539 ((PRESCALER) == TIM_ICPSC_DIV8)) 548 #define TIM_IT_Update ((uint16_t)0x0001) 549 #define TIM_IT_CC1 ((uint16_t)0x0002) 550 #define TIM_IT_CC2 ((uint16_t)0x0004) 551 #define TIM_IT_CC3 ((uint16_t)0x0008) 552 #define TIM_IT_CC4 ((uint16_t)0x0010) 553 #define TIM_IT_COM ((uint16_t)0x0020) 554 #define TIM_IT_Trigger ((uint16_t)0x0040) 555 #define TIM_IT_Break ((uint16_t)0x0080) 556 #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) 558 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ 559 ((IT) == TIM_IT_CC1) || \ 560 ((IT) == TIM_IT_CC2) || \ 561 ((IT) == TIM_IT_CC3) || \ 562 ((IT) == TIM_IT_CC4) || \ 563 ((IT) == TIM_IT_COM) || \ 564 ((IT) == TIM_IT_Trigger) || \ 565 ((IT) == TIM_IT_Break)) 574 #define TIM_DMABase_CR1 ((uint16_t)0x0000) 575 #define TIM_DMABase_CR2 ((uint16_t)0x0001) 576 #define TIM_DMABase_SMCR ((uint16_t)0x0002) 577 #define TIM_DMABase_DIER ((uint16_t)0x0003) 578 #define TIM_DMABase_SR ((uint16_t)0x0004) 579 #define TIM_DMABase_EGR ((uint16_t)0x0005) 580 #define TIM_DMABase_CCMR1 ((uint16_t)0x0006) 581 #define TIM_DMABase_CCMR2 ((uint16_t)0x0007) 582 #define TIM_DMABase_CCER ((uint16_t)0x0008) 583 #define TIM_DMABase_CNT ((uint16_t)0x0009) 584 #define TIM_DMABase_PSC ((uint16_t)0x000A) 585 #define TIM_DMABase_ARR ((uint16_t)0x000B) 586 #define TIM_DMABase_RCR ((uint16_t)0x000C) 587 #define TIM_DMABase_CCR1 ((uint16_t)0x000D) 588 #define TIM_DMABase_CCR2 ((uint16_t)0x000E) 589 #define TIM_DMABase_CCR3 ((uint16_t)0x000F) 590 #define TIM_DMABase_CCR4 ((uint16_t)0x0010) 591 #define TIM_DMABase_BDTR ((uint16_t)0x0011) 592 #define TIM_DMABase_DCR ((uint16_t)0x0012) 593 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ 594 ((BASE) == TIM_DMABase_CR2) || \ 595 ((BASE) == TIM_DMABase_SMCR) || \ 596 ((BASE) == TIM_DMABase_DIER) || \ 597 ((BASE) == TIM_DMABase_SR) || \ 598 ((BASE) == TIM_DMABase_EGR) || \ 599 ((BASE) == TIM_DMABase_CCMR1) || \ 600 ((BASE) == TIM_DMABase_CCMR2) || \ 601 ((BASE) == TIM_DMABase_CCER) || \ 602 ((BASE) == TIM_DMABase_CNT) || \ 603 ((BASE) == TIM_DMABase_PSC) || \ 604 ((BASE) == TIM_DMABase_ARR) || \ 605 ((BASE) == TIM_DMABase_RCR) || \ 606 ((BASE) == TIM_DMABase_CCR1) || \ 607 ((BASE) == TIM_DMABase_CCR2) || \ 608 ((BASE) == TIM_DMABase_CCR3) || \ 609 ((BASE) == TIM_DMABase_CCR4) || \ 610 ((BASE) == TIM_DMABase_BDTR) || \ 611 ((BASE) == TIM_DMABase_DCR)) 620 #define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) 621 #define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) 622 #define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) 623 #define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) 624 #define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) 625 #define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) 626 #define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) 627 #define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) 628 #define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) 629 #define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) 630 #define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) 631 #define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) 632 #define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) 633 #define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) 634 #define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) 635 #define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) 636 #define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) 637 #define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) 638 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ 639 ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ 640 ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ 641 ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ 642 ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ 643 ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ 644 ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ 645 ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ 646 ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ 647 ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ 648 ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ 649 ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ 650 ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ 651 ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ 652 ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ 653 ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ 654 ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ 655 ((LENGTH) == TIM_DMABurstLength_18Transfers)) 664 #define TIM_DMA_Update ((uint16_t)0x0100) 665 #define TIM_DMA_CC1 ((uint16_t)0x0200) 666 #define TIM_DMA_CC2 ((uint16_t)0x0400) 667 #define TIM_DMA_CC3 ((uint16_t)0x0800) 668 #define TIM_DMA_CC4 ((uint16_t)0x1000) 669 #define TIM_DMA_COM ((uint16_t)0x2000) 670 #define TIM_DMA_Trigger ((uint16_t)0x4000) 671 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) 680 #define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) 681 #define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) 682 #define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) 683 #define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) 684 #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ 685 ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ 686 ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ 687 ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) 696 #define TIM_TS_ITR0 ((uint16_t)0x0000) 697 #define TIM_TS_ITR1 ((uint16_t)0x0010) 698 #define TIM_TS_ITR2 ((uint16_t)0x0020) 699 #define TIM_TS_ITR3 ((uint16_t)0x0030) 700 #define TIM_TS_TI1F_ED ((uint16_t)0x0040) 701 #define TIM_TS_TI1FP1 ((uint16_t)0x0050) 702 #define TIM_TS_TI2FP2 ((uint16_t)0x0060) 703 #define TIM_TS_ETRF ((uint16_t)0x0070) 704 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ 705 ((SELECTION) == TIM_TS_ITR1) || \ 706 ((SELECTION) == TIM_TS_ITR2) || \ 707 ((SELECTION) == TIM_TS_ITR3) || \ 708 ((SELECTION) == TIM_TS_TI1F_ED) || \ 709 ((SELECTION) == TIM_TS_TI1FP1) || \ 710 ((SELECTION) == TIM_TS_TI2FP2) || \ 711 ((SELECTION) == TIM_TS_ETRF)) 712 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ 713 ((SELECTION) == TIM_TS_ITR1) || \ 714 ((SELECTION) == TIM_TS_ITR2) || \ 715 ((SELECTION) == TIM_TS_ITR3)) 724 #define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) 725 #define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) 726 #define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) 727 #define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \ 728 ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \ 729 ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED)) 737 #define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) 738 #define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) 739 #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ 740 ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) 749 #define TIM_PSCReloadMode_Update ((uint16_t)0x0000) 750 #define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) 751 #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ 752 ((RELOAD) == TIM_PSCReloadMode_Immediate)) 761 #define TIM_ForcedAction_Active ((uint16_t)0x0050) 762 #define TIM_ForcedAction_InActive ((uint16_t)0x0040) 763 #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ 764 ((ACTION) == TIM_ForcedAction_InActive)) 773 #define TIM_EncoderMode_TI1 ((uint16_t)0x0001) 774 #define TIM_EncoderMode_TI2 ((uint16_t)0x0002) 775 #define TIM_EncoderMode_TI12 ((uint16_t)0x0003) 776 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ 777 ((MODE) == TIM_EncoderMode_TI2) || \ 778 ((MODE) == TIM_EncoderMode_TI12)) 787 #define TIM_EventSource_Update ((uint16_t)0x0001) 788 #define TIM_EventSource_CC1 ((uint16_t)0x0002) 789 #define TIM_EventSource_CC2 ((uint16_t)0x0004) 790 #define TIM_EventSource_CC3 ((uint16_t)0x0008) 791 #define TIM_EventSource_CC4 ((uint16_t)0x0010) 792 #define TIM_EventSource_COM ((uint16_t)0x0020) 793 #define TIM_EventSource_Trigger ((uint16_t)0x0040) 794 #define TIM_EventSource_Break ((uint16_t)0x0080) 795 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) 804 #define TIM_UpdateSource_Global ((uint16_t)0x0000) 807 #define TIM_UpdateSource_Regular ((uint16_t)0x0001) 808 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ 809 ((SOURCE) == TIM_UpdateSource_Regular)) 818 #define TIM_OCPreload_Enable ((uint16_t)0x0008) 819 #define TIM_OCPreload_Disable ((uint16_t)0x0000) 820 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ 821 ((STATE) == TIM_OCPreload_Disable)) 830 #define TIM_OCFast_Enable ((uint16_t)0x0004) 831 #define TIM_OCFast_Disable ((uint16_t)0x0000) 832 #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ 833 ((STATE) == TIM_OCFast_Disable)) 842 #define TIM_OCClear_Enable ((uint16_t)0x0080) 843 #define TIM_OCClear_Disable ((uint16_t)0x0000) 844 #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ 845 ((STATE) == TIM_OCClear_Disable)) 853 #define TIM_TRGOSource_Reset ((uint16_t)0x0000) 854 #define TIM_TRGOSource_Enable ((uint16_t)0x0010) 855 #define TIM_TRGOSource_Update ((uint16_t)0x0020) 856 #define TIM_TRGOSource_OC1 ((uint16_t)0x0030) 857 #define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) 858 #define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) 859 #define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) 860 #define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) 861 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ 862 ((SOURCE) == TIM_TRGOSource_Enable) || \ 863 ((SOURCE) == TIM_TRGOSource_Update) || \ 864 ((SOURCE) == TIM_TRGOSource_OC1) || \ 865 ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ 866 ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ 867 ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ 868 ((SOURCE) == TIM_TRGOSource_OC4Ref)) 877 #define TIM_SlaveMode_Reset ((uint16_t)0x0004) 878 #define TIM_SlaveMode_Gated ((uint16_t)0x0005) 879 #define TIM_SlaveMode_Trigger ((uint16_t)0x0006) 880 #define TIM_SlaveMode_External1 ((uint16_t)0x0007) 881 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ 882 ((MODE) == TIM_SlaveMode_Gated) || \ 883 ((MODE) == TIM_SlaveMode_Trigger) || \ 884 ((MODE) == TIM_SlaveMode_External1)) 893 #define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) 894 #define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) 895 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ 896 ((STATE) == TIM_MasterSlaveMode_Disable)) 905 #define TIM_FLAG_Update ((uint16_t)0x0001) 906 #define TIM_FLAG_CC1 ((uint16_t)0x0002) 907 #define TIM_FLAG_CC2 ((uint16_t)0x0004) 908 #define TIM_FLAG_CC3 ((uint16_t)0x0008) 909 #define TIM_FLAG_CC4 ((uint16_t)0x0010) 910 #define TIM_FLAG_COM ((uint16_t)0x0020) 911 #define TIM_FLAG_Trigger ((uint16_t)0x0040) 912 #define TIM_FLAG_Break ((uint16_t)0x0080) 913 #define TIM_FLAG_CC1OF ((uint16_t)0x0200) 914 #define TIM_FLAG_CC2OF ((uint16_t)0x0400) 915 #define TIM_FLAG_CC3OF ((uint16_t)0x0800) 916 #define TIM_FLAG_CC4OF ((uint16_t)0x1000) 917 #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ 918 ((FLAG) == TIM_FLAG_CC1) || \ 919 ((FLAG) == TIM_FLAG_CC2) || \ 920 ((FLAG) == TIM_FLAG_CC3) || \ 921 ((FLAG) == TIM_FLAG_CC4) || \ 922 ((FLAG) == TIM_FLAG_COM) || \ 923 ((FLAG) == TIM_FLAG_Trigger) || \ 924 ((FLAG) == TIM_FLAG_Break) || \ 925 ((FLAG) == TIM_FLAG_CC1OF) || \ 926 ((FLAG) == TIM_FLAG_CC2OF) || \ 927 ((FLAG) == TIM_FLAG_CC3OF) || \ 928 ((FLAG) == TIM_FLAG_CC4OF)) 931 #define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) 940 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) 949 #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) 958 #define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer 959 #define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers 960 #define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers 961 #define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers 962 #define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers 963 #define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers 964 #define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers 965 #define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers 966 #define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers 967 #define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers 968 #define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers 969 #define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers 970 #define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers 971 #define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers 972 #define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers 973 #define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers 974 #define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers 975 #define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers 1009 uint16_t TIM_ICPolarity, uint16_t ICFilter);
1011 uint16_t ExtTRGFilter);
1013 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
1015 uint16_t ExtTRGFilter);
1020 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
uint16_t TIM_Break
Definition: mg32f157_tim.h:139
void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIMx's Hall sensor interface.
Definition: mg32f157_tim.c:2060
void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIM peripheral Main Outputs.
Definition: mg32f157_tim.c:738
void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIMx peripheral Capture Compare DMA source.
Definition: mg32f157_tim.c:1375
uint16_t TIM_BreakPolarity
Definition: mg32f157_tim.h:142
void TIM_SetCompare2(TIM_TypeDef *TIMx, uint32_t Compare2)
Sets the TIMx Capture Compare2 Register value.
Definition: mg32f157_tim.c:2219
void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the specified TIM peripheral.
Definition: mg32f157_tim.c:713
uint16_t TIM_DeadTime
Definition: mg32f157_tim.h:135
void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF4 signal on an external event.
Definition: mg32f157_tim.c:1698
void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 3 Fast feature.
Definition: mg32f157_tim.c:1574
uint16_t TIM_Prescaler
Definition: mg32f157_tim.h:37
uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx)
Gets the TIMx Prescaler value.
Definition: mg32f157_tim.c:2435
void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 2 prescaler.
Definition: mg32f157_tim.c:2288
void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 3 prescaler.
Definition: mg32f157_tim.c:2310
void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 3 polarity.
Definition: mg32f157_tim.c:1816
uint32_t TIM_GetCapture2(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 2 value.
Definition: mg32f157_tim.c:2383
uint16_t TIM_ICPolarity
Definition: mg32f157_tim.h:105
uint16_t TIM_OSSRState
Definition: mg32f157_tim.h:126
void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct)
Fills each TIM_OCInitStruct member with its default value.
Definition: mg32f157_tim.c:659
void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct.
Definition: mg32f157_tim.c:347
void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF1 signal on an external event.
Definition: mg32f157_tim.c:1624
void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode)
Selects the TIMx's One Pulse Mode.
Definition: mg32f157_tim.c:2086
uint32_t TIM_Period
Definition: mg32f157_tim.h:43
void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR3.
Definition: mg32f157_tim.c:1475
void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 2N polarity.
Definition: mg32f157_tim.c:1792
void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Configures the TIMx Internal Trigger as External Clock.
Definition: mg32f157_tim.c:925
void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIM peripheral Commutation event.
Definition: mg32f157_tim.c:1350
void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 4 Fast feature.
Definition: mg32f157_tim.c:1599
void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 3 waveform to active or inactive level.
Definition: mg32f157_tim.c:1280
void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
Definition: mg32f157_tim.c:1065
void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables TIMx peripheral Preload register on ARR.
Definition: mg32f157_tim.c:1326
uint32_t TIM_GetCapture3(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 3 value.
Definition: mg32f157_tim.c:2396
void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
Enables or disables the TIM Capture Compare Channel x.
Definition: mg32f157_tim.c:1891
void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode2.
Definition: mg32f157_tim.c:1034
void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 2 waveform to active or inactive level.
Definition: mg32f157_tim.c:1256
void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
Configures the TIMx Prescaler.
Definition: mg32f157_tim.c:1093
uint16_t TIM_OCNPolarity
Definition: mg32f157_tim.h:82
uint16_t TIM_OCNIdleState
Definition: mg32f157_tim.h:90
void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct.
Definition: mg32f157_tim.c:179
uint16_t TIM_ClockDivision
Definition: mg32f157_tim.h:47
void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel2 according to the specified parameters in the TIM_OCInitStruct.
Definition: mg32f157_tim.c:263
void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct)
Fills each TIM_ICInitStruct member with its default value.
Definition: mg32f157_tim.c:678
void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
Enables or disables the TIMx's DMA Requests.
Definition: mg32f157_tim.c:881
void TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
Sets the TIMx Counter Register value.
Definition: mg32f157_tim.c:2177
uint16_t TIM_ICPrescaler
Definition: mg32f157_tim.h:111
void TIM_SetCompare3(TIM_TypeDef *TIMx, uint32_t Compare3)
Sets the TIMx Capture Compare3 Register value.
Definition: mg32f157_tim.c:2233
void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode1.
Definition: mg32f157_tim.c:992
void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or Disables the TIMx Update event.
Definition: mg32f157_tim.c:2009
void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 1 waveform to active or inactive level.
Definition: mg32f157_tim.c:1232
void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct.
Definition: mg32f157_tim.c:494
uint16_t TIM_OSSIState
Definition: mg32f157_tim.h:129
void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Clears the TIMx's pending flags.
Definition: mg32f157_tim.c:2509
void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 4 prescaler.
Definition: mg32f157_tim.c:2332
uint32_t TIM_Pulse
Definition: mg32f157_tim.h:76
void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF3 signal on an external event.
Definition: mg32f157_tim.c:1674
TIM Output Compare Init structure definition.
Definition: mg32f157_tim.h:64
void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
Configures the: Break feature, dead time, Lock level, the OSSI, the OSSR State and the AOE(automatic ...
Definition: mg32f157_tim.c:619
TIM Time Base Init structure definition.
Definition: mg32f157_tim.h:35
void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState)
Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
Definition: mg32f157_tim.c:1400
void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode)
Sets or Resets the TIMx Master/Slave Mode.
Definition: mg32f157_tim.c:2159
void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF2 signal on an external event.
Definition: mg32f157_tim.c:1650
void TIM_SetCompare1(TIM_TypeDef *TIMx, uint32_t Compare1)
Sets the TIMx Capture Compare1 Register value.
Definition: mg32f157_tim.c:2205
FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Checks whether the specified TIM flag is set or not.
Definition: mg32f157_tim.c:2467
void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
Configures the TIMx Encoder Interface.
Definition: mg32f157_tim.c:1181
void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 1 prescaler.
Definition: mg32f157_tim.c:2266
void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD)
Sets the TIMx Clock Division value.
Definition: mg32f157_tim.c:2354
Definition: mg32f157.h:889
void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR1.
Definition: mg32f157_tim.c:1426
uint16_t TIM_Channel
Definition: mg32f157_tim.h:102
void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
Selects the TIM Output Compare Mode.
Definition: mg32f157_tim.c:1962
void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT)
Clears the TIMx's interrupt pending bits.
Definition: mg32f157_tim.c:2581
void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 1N polarity.
Definition: mg32f157_tim.c:1745
uint32_t TIM_GetCapture1(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 1 value.
Definition: mg32f157_tim.c:2370
uint16_t TIM_OCMode
Definition: mg32f157_tim.h:66
uint32_t TIM_GetCounter(TIM_TypeDef *TIMx)
Gets the TIMx Counter value.
Definition: mg32f157_tim.c:2422
void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload)
Sets the TIMx Autoreload Register value.
Definition: mg32f157_tim.c:2191
void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource)
Configures the TIMx event to be generate by software.
Definition: mg32f157_tim.c:814
uint16_t TIM_LOCKLevel
Definition: mg32f157_tim.h:132
uint16_t TIM_ICSelection
Definition: mg32f157_tim.h:108
void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource)
Configures the TIMx Update Request Interrupt source.
Definition: mg32f157_tim.c:2036
uint16_t TIM_OCPolarity
Definition: mg32f157_tim.h:79
void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 1 polarity.
Definition: mg32f157_tim.c:1722
void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 4 polarity.
Definition: mg32f157_tim.c:1864
void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter)
Configures the TIMx Trigger as External Clock.
Definition: mg32f157_tim.c:952
void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode)
Specifies the TIMx Counter Mode to be used.
Definition: mg32f157_tim.c:1116
void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Initializes the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_TimeB...
Definition: mg32f157_tim.c:126
void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
Enables or disables the TIM Capture Compare Channel xN.
Definition: mg32f157_tim.c:1921
ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT)
Checks whether the TIM interrupt has occurred or not.
Definition: mg32f157_tim.c:2539
void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 4 waveform to active or inactive level.
Definition: mg32f157_tim.c:1304
void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Selects the Input Trigger source.
Definition: mg32f157_tim.c:1146
TIM Input Capture Init structure definition.
Definition: mg32f157_tim.h:99
void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode)
Selects the TIMx Slave Mode.
Definition: mg32f157_tim.c:2138
void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
Fills each TIM_BDTRInitStruct member with its default value.
Definition: mg32f157_tim.c:694
void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 2 polarity.
Definition: mg32f157_tim.c:1769
void TIM_DeInit(TIM_TypeDef *TIMx)
Deinitializes the TIMx peripheral registers to their default reset values.
Definition: mg32f157_tim.c:70
uint16_t TIM_OutputState
Definition: mg32f157_tim.h:69
void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 1 Fast feature.
Definition: mg32f157_tim.c:1523
uint32_t TIM_GetCapture4(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 4 value.
Definition: mg32f157_tim.c:2409
uint16_t TIM_OCIdleState
Definition: mg32f157_tim.h:86
void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
Configures the TIMx's DMA interface.
Definition: mg32f157_tim.c:854
uint16_t TIM_AutomaticOutput
Definition: mg32f157_tim.h:145
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Fills each TIM_TimeBaseInitStruct member with its default value.
Definition: mg32f157_tim.c:643
void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState)
Enables or disables the specified TIM interrupts.
Definition: mg32f157_tim.c:777
void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource)
Selects the TIMx Trigger Output Mode.
Definition: mg32f157_tim.c:2115
uint16_t TIM_CounterMode
Definition: mg32f157_tim.h:40
void TIM_InternalClockConfig(TIM_TypeDef *TIMx)
Configures the TIMx internal Clock.
Definition: mg32f157_tim.c:906
void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR2.
Definition: mg32f157_tim.c:1451
void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 2 Fast feature.
Definition: mg32f157_tim.c:1549
uint16_t TIM_OutputNState
Definition: mg32f157_tim.h:72
uint16_t TIM_ICFilter
Definition: mg32f157_tim.h:114
void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR4.
Definition: mg32f157_tim.c:1499
void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 3N polarity.
Definition: mg32f157_tim.c:1839
BDTR structure definition.
Definition: mg32f157_tim.h:123
void TIM_SetCompare4(TIM_TypeDef *TIMx, uint32_t Compare4)
Sets the TIMx Capture Compare4 Register value.
Definition: mg32f157_tim.c:2247
uint8_t TIM_RepetitionCounter
Definition: mg32f157_tim.h:50
void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measur...
Definition: mg32f157_tim.c:561
void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel4 according to the specified parameters in the TIM_OCInitStruct.
Definition: mg32f157_tim.c:428