MG32F157 Standard Peripherals Firmware Library
Data Fields
QUADSPI_TypeDef Struct Reference

Data Fields

__IO uint32_t CR
 
__IO uint32_t DCR
 
__IO uint32_t SR
 
__IO uint32_t FCR
 
__IO uint32_t DLR
 
__IO uint32_t CCR
 
__IO uint32_t AR
 
__IO uint32_t ABR
 
__IO uint32_t DR
 
__IO uint32_t PSMKR
 
__IO uint32_t PSMAR
 
__IO uint32_t PIR
 
__IO uint32_t LPTR
 

Field Documentation

◆ ABR

__IO uint32_t ABR

QUADSPI alternate bytes registers, Address offset: 0x01C

◆ AR

__IO uint32_t AR

QUADSPI address register, Address offset: 0x018

◆ CCR

__IO uint32_t CCR

QUADSPI communication configuration register, Address offset: 0x014

◆ CR

__IO uint32_t CR

QUADSPI control register, Address offset: 0x000

◆ DCR

__IO uint32_t DCR

QUADSPI device configuration register, Address offset: 0x004

◆ DLR

__IO uint32_t DLR

QUADSPI data length register, Address offset: 0x010

◆ DR

__IO uint32_t DR

QUADSPI data register, Address offset: 0x020

◆ FCR

__IO uint32_t FCR

QUADSPI flag clear register, Address offset: 0x00C

◆ LPTR

__IO uint32_t LPTR

QUADSPI low-power timeout register, Address offset: 0x030

◆ PIR

__IO uint32_t PIR

QUADSPI polling interval register, Address offset: 0x02C

◆ PSMAR

__IO uint32_t PSMAR

QUADSPI polling status match register, Address offset: 0x028

◆ PSMKR

__IO uint32_t PSMKR

QUADSPI polling status mask register, Address offset: 0x024

◆ SR

__IO uint32_t SR

QUADSPI status register, Address offset: 0x008


The documentation for this struct was generated from the following file: