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#define | FLASH_BASE ((uint32_t)0x08000000) |
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#define | SRAM_BASE ((uint32_t)0x20000000) |
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#define | PERIPH_BASE ((uint32_t)0x40000000) |
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#define | SRAM_BB_BASE ((uint32_t)0x22000000) |
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#define | PERIPH_BB_BASE ((uint32_t)0x42000000) |
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#define | APB1PERIPH_BASE PERIPH_BASE |
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#define | APB2PERIPH_BASE (PERIPH_BASE + 0x10000) |
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#define | AHBPERIPH_BASE (PERIPH_BASE + 0x20000) |
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#define | TIM2_BASE (APB1PERIPH_BASE + 0x0000) |
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#define | TIM3_BASE (APB1PERIPH_BASE + 0x0400) |
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#define | TIM4_BASE (APB1PERIPH_BASE + 0x0800) |
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#define | TIM5_BASE (APB1PERIPH_BASE + 0x0C00) |
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#define | TIM6_BASE (APB1PERIPH_BASE + 0x1000) |
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#define | TIM7_BASE (APB1PERIPH_BASE + 0x1400) |
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#define | RTC_BASE (APB1PERIPH_BASE + 0x2800) |
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#define | WWDG_BASE (APB1PERIPH_BASE + 0x2C00) |
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#define | IWDG_BASE (APB1PERIPH_BASE + 0x3000) |
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#define | SPI2_BASE (APB1PERIPH_BASE + 0x3800) |
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#define | SPI3_BASE (APB1PERIPH_BASE + 0x3C00) |
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#define | USART2_BASE (APB1PERIPH_BASE + 0x4400) |
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#define | USART3_BASE (APB1PERIPH_BASE + 0x4800) |
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#define | UART4_BASE (APB1PERIPH_BASE + 0x4C00) |
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#define | UART5_BASE (APB1PERIPH_BASE + 0x5000) |
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#define | I2C1_BASE (APB1PERIPH_BASE + 0x5400) |
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#define | I2C2_BASE (APB1PERIPH_BASE + 0x5800) |
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#define | CAN1_BASE (APB1PERIPH_BASE + 0x6400) |
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#define | BKP_BASE (APB1PERIPH_BASE + 0x6C00) |
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#define | PWR_BASE (APB1PERIPH_BASE + 0x7000) |
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#define | DAC_BASE (APB1PERIPH_BASE + 0x7400) |
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#define | AFIO_BASE (APB2PERIPH_BASE + 0x0000) |
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#define | OPA1_BASE (APB2PERIPH_BASE + 0x0200) |
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#define | OPA2_BASE (APB2PERIPH_BASE + 0x0280) |
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#define | OPA3_BASE (APB2PERIPH_BASE + 0x0300) |
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#define | EXTI_BASE (APB2PERIPH_BASE + 0x0400) |
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#define | GPIOA_BASE (APB2PERIPH_BASE + 0x0800) |
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#define | GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) |
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#define | GPIOC_BASE (APB2PERIPH_BASE + 0x1000) |
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#define | GPIOD_BASE (APB2PERIPH_BASE + 0x1400) |
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#define | GPIOE_BASE (APB2PERIPH_BASE + 0x1800) |
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#define | ADC1_BASE (APB2PERIPH_BASE + 0x2400) |
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#define | ADC2_BASE (APB2PERIPH_BASE + 0x2800) |
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#define | TIM1_BASE (APB2PERIPH_BASE + 0x2C00) |
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#define | SPI1_BASE (APB2PERIPH_BASE + 0x3000) |
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#define | TIM8_BASE (APB2PERIPH_BASE + 0x3400) |
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#define | USART1_BASE (APB2PERIPH_BASE + 0x3800) |
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#define | ADC3_BASE (APB2PERIPH_BASE + 0x3C00) |
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#define | QUADSPI_BASE (APB2PERIPH_BASE + 0x4000) |
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#define | USB_BASE (PERIPH_BASE + 0x5C00) |
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#define | SDIO_BASE (PERIPH_BASE + 0x18000) |
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#define | DMAC1_BASE (AHBPERIPH_BASE + 0x0000) |
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#define | DMAC2_BASE (AHBPERIPH_BASE + 0x0400) |
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#define | RCC_BASE (AHBPERIPH_BASE + 0x1000) |
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#define | CRC_BASE (AHBPERIPH_BASE + 0x3000) |
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#define | TRNG_BASE (AHBPERIPH_BASE + 0x5000) |
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#define | AES_BASE (AHBPERIPH_BASE + 0x6000) |
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#define | FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) |
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#define | OB_BASE ((uint32_t)0x1FFFF800) |
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#define | DBGMCU_BASE ((uint32_t)0xE0042000) |
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