11 #ifndef __MG32F157_DMAC_H 12 #define __MG32F157_DMAC_H 36 FunctionalState DMAC_SourceGather;
37 uint32_t DMAC_SourceGatherCount;
38 uint32_t DMAC_SourceGatherInterval;
46 FunctionalState DMAC_DestinationScatter;
47 uint32_t DMAC_DestinationScatterCount;
48 uint32_t DMAC_DestinationScatterInterval;
141 #define DMAC_Interrupt_Enable ((uint32_t)0x00000001) 142 #define DMAC_Interrupt_Disable ((uint32_t)0x00000000) 151 #define DMAC_SourceTransferWidth_8b DMAC_CTLL_SRC_TR_WIDTH_8 152 #define DMAC_SourceTransferWidth_16b DMAC_CTLL_SRC_TR_WIDTH_16 153 #define DMAC_SourceTransferWidth_32b DMAC_CTLL_SRC_TR_WIDTH_32 162 #define DMAC_DestinationTransferWidth_8b DMAC_CTLL_DST_TR_WIDTH_8 163 #define DMAC_DestinationTransferWidth_16b DMAC_CTLL_DST_TR_WIDTH_16 164 #define DMAC_DestinationTransferWidth_32b DMAC_CTLL_DST_TR_WIDTH_32 173 #define DMAC_SourceAddrInc_Increment DMAC_CTLL_SINC_INC 174 #define DMAC_SourceAddrInc_Decrement DMAC_CTLL_SINC_DEC 175 #define DMAC_SourceAddrInc_NoChange DMAC_CTLL_SINC_NO 184 #define DMAC_DestinationAddrInc_Increment DMAC_CTLL_DINC_INC 185 #define DMAC_DestinationAddrInc_Decrement DMAC_CTLL_DINC_DEC 186 #define DMAC_DestinationAddrInc_NoChange DMAC_CTLL_DINC_NO 195 #define DMAC_SourceTransactionLength_1 DMAC_CTLL_SRC_MSIZE_1 196 #define DMAC_SourceTransactionLength_4 DMAC_CTLL_SRC_MSIZE_4 197 #define DMAC_SourceTransactionLength_8 DMAC_CTLL_SRC_MSIZE_8 206 #define DMAC_DestinationTransactionLength_1 DMAC_CTLL_DEST_MSIZE_1 207 #define DMAC_DestinationTransactionLength_4 DMAC_CTLL_DEST_MSIZE_4 208 #define DMAC_DestinationTransactionLength_8 DMAC_CTLL_DEST_MSIZE_8 217 #define DMAC_TransferTypeAndFlowControl_MemoryToMemory_DMAC DMAC_CTLL_TT_FC_M2M_DMAC 218 #define DMAC_TransferTypeAndFlowControl_MemoryToPeripheral_DMAC DMAC_CTLL_TT_FC_M2P_DMAC 219 #define DMAC_TransferTypeAndFlowControl_PeripheralToMemory_DMAC DMAC_CTLL_TT_FC_P2M_DMAC 220 #define DMAC_TransferTypeAndFlowControl_PeripheralToPeripheral_DMAC DMAC_CTLL_TT_FC_P2P_DMAC 222 #define DMAC_TransferTypeAndFlowControl_PeripheralToMemory_Peripheral DMAC_CTLL_TT_FC_P2M_PERIPH 223 #define DMAC_TransferTypeAndFlowControl_PeripheralToPeripheral_SourcePeripheral DMAC_CTLL_TT_FC_P2P_SRC_PERIPH 224 #define DMAC_TransferTypeAndFlowControl_MemoryToPeripheral_Peripheral DMAC_CTLL_TT_FC_M2P_PERIPH 225 #define DMAC_TransferTypeAndFlowControl_PeripheralToPeripheral_DestinationPeripheral DMAC_CTLL_TT_FC_P2P_DST_PERIPH 234 #define DMAC_SourceHandshakingInterfaceSelect_Hardware (0x0U << 11) 235 #define DMAC_SourceHandshakingInterfaceSelect_Software (0x1U << 11) 244 #define DMAC_DestinationHandshakingInterfaceSelect_Hardware (0x0U << 10) 245 #define DMAC_DestinationHandshakingInterfaceSelect_Software (0x1U << 10) 254 #define DMAC_SourceHandshakingInterfacePolarity_High (0x0U << 19) 255 #define DMAC_SourceHandshakingInterfacePolarity_Low (0x1U << 19) 264 #define DMAC_DestinationHandshakingInterfacePolarity_High (0x0U << 18) 265 #define DMAC_DestinationHandshakingInterfacePolarity_Low (0x1U << 18) 274 #define DMAC_AutomaticSourceReload_Enable (DMAC_CFGL_RELOAD_SRC) 275 #define DMAC_AutomaticSourceReload_Disable ((uint32_t)0x00000000) 284 #define DMAC_AutomaticDestinationReload_Enable (DMAC_CFGL_RELOAD_DST) 285 #define DMAC_AutomaticDestinationReload_Disable ((uint32_t)0x00000000) 294 #define DMAC_FlowControlMode_0 (0x0 << 0) 295 #define DMAC_FlowControlMode_1 (0x1 << 0) 304 #define DMAC_FIFOMode_0 (0x0 << 1) 305 #define DMAC_FIFOMode_1 (0x1 << 1) 315 #define DMAC_HardwareHandshakingInterface_ADC1__TIM2_CH3__TIM4_CH1__QSPI0__AES_RX 0 316 #define DMAC_HardwareHandshakingInterface_USART3_TX__TIM1_CH1__TIM2_UP__TIM3_CH3__SPI1_RX__AES_TX 1 317 #define DMAC_HardwareHandshakingInterface_USART3_RX__TIM1_CH2__TIM3_CH4__TIM3_UP__SPI1_TX 2 318 #define DMAC_HardwareHandshakingInterface_USART1_TX__TIM1_CH4__TIM1_TRIG__TIM1_COM__TIM4_CH2__SPI2_RX__I2C2_TX 3 319 #define DMAC_HardwareHandshakingInterface_USART1_RX__TIM1_UP__SPI2_TX__TIM2_CH1__TIM4_CH3__I2C2_RX 4 320 #define DMAC_HardwareHandshakingInterface_USART2_RX__TIM1_CH3__TIM3_CH1__TIM3_TRIG__I2C1_TX 5 321 #define DMAC_HardwareHandshakingInterface_USART2_TX__TIM2_CH2__TIM2_CH4__TIM4_UP_I2C1_RX 6 324 #define DMAC_HardwareHandshakingInterface_TIM5_CH4__TIM5_TRIG__TIM8_CH3__TIM8_UP__SPI3_RX 0 325 #define DMAC_HardwareHandshakingInterface_TIM8_CH4__TIM8_TRIG__TIM8_COM__TIM5_CH3__TIM5_UP__SPI3_TX 1 326 #define DMAC_HardwareHandshakingInterface_TIM8_CH1__UART4_RX__TIM6_UP__DAC1 2 327 #define DMAC_HardwareHandshakingInterface_TIM5_CH2__SDIO__TIM7_UP__DAC2 3 328 #define DMAC_HardwareHandshakingInterface_ADC3__TIM8_CH2__TIM5_CH1__UART4_TX 4 337 #define DMAC_Channel_1 ((uint8_t)0x00) 338 #define DMAC_Channel_2 ((uint8_t)0x01) 339 #define DMAC_Channel_3 ((uint8_t)0x02) 340 #define DMAC_Channel_4 ((uint8_t)0x03) 341 #define DMAC_Channel_5 ((uint8_t)0x04) 342 #define DMAC_Channel_6 ((uint8_t)0x05) 343 #define DMAC_Channel_7 ((uint8_t)0x06) 352 #define DMAC_IT_TFR ((uint16_t)0x0000) 353 #define DMAC_IT_BLOCK ((uint16_t)0x0008) 354 #define DMAC_IT_SRCTRAN ((uint16_t)0x0010) 355 #define DMAC_IT_DSTTRAN ((uint16_t)0x0018) 356 #define DMAC_IT_ERR ((uint16_t)0x0020) SignalState DMAC_SWHS_GetLstDstSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel)
Returns the state of LstDst signal for the corresponding channel.
Definition: mg32f157_dmac.c:992
uint8_t DMAC_ProtectionControl
Definition: mg32f157_dmac.h:115
SignalState DMAC_SWHS_GetSglReqDstSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel)
Returns the state of SglReqDst signal for the corresponding channel.
Definition: mg32f157_dmac.c:928
DMAC Destination Scatter Structure definition.
Definition: mg32f157_dmac.h:44
uint32_t DMAC_FIFOMode
Definition: mg32f157_dmac.h:110
uint32_t DMAC_DestinationHandshakingInterfaceSelect
Definition: mg32f157_dmac.h:91
void DMAC_ChannelCmd(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, FunctionalState NewState)
Enables or disables the specified DMACx Channely.
Definition: mg32f157_dmac.c:405
uint32_t DMAC_Interrupt
Definition: mg32f157_dmac.h:60
DMAC Channel Init Structure definition.
Definition: mg32f157_dmac.h:54
DMAC Source Gather Structure definition.
Definition: mg32f157_dmac.h:34
void DMAC_SWHS_SetReqDstSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, SignalState NewState)
Controls the state of ReqDst signal for the corresponding channels.
Definition: mg32f157_dmac.c:682
void DMAC_DeInit(DMAC_TypeDef *DMACx)
Deinitializes the DMACx peripheral registers to their default reset values.
Definition: mg32f157_dmac.c:40
uint32_t DMAC_SourceHandshakingInterfacePolarity
Definition: mg32f157_dmac.h:95
uint32_t DMAC_SourceAddrInc
Definition: mg32f157_dmac.h:69
uint8_t DMAC_ChannelPriority
Definition: mg32f157_dmac.h:113
uint32_t DMAC_DestinationAddrInc
Definition: mg32f157_dmac.h:72
void DMAC_Channel_StructInit(DMAC_Channel_InitTypeDef *DMAC_Channel_InitStruct)
Fills each DMAC_Channel_InitStruct member with its default value.
Definition: mg32f157_dmac.c:156
uint32_t DMAC_SourceBaseAddr
Definition: mg32f157_dmac.h:56
void DMAC_SWHS_SetReqSrcSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, SignalState NewState)
Controls the state of ReqSrc signal for the corresponding channels.
Definition: mg32f157_dmac.c:652
void DMAC_Cmd(DMAC_TypeDef *DMACx, FunctionalState NewState)
Enables or disables the specified DMACx peripheral.
Definition: mg32f157_dmac.c:355
uint8_t DMAC_DestinationHardwareHandshakingInterfaceAssign
Definition: mg32f157_dmac.h:123
ITStatus DMAC_GetITStatus(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, uint16_t DMAC_IT)
Checks whether the specified DMACx Channely interrupt has occurred or not.
Definition: mg32f157_dmac.c:554
uint16_t DMAC_MaximumAMBABurstLength
Definition: mg32f157_dmac.h:127
void DMAC_Channel_SuspendCmd(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, FunctionalState NewState)
Forces or releases the current DMACx Channely transfer suspend.
Definition: mg32f157_dmac.c:301
void DMAC_ITConfig(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, uint16_t DMAC_IT, FunctionalState NewState)
Enables or disables the specified DMACx Channely interrupts.
Definition: mg32f157_dmac.c:474
void DMAC_ClearITPendingBit(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, uint16_t DMAC_IT)
Clears the DMACx's interrupt pending bits.
Definition: mg32f157_dmac.c:624
uint16_t DMAC_Channel_GetBlockTransferSize(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel)
Returns the number of remaining data units in the current DMACx Channely block transfer.
Definition: mg32f157_dmac.c:278
uint8_t DMAC_SourceHardwareHandshakingInterfaceAssign
Definition: mg32f157_dmac.h:119
void DMAC_SWHS_SetSglReqSrcSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, SignalState NewState)
Controls the state of SglReqSrc signal for the corresponding channels.
Definition: mg32f157_dmac.c:712
uint32_t DMAC_AutomaticSourceReload
Definition: mg32f157_dmac.h:101
Definition: mg32f157.h:460
uint32_t DMAC_AutomaticDestinationReload
Definition: mg32f157_dmac.h:104
SignalState DMAC_SWHS_GetSglReqSrcSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel)
Returns the state of SglReqSrc signal for the corresponding channel.
Definition: mg32f157_dmac.c:896
uint32_t DMAC_DestinationHandshakingInterfacePolarity
Definition: mg32f157_dmac.h:98
void DMAC_Channel_SetDestinationAddress(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, uint32_t DestinationAddress)
Sets the destination address of the specified DMACx Channely.
Definition: mg32f157_dmac.c:234
void DMAC_Channel_Init(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, DMAC_Channel_InitTypeDef *DMAC_Channel_InitStruct)
Initializes the DMACx Channely according to the specified parameters in the DMAC_Channel_InitStruct s...
Definition: mg32f157_dmac.c:118
FlagStatus DMAC_Channel_IsFIFOEmpty(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel)
Checks whether the DMACx Channely FIFO is empty or not.
Definition: mg32f157_dmac.c:327
void DMAC_Channel_SetSourceAddress(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, uint32_t SourceAddress)
Sets the source address of the specified DMACx Channely.
Definition: mg32f157_dmac.c:212
SignalState DMAC_SWHS_GetLstSrcSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel)
Returns the state of LstSrc signal for the corresponding channel.
Definition: mg32f157_dmac.c:960
FunctionalState DMAC_GetCmdStatus(DMAC_TypeDef *DMACx)
Returns the status of EN bit for the specified DMACx.
Definition: mg32f157_dmac.c:372
ITStatus DMAC_GetCombinedITStatus(DMAC_TypeDef *DMACx, uint16_t DMAC_IT)
Checks whether the specified DMACx interrupt has occurred or not.
Definition: mg32f157_dmac.c:585
void DMAC_SWHS_SetLstDstSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, SignalState NewState)
Controls the state of LstDst signal for the corresponding channels.
Definition: mg32f157_dmac.c:802
FunctionalState DMAC_GetChannelCmdStatus(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel)
Returns the status of EN bit for the specified DMACx Channely.
Definition: mg32f157_dmac.c:433
uint32_t DMAC_SourceTransactionLength
Definition: mg32f157_dmac.h:75
void DMAC_Channel_SetBlockTransferSize(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, uint16_t DMAC_BlockTransferSize)
Sets the number of data units to be transferred on the block transfer.
Definition: mg32f157_dmac.c:257
uint32_t DMAC_BlockTransferSize
Definition: mg32f157_dmac.h:84
SignalState DMAC_SWHS_GetReqDstSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel)
Returns the state of ReqDst signal for the corresponding channel.
Definition: mg32f157_dmac.c:864
uint32_t DMAC_TransferTypeAndFlowControl
Definition: mg32f157_dmac.h:81
uint32_t DMAC_DestinationTransferWidth
Definition: mg32f157_dmac.h:66
void DMAC_SWHS_SetSglReqDstSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, SignalState NewState)
Controls the state of SglReqDst signal for the corresponding channels.
Definition: mg32f157_dmac.c:742
SignalState DMAC_SWHS_GetReqSrcSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel)
Returns the state of ReqSrc signal for the corresponding channel.
Definition: mg32f157_dmac.c:832
uint32_t DMAC_DestinationTransactionLength
Definition: mg32f157_dmac.h:78
uint32_t DMAC_SourceHandshakingInterfaceSelect
Definition: mg32f157_dmac.h:87
void DMAC_SWHS_SetLstSrcSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, SignalState NewState)
Controls the state of LstSrc signal for the corresponding channels.
Definition: mg32f157_dmac.c:772
uint32_t DMAC_SourceTransferWidth
Definition: mg32f157_dmac.h:63
uint32_t DMAC_DestinationBaseAddr
Definition: mg32f157_dmac.h:58
ITStatus DMAC_GetRawITStatus(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, uint16_t DMAC_IT)
Checks whether the specified DMACx Channely raw interrupt status.
Definition: mg32f157_dmac.c:514
uint32_t DMAC_FlowControlMode
Definition: mg32f157_dmac.h:107