MG32F157 Standard Peripherals Firmware Library
Data Fields
USB_TypeDef Struct Reference

Data Fields

__IOM uint8_t FADDR
 
__IOM uint8_t POWER
 
__IM uint16_t INTRTX
 
__IM uint16_t INTRRX
 
__IOM uint16_t INTRTXE
 
__IOM uint16_t INTRRXE
 
__IM uint8_t INTRUSB
 
__IOM uint8_t INTRUSBE
 
__IM uint16_t FRAME
 
__IOM uint8_t INDEX
 
__IOM uint8_t TESTMODE
 
__IOM uint16_t TXMAXP
 
union {
   __IOM uint8_t   CSR0L
 
   __IOM uint8_t   TXCSRL
 
}; 
 
union {
   __IOM uint8_t   CSR0H
 
   __IOM uint8_t   TXCSRH
 
}; 
 
__IOM uint16_t RXMAXP
 
__IOM uint8_t RXCSRL
 
__IOM uint8_t RXCSRH
 
union {
   __IM uint16_t   COUNT0
 
   __IM uint16_t   RXCOUNT
 
}; 
 
union {
   __IOM uint8_t   TYPE0
 
   __IOM uint8_t   TXTYPE
 
}; 
 
union {
   __IOM uint8_t   NAKLIMIT0
 
   __IOM uint8_t   TXINTERVAL
 
}; 
 
__IOM uint8_t RXTYPE
 
__IOM uint8_t RXINTERVAL
 
uint8_t RESERVED1
 
union {
   __IOM uint8_t   CONFIGDATA
 
   __IOM uint8_t   FIFOSIZE
 
}; 
 
__IOM uint32_t FIFO [16]
 
__IOM uint8_t DEVCTL
 
__IOM uint8_t MISC
 
__IOM uint8_t TXFIFOSZ
 
__IOM uint8_t RXFIFOSZ
 
__IOM uint16_t TXFIFOADD
 
__IOM uint16_t RXFIFOADD
 
union {
   __OM uint32_t   VCONTROL
 
   __IM uint32_t   VSTATUS
 
}; 
 
__IM uint16_t HWVERS
 
uint8_t RESERVED2 [10]
 
__IM uint8_t EPINFO
 
__IM uint8_t RAMINFO
 
__IOM uint8_t LINKINFO
 
__IOM uint8_t VPLEN
 
__IOM uint8_t HS_EOF1
 
__IOM uint8_t FS_EOF1
 
__IOM uint8_t LS_EOF1
 
__IOM uint8_t SOFT_RST
 

Field Documentation

◆ CONFIGDATA

__IOM uint8_t CONFIGDATA

Configuration information, Address offset: 0x01F

◆ COUNT0

__IM uint16_t COUNT0

Number of received bytes in Endpoint 0 FIFO, Address offset: 0x018

◆ CSR0H

__IOM uint8_t CSR0H

Control Status High register for Endpoint 0, Address offset: 0x013

◆ CSR0L

__IOM uint8_t CSR0L

Control Status Low register for Endpoint 0, Address offset: 0x012

◆ DEVCTL

__IOM uint8_t DEVCTL

DEVCTL register, Address offset: 0x060

◆ EPINFO

__IM uint8_t EPINFO

EPINFO register, Address offset: 0x078

◆ FADDR

__IOM uint8_t FADDR

Function address register, Address offset: 0x000

◆ FIFO

__IOM uint32_t FIFO[16]

FIFOs for Endpoints 0 to 15, Address offset: 0x020 - 0x05F

◆ FIFOSIZE

__IOM uint8_t FIFOSIZE

FIFO size information, Address offset: 0x01F

◆ FRAME

__IM uint16_t FRAME

Frame number, Address offset: 0x00C

◆ FS_EOF1

__IOM uint8_t FS_EOF1

FS_EOF1 register, Address offset: 0x07D

◆ HS_EOF1

__IOM uint8_t HS_EOF1

HS_EOF1 register, Address offset: 0x07C

◆ HWVERS

__IM uint16_t HWVERS

Hardware Version Number register, Address offset: 0x06C

◆ INDEX

__IOM uint8_t INDEX

Index register, Address offset: 0x00E

◆ INTRRX

__IM uint16_t INTRRX

Interrupt register for RX Endpoints 1 to 15, Address offset: 0x004

◆ INTRRXE

__IOM uint16_t INTRRXE

Interrupt enable register for IntrRx, Address offset: 0x008

◆ INTRTX

__IM uint16_t INTRTX

Interrupt register for Endpoint 0 plus TX Endpoints 1 to 15, Address offset: 0x002

◆ INTRTXE

__IOM uint16_t INTRTXE

Interrupt enable register for IntrTx, Address offset: 0x006

◆ INTRUSB

__IM uint8_t INTRUSB

Interrupt register for common USB interrupts, Address offset: 0x00A

◆ INTRUSBE

__IOM uint8_t INTRUSBE

Interrupt enable register for IntrUSB, Address offset: 0x00B

◆ LINKINFO

__IOM uint8_t LINKINFO

LINKINFO register, Address offset: 0x07A

◆ LS_EOF1

__IOM uint8_t LS_EOF1

LS_EOF1 register, Address offset: 0x07E

◆ MISC

__IOM uint8_t MISC

MISC register, Address offset: 0x061

◆ NAKLIMIT0

__IOM uint8_t NAKLIMIT0

NAKLIMIT0 register (host mode only), Address offset: 0x01B

◆ POWER

__IOM uint8_t POWER

Power management register, Address offset: 0x001

◆ RAMINFO

__IM uint8_t RAMINFO

RAMINFO register, Address offset: 0x079

◆ RESERVED1

uint8_t RESERVED1

Reserved, 0x01E

◆ RESERVED2

uint8_t RESERVED2[10]

Reserved, 0x06E - 0x077

◆ RXCOUNT

__IM uint16_t RXCOUNT

Number of bytes in peripheral RX endpoint FIFO, Address offset: 0x018

◆ RXCSRH

__IOM uint8_t RXCSRH

Control Status High register for peripheral RX endpoint, Address offset: 0x017

◆ RXCSRL

__IOM uint8_t RXCSRL

Control Status Low register for peripheral RX endpoint, Address offset: 0x016

◆ RXFIFOADD

__IOM uint16_t RXFIFOADD

RXFIFOADD register, Address offset: 0x066

◆ RXFIFOSZ

__IOM uint8_t RXFIFOSZ

RXFIFOSZ register, Address offset: 0x063

◆ RXINTERVAL

__IOM uint8_t RXINTERVAL

RXINTERVAL register (host mode only), Address offset: 0x01D

◆ RXMAXP

__IOM uint16_t RXMAXP

Maximum packet size for peripheral RX endpoint, Address offset: 0x014

◆ RXTYPE

__IOM uint8_t RXTYPE

RXTYPE register (host mode only), Address offset: 0x01C

◆ SOFT_RST

__IOM uint8_t SOFT_RST

SOFT_RST register, Address offset: 0x07F

◆ TESTMODE

__IOM uint8_t TESTMODE

Testmode register, Address offset: 0x00F

◆ TXCSRH

__IOM uint8_t TXCSRH

Control Status High register for peripheral TX endpoint, Address offset: 0x013

◆ TXCSRL

__IOM uint8_t TXCSRL

Control Status Low register for peripheral TX endpoint, Address offset: 0x012

◆ TXFIFOADD

__IOM uint16_t TXFIFOADD

TXFIFOADD register, Address offset: 0x064

◆ TXFIFOSZ

__IOM uint8_t TXFIFOSZ

TXFIFOSZ register, Address offset: 0x062

◆ TXINTERVAL

__IOM uint8_t TXINTERVAL

TXINTERVAL register (host mode only), Address offset: 0x01B

◆ TXMAXP

__IOM uint16_t TXMAXP

Maximum packet size for peripheral TX endpoint, Address offset: 0x010

◆ TXTYPE

__IOM uint8_t TXTYPE

Control of the host TX endpoint (host mode only), Address offset: 0x01A

◆ TYPE0

__IOM uint8_t TYPE0

Defines the speed of Endpoint 0 (host mode only), Address offset: 0x01A

◆ VCONTROL

__OM uint32_t VCONTROL

VCONTROL register, Address offset: 0x068

◆ VPLEN

__IOM uint8_t VPLEN

VPLEN register, Address offset: 0x07B

◆ VSTATUS

__IM uint32_t VSTATUS

VSTATUS register, Address offset: 0x068


The documentation for this struct was generated from the following file: