MG32F157 Standard Peripherals Firmware Library
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Modules | |
Library_configuration_section | |
Peripheral_registers_structures | |
Peripheral_memory_map | |
Peripheral_declaration | |
Exported_constants | |
Exported_macro | |
Macros | |
#define | HSI_VALUE (8000000) |
#define | LSI_VALUE (40000) |
#define | __CM3_REV 0x0201U /* Core revision r2p1 */ |
#define | __MPU_PRESENT 0 /* MG32F157 devices does not provide an MPU */ |
#define | __VTOR_PRESENT 1 /* VTOR present or not */ |
#define | __NVIC_PRIO_BITS 4 /* Number of Bits used for Priority Levels */ |
#define | __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ |
#define | IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) |
#define | M8(adr) (*((volatile uint8_t *) (adr))) |
#define | M16(adr) (*((volatile uint16_t *) (adr))) |
#define | M32(adr) (*((volatile uint32_t *) (adr))) |
#define | BIT_BAND_ADDR(addr, bitnum) ((((uint32_t)(addr)) & 0xF0000000) + 0x2000000 + ((((uint32_t)(addr)) & 0xFFFFF) << 5) + ((bitnum) << 2)) |
Typedefs | |
typedef enum IRQn | IRQn_Type |
typedef enum FlagStatus | ITStatus |
Enumerations | |
enum | IRQn { NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, WWDG_IRQn = 0, PVD_IRQn = 1, TAMPER_IRQn = 2, RTC_IRQn = 3, FLASH_IRQn = 4, RCC_IRQn = 5, EXTI0_IRQn = 6, EXTI1_IRQn = 7, EXTI2_IRQn = 8, EXTI3_IRQn = 9, EXTI4_IRQn = 10, DMAC1_Channel1_IRQn = 11, DMAC1_Channel2_IRQn = 12, DMAC1_Channel3_IRQn = 13, DMAC1_Channel4_IRQn = 14, DMAC1_Channel5_IRQn = 15, DMAC1_Channel6_IRQn = 16, DMAC1_Channel7_IRQn = 17, ADC1_2_IRQn = 18, USB_DMA_CAN1_IRQn = 19, USB_IRQn = 20, EXTI9_5_IRQn = 23, TIM1_BRK_IRQn = 24, TIM1_UP_IRQn = 25, TIM1_TRG_COM_IRQn = 26, TIM1_CC_IRQn = 27, TIM2_IRQn = 28, TIM3_IRQn = 29, TIM4_IRQn = 30, I2C1_EV_IRQn = 31, I2C1_ER_IRQn = 32, I2C2_EV_IRQn = 33, I2C2_ER_IRQn = 34, SPI1_IRQn = 35, SPI2_IRQn = 36, USART1_IRQn = 37, USART2_IRQn = 38, USART3_IRQn = 39, EXTI15_10_IRQn = 40, RTCAlarm_IRQn = 41, TIM8_BRK_IRQn = 43, TIM8_UP_IRQn = 44, TIM8_TRG_COM_IRQn = 45, TIM8_CC_IRQn = 46, ADC3_IRQn = 47, SDIO_IRQn = 49, TIM5_IRQn = 50, SPI3_IRQn = 51, UART4_IRQn = 52, UART5_IRQn = 53, TIM6_IRQn = 54, TIM7_IRQn = 55, DMAC2_Channel1_IRQn = 56, DMAC2_Channel2_IRQn = 57, DMAC2_Channel3_IRQn = 58, DMAC2_Channel4_5_IRQn = 59, QUADSPI_IRQn = 60, RNG_IRQn = 61, AES_IRQn = 62, USART_EXTI_IRQn = 63 } |
enum | FlagStatus { RESET = 0, SET = !RESET } |
enum | FunctionalState { DISABLE = 0, ENABLE = !DISABLE } |
enum | SignalState { INACTIVE = 0, ACTIVE = !INACTIVE } |
enum | ErrorStatus { ERROR = 0, SUCCESS = !ERROR } |
#define HSI_VALUE (8000000) |
Value of the Internal 8M oscillator in Hz
#define LSI_VALUE (40000) |
Value of the Internal 40K oscillator in Hz
enum IRQn |