◆ CR
DAC control register, Address offset: 0x000
◆ DHR12L1
DAC channel1 12-bit left aligned data holding register, Address offset: 0x00C
◆ DHR12L2
DAC channel2 12-bit left aligned data holding register, Address offset: 0x018
◆ DHR12LD
DUAL DAC 12-bit left aligned data holding register, Address offset: 0x024
◆ DHR12R1
DAC channel1 12-bit right-aligned data holding register, Address offset: 0x008
◆ DHR12R2
DAC channel2 12-bit right aligned data holding register, Address offset: 0x014
◆ DHR12RD
DUAL DAC 12-bit right-aligned data holding register, Address offset: 0x020
◆ DHR8R1
DAC channel1 8-bit right aligned data holding register, Address offset: 0x010
◆ DHR8R2
DAC channel2 8-bit right-aligned data holding register, Address offset: 0x01C
◆ DHR8RD
DUAL DAC 8-bit right aligned data holding register, Address offset: 0x028
◆ DOR1
DAC channel1 data output register, Address offset: 0x02C
◆ DOR2
DAC channel2 data output register, Address offset: 0x030
◆ SWTRIGR
DAC software trigger register, Address offset: 0x004
The documentation for this struct was generated from the following file: