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#define | DMAC_HardwareHandshakingInterface_ADC1__TIM2_CH3__TIM4_CH1__QSPI0__AES_RX 0 |
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#define | DMAC_HardwareHandshakingInterface_USART3_TX__TIM1_CH1__TIM2_UP__TIM3_CH3__SPI1_RX__AES_TX 1 |
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#define | DMAC_HardwareHandshakingInterface_USART3_RX__TIM1_CH2__TIM3_CH4__TIM3_UP__SPI1_TX 2 |
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#define | DMAC_HardwareHandshakingInterface_USART1_TX__TIM1_CH4__TIM1_TRIG__TIM1_COM__TIM4_CH2__SPI2_RX__I2C2_TX 3 |
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#define | DMAC_HardwareHandshakingInterface_USART1_RX__TIM1_UP__SPI2_TX__TIM2_CH1__TIM4_CH3__I2C2_RX 4 |
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#define | DMAC_HardwareHandshakingInterface_USART2_RX__TIM1_CH3__TIM3_CH1__TIM3_TRIG__I2C1_TX 5 |
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#define | DMAC_HardwareHandshakingInterface_USART2_TX__TIM2_CH2__TIM2_CH4__TIM4_UP_I2C1_RX 6 |
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#define | DMAC_HardwareHandshakingInterface_TIM5_CH4__TIM5_TRIG__TIM8_CH3__TIM8_UP__SPI3_RX 0 |
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#define | DMAC_HardwareHandshakingInterface_TIM8_CH4__TIM8_TRIG__TIM8_COM__TIM5_CH3__TIM5_UP__SPI3_TX 1 |
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#define | DMAC_HardwareHandshakingInterface_TIM8_CH1__UART4_RX__TIM6_UP__DAC1 2 |
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#define | DMAC_HardwareHandshakingInterface_TIM5_CH2__SDIO__TIM7_UP__DAC2 3 |
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#define | DMAC_HardwareHandshakingInterface_ADC3__TIM8_CH2__TIM5_CH1__UART4_TX 4 |
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