◆ CONFIGDATA
Configuration information, Address offset: 0x01F
◆ COUNT0
Number of received bytes in Endpoint 0 FIFO, Address offset: 0x018
◆ CSR0H
Control Status High register for Endpoint 0, Address offset: 0x013
◆ CSR0L
Control Status Low register for Endpoint 0, Address offset: 0x012
◆ DEVCTL
DEVCTL register, Address offset: 0x060
◆ EPINFO
EPINFO register, Address offset: 0x078
◆ FADDR
Function address register, Address offset: 0x000
◆ FIFO
FIFOs for Endpoints 0 to 15, Address offset: 0x020 - 0x05F
◆ FIFOSIZE
FIFO size information, Address offset: 0x01F
◆ FRAME
Frame number, Address offset: 0x00C
◆ FS_EOF1
FS_EOF1 register, Address offset: 0x07D
◆ HS_EOF1
HS_EOF1 register, Address offset: 0x07C
◆ HWVERS
Hardware Version Number register, Address offset: 0x06C
◆ INDEX
Index register, Address offset: 0x00E
◆ INTRRX
Interrupt register for RX Endpoints 1 to 15, Address offset: 0x004
◆ INTRRXE
Interrupt enable register for IntrRx, Address offset: 0x008
◆ INTRTX
Interrupt register for Endpoint 0 plus TX Endpoints 1 to 15, Address offset: 0x002
◆ INTRTXE
Interrupt enable register for IntrTx, Address offset: 0x006
◆ INTRUSB
Interrupt register for common USB interrupts, Address offset: 0x00A
◆ INTRUSBE
Interrupt enable register for IntrUSB, Address offset: 0x00B
◆ LINKINFO
LINKINFO register, Address offset: 0x07A
◆ LS_EOF1
LS_EOF1 register, Address offset: 0x07E
◆ MISC
MISC register, Address offset: 0x061
◆ NAKLIMIT0
NAKLIMIT0 register (host mode only), Address offset: 0x01B
◆ POWER
Power management register, Address offset: 0x001
◆ RAMINFO
RAMINFO register, Address offset: 0x079
◆ RESERVED1
◆ RESERVED2
◆ RXCOUNT
Number of bytes in peripheral RX endpoint FIFO, Address offset: 0x018
◆ RXCSRH
Control Status High register for peripheral RX endpoint, Address offset: 0x017
◆ RXCSRL
Control Status Low register for peripheral RX endpoint, Address offset: 0x016
◆ RXFIFOADD
RXFIFOADD register, Address offset: 0x066
◆ RXFIFOSZ
RXFIFOSZ register, Address offset: 0x063
◆ RXINTERVAL
RXINTERVAL register (host mode only), Address offset: 0x01D
◆ RXMAXP
Maximum packet size for peripheral RX endpoint, Address offset: 0x014
◆ RXTYPE
RXTYPE register (host mode only), Address offset: 0x01C
◆ SOFT_RST
SOFT_RST register, Address offset: 0x07F
◆ TESTMODE
Testmode register, Address offset: 0x00F
◆ TXCSRH
Control Status High register for peripheral TX endpoint, Address offset: 0x013
◆ TXCSRL
Control Status Low register for peripheral TX endpoint, Address offset: 0x012
◆ TXFIFOADD
TXFIFOADD register, Address offset: 0x064
◆ TXFIFOSZ
TXFIFOSZ register, Address offset: 0x062
◆ TXINTERVAL
TXINTERVAL register (host mode only), Address offset: 0x01B
◆ TXMAXP
Maximum packet size for peripheral TX endpoint, Address offset: 0x010
◆ TXTYPE
Control of the host TX endpoint (host mode only), Address offset: 0x01A
◆ TYPE0
Defines the speed of Endpoint 0 (host mode only), Address offset: 0x01A
◆ VCONTROL
VCONTROL register, Address offset: 0x068
◆ VPLEN
VPLEN register, Address offset: 0x07B
◆ VSTATUS
VSTATUS register, Address offset: 0x068
The documentation for this struct was generated from the following file: