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struct { |
__IOM uint32_t SAR |
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uint32_t Undefined_SAR |
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__IOM uint32_t DAR |
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uint32_t Undefined_DAR |
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__IOM uint32_t LLP |
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uint32_t Undefined_LLP |
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__IOM uint32_t CTLL |
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__IOM uint32_t CTLH |
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__IOM uint32_t SSTAT |
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uint32_t Undefined_SSTAT |
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__IOM uint32_t DSTAT |
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uint32_t Undefined_DSTAT |
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__IOM uint32_t SSTATAR |
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uint32_t Undefined_SSTATAR |
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__IOM uint32_t DSTATAR |
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uint32_t Undefined_DSTATAR |
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__IOM uint32_t CFGL |
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__IOM uint32_t CFGH |
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uint32_t RESERVED0 [4] |
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} | Ch [7] |
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uint32_t | RESERVED1 [22] |
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__IM uint32_t | RawTfr |
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uint32_t | Undefined_RawTfr |
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__IM uint32_t | RawBlock |
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uint32_t | Undefined_RawBlock |
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__IM uint32_t | RawSrcTran |
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uint32_t | Undefined_RawSrcTran |
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__IM uint32_t | RawDstTran |
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uint32_t | Undefined_RawDstTran |
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__IM uint32_t | RawErr |
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uint32_t | Undefined_RawErr |
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__IM uint32_t | StatusTfr |
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uint32_t | Undefined_StatusTfr |
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__IM uint32_t | StatusBlock |
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uint32_t | Undefined_StatusBlock |
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__IM uint32_t | StatusSrcTran |
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uint32_t | Undefined_StatusSrcTran |
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__IM uint32_t | StatusDstTran |
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uint32_t | Undefined_StatusDstTran |
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__IM uint32_t | StatusErr |
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uint32_t | Undefined_StatusErr |
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__IOM uint32_t | MaskTfr |
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uint32_t | Undefined_MaskTfr |
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__IOM uint32_t | MaskBlock |
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uint32_t | Undefined_MaskBlock |
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__IOM uint32_t | MaskSrcTran |
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uint32_t | Undefined_MaskSrcTran |
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__IOM uint32_t | MaskDstTran |
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uint32_t | Undefined_MaskDstTran |
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__IOM uint32_t | MaskErr |
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uint32_t | Undefined_MaskErr |
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__OM uint32_t | ClearTfr |
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uint32_t | Undefined_ClearTfr |
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__OM uint32_t | ClearBlock |
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uint32_t | Undefined_ClearBlock |
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__OM uint32_t | ClearSrcTran |
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uint32_t | Undefined_ClearSrcTran |
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__OM uint32_t | ClearDstTran |
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uint32_t | Undefined_ClearDstTran |
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__OM uint32_t | ClearErr |
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uint32_t | Undefined_ClearErr |
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__IM uint32_t | StatusInt |
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uint32_t | Undefined_StatusInt |
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__IOM uint32_t | ReqSrcReg |
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uint32_t | Undefined_ReqSrcReg |
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__IOM uint32_t | ReqDstReg |
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uint32_t | Undefined_ReqDstReg |
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__IOM uint32_t | SglReqSrcReg |
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uint32_t | Undefined_SglReqSrcReg |
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__IOM uint32_t | SglReqDstReg |
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uint32_t | Undefined_SglReqDstReg |
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__IOM uint32_t | LstSrcReg |
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uint32_t | Undefined_LstSrcReg |
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__IOM uint32_t | LstDstReg |
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uint32_t | Undefined_LstDstReg |
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__IOM uint32_t | DmaCfgReg |
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uint32_t | Undefined_DmaCfgReg |
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__IOM uint32_t | ChEnReg |
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uint32_t | Undefined_ChEnReg |
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◆ CFGH
Channel x Configuration High Register, Address offset: 0x044, 0x09C, 0x0F4, 0x14C, 0x1A4, 0x1FC, 0x254
◆ CFGL
Channel x Configuration Low Register, Address offset: 0x040, 0x098, 0x0F0, 0x148, 0x1A0, 0x1F8, 0x250
◆ ChEnReg
DMA Channel Enable Register, Address offset: 0x3A0
◆ ClearBlock
Clear for IntBlock Interrupt, Address offset: 0x340
◆ ClearDstTran
__OM uint32_t ClearDstTran |
Clear for IntDstTran Interrupt, Address offset: 0x350
◆ ClearErr
Clear for IntErr Interrupt, Address offset: 0x358
◆ ClearSrcTran
__OM uint32_t ClearSrcTran |
Clear for IntSrcTran Interrupt, Address offset: 0x348
◆ ClearTfr
Clear for IntTfr Interrupt, Address offset: 0x338
◆ CTLH
Channel x Control High Register, Address offset: 0x01C, 0x074, 0x0CC, 0x124, 0x17C, 0x1D4, 0x22C
◆ CTLL
Channel x Control Low Register, Address offset: 0x018, 0x070, 0x0C8, 0x120, 0x178, 0x1D0, 0x228
◆ DAR
Channel x Destination Address Register, Address offset: 0x008, 0x060, 0x0B8, 0x110, 0x168, 0x1C0, 0x218
◆ DmaCfgReg
DMA Configuration Register, Address offset: 0x398
◆ DSTAT
Channel x Destination Status Register, Address offset: 0x028, 0x080, 0x0D8, 0x130, 0x188, 0x1E0, 0x238
◆ DSTATAR
Channel x Destination Status Address Register, Address offset: 0x038, 0x090, 0x0E8, 0x140, 0x198, 0x1F0, 0x248
◆ LLP
Channel x Linked List Pointer Register, Address offset: 0x010, 0x068, 0x0CO, 0x118, 0x170, 0x1C8, 0x220
◆ LstDstReg
Last Destination Transaction Request Register, Address offset: 0x390
◆ LstSrcReg
Last Source Transaction Request Register, Address offset: 0x388
◆ MaskBlock
Mask for IntBlock Interrupt, Address offset: 0x318
◆ MaskDstTran
__IOM uint32_t MaskDstTran |
Mask for IntDstTran Interrupt, Address offset: 0x328
◆ MaskErr
Mask for IntErr Interrupt, Address offset: 0x330
◆ MaskSrcTran
__IOM uint32_t MaskSrcTran |
Mask for IntSrcTran Interrupt, Address offset: 0x320
◆ MaskTfr
Mask for IntTfr Interrupt, Address offset: 0x310
◆ RawBlock
Raw Status for IntBlock Interrupt, Address offset: 0x2C8
◆ RawDstTran
Raw Status for IntDstTran Interrupt, Address offset: 0x2D8
◆ RawErr
Raw Status for IntErr Interrupt, Address offset: 0x2E0
◆ RawSrcTran
Raw Status for IntSrcTran Interrupt, Address offset: 0x2D0
◆ RawTfr
Raw Status for IntTfr Interrupt, Address offset: 0x2C0
◆ ReqDstReg
Destination Software Transaction Request Register, Address offset: 0x370
◆ ReqSrcReg
Source Software Transaction Request Register, Address offset: 0x368
◆ RESERVED0
◆ RESERVED1
◆ SAR
Channel x Source Address Register, Address offset: 0x000, 0x058, 0x0B0, 0x108, 0x160, 0x1B8, 0x210
◆ SglReqDstReg
__IOM uint32_t SglReqDstReg |
Single Destination Transaction Request Register, Address offset: 0x380
◆ SglReqSrcReg
__IOM uint32_t SglReqSrcReg |
Single Source Transaction Request Register, Address offset: 0x378
◆ SSTAT
Channel x Source Status Register, Address offset: 0x020, 0x078, 0x0D0, 0x128, 0x180, 0x1D8, 0x230
◆ SSTATAR
Channel x Source Status Address Register, Address offset: 0x030, 0x088, 0x0E0, 0x138, 0x190, 0x1E8, 0x240
◆ StatusBlock
__IM uint32_t StatusBlock |
Status for IntBlock Interrupt, Address offset: 0x2F0
◆ StatusDstTran
__IM uint32_t StatusDstTran |
Status for IntDstTran Interrupt, Address offset: 0x300
◆ StatusErr
Status for IntErr Interrupt, Address offset: 0x308
◆ StatusInt
Status for each interrupt type, Address offset: 0x360
◆ StatusSrcTran
__IM uint32_t StatusSrcTran |
Status for IntSrcTran Interrupt, Address offset: 0x2F8
◆ StatusTfr
Status for IntTfr Interrupt, Address offset: 0x2E8
The documentation for this struct was generated from the following file: