◆ AHBENR
AHB Peripheral Clock enable register, Address offset: 0x014
◆ APB1ENR
APB1 peripheral clock enable register, Address offset: 0x01C
◆ APB1RSTR
APB1 peripheral reset register, Address offset: 0x010
◆ APB2ENR
APB2 peripheral clock enable register, Address offset: 0x018
◆ APB2RSTR
APB2 peripheral reset register, Address offset: 0x00C
◆ BDCR
Backup domain control register, Address offset: 0x020
◆ CFGR
Clock configuration register, Address offset: 0x004
◆ CIR
Clock interrupt register, Address offset: 0x008
◆ CR
Clock control register, Address offset: 0x000
◆ CSR
Control/status register, Address offset: 0x024
The documentation for this struct was generated from the following file: