11 #ifndef __MG32F157_RCC_H 12 #define __MG32F157_RCC_H 49 #define RCC_HSE_OFF ((uint32_t)0x00000000) 50 #define RCC_HSE_ON ((uint32_t)0x00010000) 51 #define RCC_HSE_Bypass ((uint32_t)0x00040000) 52 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ 53 ((HSE) == RCC_HSE_Bypass)) 62 #define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) 63 #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) 64 #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) 65 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ 66 ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ 67 ((SOURCE) == RCC_PLLSource_HSE_Div2)) 76 #define RCC_PLLMul_2 ((uint32_t)0x00000000) 77 #define RCC_PLLMul_3 ((uint32_t)0x00040000) 78 #define RCC_PLLMul_4 ((uint32_t)0x00080000) 79 #define RCC_PLLMul_5 ((uint32_t)0x000C0000) 80 #define RCC_PLLMul_6 ((uint32_t)0x00100000) 81 #define RCC_PLLMul_7 ((uint32_t)0x00140000) 82 #define RCC_PLLMul_8 ((uint32_t)0x00180000) 83 #define RCC_PLLMul_9 ((uint32_t)0x001C0000) 84 #define RCC_PLLMul_10 ((uint32_t)0x00200000) 85 #define RCC_PLLMul_11 ((uint32_t)0x00240000) 86 #define RCC_PLLMul_12 ((uint32_t)0x00280000) 87 #define RCC_PLLMul_13 ((uint32_t)0x002C0000) 88 #define RCC_PLLMul_14 ((uint32_t)0x00300000) 89 #define RCC_PLLMul_15 ((uint32_t)0x00340000) 90 #define RCC_PLLMul_16 ((uint32_t)0x00380000) 91 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ 92 ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ 93 ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ 94 ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ 95 ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ 96 ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ 97 ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ 98 ((MUL) == RCC_PLLMul_16)) 107 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) 108 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) 109 #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) 110 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ 111 ((SOURCE) == RCC_SYSCLKSource_HSE) || \ 112 ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) 121 #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) 122 #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) 123 #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) 124 #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) 125 #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) 126 #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) 127 #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) 128 #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) 129 #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) 130 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ 131 ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ 132 ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ 133 ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ 134 ((HCLK) == RCC_SYSCLK_Div512)) 143 #define RCC_HCLK_Div1 ((uint32_t)0x00000000) 144 #define RCC_HCLK_Div2 ((uint32_t)0x00000400) 145 #define RCC_HCLK_Div4 ((uint32_t)0x00000500) 146 #define RCC_HCLK_Div8 ((uint32_t)0x00000600) 147 #define RCC_HCLK_Div16 ((uint32_t)0x00000700) 148 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ 149 ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ 150 ((PCLK) == RCC_HCLK_Div16)) 159 #define RCC_IT_LSIRDY ((uint8_t)0x01) 160 #define RCC_IT_LSERDY ((uint8_t)0x02) 161 #define RCC_IT_HSIRDY ((uint8_t)0x04) 162 #define RCC_IT_HSERDY ((uint8_t)0x08) 163 #define RCC_IT_PLLRDY ((uint8_t)0x10) 164 #define RCC_IT_CSS ((uint8_t)0x80) 166 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) 167 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ 168 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ 169 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) 170 #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) 179 #define RCC_USBCLKSource_PLLCLK_Div2 ((uint8_t)0x00) 180 #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) 182 #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_Div2) || \ 183 ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) 192 #define RCC_PCLK2_Div2 ((uint32_t)0x00000000) 193 #define RCC_PCLK2_Div4 ((uint32_t)0x00004000) 194 #define RCC_PCLK2_Div6 ((uint32_t)0x00008000) 195 #define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) 196 #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ 197 ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) 206 #define RCC_LSE_OFF ((uint8_t)0x00) 207 #define RCC_LSE_ON ((uint8_t)0x01) 208 #define RCC_LSE_Bypass ((uint8_t)0x04) 209 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ 210 ((LSE) == RCC_LSE_Bypass)) 219 #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) 220 #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) 221 #define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) 222 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ 223 ((SOURCE) == RCC_RTCCLKSource_LSI) || \ 224 ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) 233 #define RCC_AHBPeriph_DMAC1 ((uint32_t)0x00000001) 234 #define RCC_AHBPeriph_DMAC2 ((uint32_t)0x00000002) 235 #define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) 236 #define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) 237 #define RCC_AHBPeriph_RNG ((uint32_t)0x00000020) 238 #define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) 239 #define RCC_AHBPeriph_AES ((uint32_t)0x00000080) 240 #define RCC_AHBPeriph_QUADSPI ((uint32_t)0x00000100) 241 #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) 242 #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFA08) == 0x00) && ((PERIPH) != 0x00)) 251 #define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) 252 #define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) 253 #define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) 254 #define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) 255 #define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) 256 #define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) 257 #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) 258 #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) 259 #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) 260 #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) 261 #define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) 262 #define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) 263 #define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) 265 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFF0182) == 0x00) && ((PERIPH) != 0x00)) 274 #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) 275 #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) 276 #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) 277 #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) 278 #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) 279 #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) 280 #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) 281 #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) 282 #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) 283 #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) 284 #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) 285 #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) 286 #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) 287 #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) 288 #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) 289 #define RCC_APB1Periph_USB ((uint32_t)0x00800000) 290 #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) 291 #define RCC_APB1Periph_BKP ((uint32_t)0x08000000) 292 #define RCC_APB1Periph_PWR ((uint32_t)0x10000000) 293 #define RCC_APB1Periph_DAC ((uint32_t)0x20000000) 295 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC50137C0) == 0x00) && ((PERIPH) != 0x00)) 304 #define RCC_MCO_NoClock ((uint8_t)0x00) 305 #define RCC_MCO_SYSCLK ((uint8_t)0x04) 306 #define RCC_MCO_HSI ((uint8_t)0x05) 307 #define RCC_MCO_HSE ((uint8_t)0x06) 308 #define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) 310 #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ 311 ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ 312 ((MCO) == RCC_MCO_PLLCLK_Div2)) 321 #define RCC_FLAG_HSIRDY ((uint8_t)0x21) 322 #define RCC_FLAG_HSERDY ((uint8_t)0x31) 323 #define RCC_FLAG_PLLRDY ((uint8_t)0x39) 324 #define RCC_FLAG_LSERDY ((uint8_t)0x41) 325 #define RCC_FLAG_LSIRDY ((uint8_t)0x61) 326 #define RCC_FLAG_PINRST ((uint8_t)0x7A) 327 #define RCC_FLAG_PORRST ((uint8_t)0x7B) 328 #define RCC_FLAG_SFTRST ((uint8_t)0x7C) 329 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) 330 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) 331 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) 333 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ 334 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ 335 ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ 336 ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ 337 ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ 338 ((FLAG) == RCC_FLAG_LPWRRST)) 341 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) 358 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
366 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
void RCC_ClearFlag(void)
Clears the RCC reset flags.
Definition: mg32f157_rcc.c:962
void RCC_PCLK1Config(uint32_t RCC_HCLK)
Configures the Low Speed APB clock (PCLK1).
Definition: mg32f157_rcc.c:390
ITStatus RCC_GetITStatus(uint8_t RCC_IT)
Checks whether the specified RCC interrupt has occurred or not.
Definition: mg32f157_rcc.c:980
void RCC_ClearITPendingBit(uint8_t RCC_IT)
Clears the RCC's interrupt pending bits.
Definition: mg32f157_rcc.c:1012
void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
Enables or disables the Clock Security System.
Definition: mg32f157_rcc.c:873
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the High Speed APB (APB2) peripheral clock.
Definition: mg32f157_rcc.c:717
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
Checks whether the specified RCC flag is set or not.
Definition: mg32f157_rcc.c:917
void RCC_DeInit(void)
Resets the RCC clock configuration to the default reset state.
Definition: mg32f157_rcc.c:146
void RCC_HSICmd(FunctionalState NewState)
Enables or disables the Internal High Speed oscillator (HSI).
Definition: mg32f157_rcc.c:261
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
Configures the RTC clock (RTCCLK).
Definition: mg32f157_rcc.c:559
void RCC_LSICmd(FunctionalState NewState)
Enables or disables the Internal Low Speed oscillator (LSI).
Definition: mg32f157_rcc.c:542
uint32_t HCLK_Frequency
Definition: mg32f157_rcc.h:34
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
Enables or disables the specified RCC interrupts.
Definition: mg32f157_rcc.c:443
void RCC_PCLK2Config(uint32_t RCC_HCLK)
Configures the High Speed APB clock (PCLK2).
Definition: mg32f157_rcc.c:416
void RCC_RTCCLKCmd(FunctionalState NewState)
Enables or disables the RTC clock.
Definition: mg32f157_rcc.c:573
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
Adjusts the Internal High Speed oscillator (HSI) calibration value.
Definition: mg32f157_rcc.c:241
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
Enables or disables the AHB peripheral clock.
Definition: mg32f157_rcc.c:680
void RCC_HSEConfig(uint32_t RCC_HSE)
Configures the External High Speed oscillator (HSE).
Definition: mg32f157_rcc.c:177
uint32_t ADCCLK_Frequency
Definition: mg32f157_rcc.h:37
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
Configures the PLL clock source and multiplication factor.
Definition: mg32f157_rcc.c:280
void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
Configures the USB clock (USBCLK).
Definition: mg32f157_rcc.c:470
ErrorStatus RCC_WaitForHSEStartUp(void)
Waits for HSE start-up.
Definition: mg32f157_rcc.c:211
uint32_t SYSCLK_Frequency
Definition: mg32f157_rcc.h:33
void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
Configures the AHB clock (HCLK).
Definition: mg32f157_rcc.c:364
uint8_t RCC_GetSYSCLKSource(void)
Returns the clock source used as system clock.
Definition: mg32f157_rcc.c:343
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the Low Speed APB (APB1) peripheral clock.
Definition: mg32f157_rcc.c:760
void RCC_MCOConfig(uint8_t RCC_MCO)
Selects the clock source to output on MCO pin.
Definition: mg32f157_rcc.c:891
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
Definition: mg32f157_rcc.c:839
void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
Configures the ADC clock (ADCCLK).
Definition: mg32f157_rcc.c:489
uint32_t PCLK2_Frequency
Definition: mg32f157_rcc.h:36
uint32_t PCLK1_Frequency
Definition: mg32f157_rcc.h:35
void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks)
Returns the frequencies of different on chip clocks.
Definition: mg32f157_rcc.c:588
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Forces or releases High Speed APB (APB2) peripheral reset.
Definition: mg32f157_rcc.c:796
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
Configures the system clock (SYSCLK).
Definition: mg32f157_rcc.c:320
void RCC_LSEConfig(uint8_t RCC_LSE)
Configures the External Low Speed oscillator (LSE).
Definition: mg32f157_rcc.c:512
Definition: mg32f157_rcc.h:31
void RCC_BackupResetCmd(FunctionalState NewState)
Forces or releases the Backup domain reset.
Definition: mg32f157_rcc.c:860
void RCC_PLLCmd(FunctionalState NewState)
Enables or disables the PLL.
Definition: mg32f157_rcc.c:303