MG32F157 Standard Peripherals Firmware Library
Data Fields
SDIO_TypeDef Struct Reference

Data Fields

__IO uint32_t CTRL
 
__IO uint32_t PWREN
 
__IO uint32_t CLKDIV
 
__IO uint32_t RESERVED0
 
__IO uint32_t CLKENA
 
__IO uint32_t TMOUT
 
__IO uint32_t CTYPE
 
__IO uint32_t BLKSIZ
 
__IO uint32_t BYTCNT
 
__IO uint32_t INTMASK
 
__IO uint32_t CMDARG
 
__IO uint32_t CMD
 
__IO uint32_t RESP0
 
__IO uint32_t RESP1
 
__IO uint32_t RESP2
 
__IO uint32_t RESP3
 
__IO uint32_t MINTSTS
 
__IO uint32_t RINTSTS
 
__IO uint32_t STATUS
 
__IO uint32_t FIFOTH
 
__IO uint32_t CDETECT
 
__IO uint32_t WRTPRT
 
__IO uint32_t RESERVED1
 
__IO uint32_t TCBCNT
 
__IO uint32_t TBBCNT
 
__IO uint32_t RESERVED2 [7]
 
__IO uint32_t BMOD
 
__IO uint32_t PLDMND
 
__IO uint32_t DBADDR
 
__IO uint32_t IDSTS
 
__IO uint32_t IDINTEN
 
__IO uint32_t DSCADDR
 
__IO uint32_t BUFADDR
 
__IO uint32_t RESERVED3 [25]
 
__IO uint32_t CARDTHRCTL
 
__IO uint32_t BACK_END_POWER
 
__IO uint32_t UHS_REG_EXT
 
__IO uint32_t EMMC_DDR_REG
 
__IO uint32_t ENABLE_SHIFT
 
uint32_t RESERVED4 [59]
 
__IO uint32_t FIFO
 

Field Documentation

◆ BACK_END_POWER

__IO uint32_t BACK_END_POWER

Back end power register, Address offset: 0x104

◆ BLKSIZ

__IO uint32_t BLKSIZ

Block sizeregister, Address offset: 0x1C

◆ BMOD

__IO uint32_t BMOD

Bus mode register, Address offset: 0x80

◆ BUFADDR

__IO uint32_t BUFADDR

Current host buffer register, Address offset: 0x98

◆ BYTCNT

__IO uint32_t BYTCNT

Byte count register, Address offset: 0x20

◆ CARDTHRCTL

__IO uint32_t CARDTHRCTL

Card read threshold enable register, Address offset: 0x100

◆ CDETECT

__IO uint32_t CDETECT

Card detect register, Address offset: 0x50

◆ CLKDIV

__IO uint32_t CLKDIV

Clock divider register, Address offset: 0x08

◆ CLKENA

__IO uint32_t CLKENA

Clock enable register, Address offset: 0x10

◆ CMD

__IO uint32_t CMD

Command register, Address offset: 0x2C

◆ CMDARG

__IO uint32_t CMDARG

Command argument register, Address offset: 0x28

◆ CTRL

__IO uint32_t CTRL

Control register, Address offset: 0x00

◆ CTYPE

__IO uint32_t CTYPE

Card type register, Address offset: 0x18

◆ DBADDR

__IO uint32_t DBADDR

Descriptor list base address register, Address offset: 0x88

◆ DSCADDR

__IO uint32_t DSCADDR

Current host descriptor address register, Address offset: 0x94

◆ EMMC_DDR_REG

__IO uint32_t EMMC_DDR_REG

Emmc DDR START bit dection register, Address offset: 0x10C

◆ ENABLE_SHIFT

__IO uint32_t ENABLE_SHIFT

Phase shift control register, Address offset: 0x110

◆ FIFO

__IO uint32_t FIFO

SDIO data FIFO register, Address offset: 0x200

◆ FIFOTH

__IO uint32_t FIFOTH

FIFO threshold register, Address offset: 0x4C

◆ IDINTEN

__IO uint32_t IDINTEN

Internal DMAC interrupt enable register, Address offset: 0x90

◆ IDSTS

__IO uint32_t IDSTS

Internal DMAC status register, Address offset: 0x8C

◆ INTMASK

__IO uint32_t INTMASK

Interrupt mask register, Address offset: 0x24

◆ MINTSTS

__IO uint32_t MINTSTS

Masked interrupt status register, Address offset: 0x40

◆ PLDMND

__IO uint32_t PLDMND

Poll memand register, Address offset: 0x84

◆ PWREN

__IO uint32_t PWREN

Power enable register, Address offset: 0x04

◆ RESERVED0

__IO uint32_t RESERVED0

Reserved

◆ RESERVED1

__IO uint32_t RESERVED1

Reserved

◆ RESERVED2

__IO uint32_t RESERVED2[7]

Reserved

◆ RESERVED3

__IO uint32_t RESERVED3[25]

Reserved

◆ RESERVED4

uint32_t RESERVED4[59]

Reserved

◆ RESP0

__IO uint32_t RESP0

Response 0 register, Address offset: 0x30

◆ RESP1

__IO uint32_t RESP1

Response 1 register, Address offset: 0x34

◆ RESP2

__IO uint32_t RESP2

Response 2 register, Address offset: 0x38

◆ RESP3

__IO uint32_t RESP3

Response 3 register, Address offset: 0x3C

◆ RINTSTS

__IO uint32_t RINTSTS

Raw interrupt status register, Address offset: 0x44

◆ STATUS

__IO uint32_t STATUS

Status register, Address offset: 0x48

◆ TBBCNT

__IO uint32_t TBBCNT

Transferred host/DMA to/from BIU-FIFO byte count register, Address offset: 0x60

◆ TCBCNT

__IO uint32_t TCBCNT

Transferred CIU card byte count register, Address offset: 0x5C

◆ TMOUT

__IO uint32_t TMOUT

Time out register, Address offset: 0x14

◆ UHS_REG_EXT

__IO uint32_t UHS_REG_EXT

Emmc 4.5 1.2V register, Address offset: 0x108

◆ WRTPRT

__IO uint32_t WRTPRT

Write protect register, Address offset: 0x54


The documentation for this struct was generated from the following file: