MG32F157 Standard Peripherals Firmware Library
mg32f157.h
1 /******************************************************************************
2  * @file mg32f157.h
3  * @brief CMSIS Core Peripheral Access Layer Header File for
4  * mg32f157 Device Series
5  * @version V0.0.4
6  * @date 16-June-2023
7  * @attention
8  *
9  * Copyright (c) 2023 Megawin Technology (Shenzhen) Corp., Ltd
10  * All rights reserved.
11  *
12  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14  * TIME. AS A RESULT, MEGAWIN TECHNOLOGY SHALL NOT BE HELD LIABLE FOR ANY
15  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18  *
19  ******************************************************************************/
20 
29 #ifndef __MG32F157_H__
30 #define __MG32F157_H__
31 
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35 
40 #if !defined USE_STDPERIPH_DRIVER
41 
46  /*#define USE_STDPERIPH_DRIVER*/
47 #endif
48 
49 
57 #if !defined HSE_VALUE
58  #define HSE_VALUE (8000000)
59 #endif /* HSE_VALUE */
60 
61 
66 #define HSE_STARTUP_TIMEOUT (0x1000)
72 #define __MG32F157_STDPERIPH_VERSION_MAIN (0x00)
73 #define __MG32F157_STDPERIPH_VERSION_SUB1 (0x00)
74 #define __MG32F157_STDPERIPH_VERSION_SUB2 (0x00)
75 #define __MG32F157_STDPERIPH_VERSION_RC (0x00)
76 #define __MG32F157_STDPERIPH_VERSION ( (__MG32F157_STDPERIPH_VERSION_MAIN << 24)\
77  |(__MG32F157_STDPERIPH_VERSION_SUB1 << 16)\
78  |(__MG32F157_STDPERIPH_VERSION_SUB2 << 8)\
79  |(__MG32F157_STDPERIPH_VERSION_RC))
80 
85 #define HSI_VALUE (8000000)
86 #define LSI_VALUE (40000)
88 /* ------------------------- Interrupt Number Definition ------------------------ */
89 
90 typedef enum IRQn
91 {
92 /* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
93  NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
94  HardFault_IRQn = -13, /* 3 HardFault Interrupt */
95  MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
96  BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
97  UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
98  SVCall_IRQn = -5, /* 11 SV Call Interrupt */
99  DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
100  PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
101  SysTick_IRQn = -1, /* 15 System Tick Interrupt */
102 
103 /* ---------------------- MG32F157 Specific Interrupt Numbers --------------------- */
104  WWDG_IRQn = 0,
105  PVD_IRQn = 1,
107  RTC_IRQn = 3,
109  RCC_IRQn = 5,
114  EXTI4_IRQn = 10,
122  ADC1_2_IRQn = 18,
124  USB_IRQn = 20,
130  TIM2_IRQn = 28,
131  TIM3_IRQn = 29,
132  TIM4_IRQn = 30,
137  SPI1_IRQn = 35,
138  SPI2_IRQn = 36,
139  USART1_IRQn = 37,
140  USART2_IRQn = 38,
141  USART3_IRQn = 39,
148  ADC3_IRQn = 47,
149  SDIO_IRQn = 49,
150  TIM5_IRQn = 50,
151  SPI3_IRQn = 51,
152  UART4_IRQn = 52,
153  UART5_IRQn = 53,
154  TIM6_IRQn = 54,
155  TIM7_IRQn = 55,
161  RNG_IRQn = 61,
162  AES_IRQn = 62,
164 } IRQn_Type;
165 
166 
167 /* ================================================================================ */
168 /* ================ Processor and Core Peripheral Section ================ */
169 /* ================================================================================ */
170 
171 /* ------- Start of section using anonymous unions and disabling warnings ------- */
172 #if defined (__CC_ARM)
173  #pragma push
174  #pragma anon_unions
175 #elif defined (__ICCARM__)
176  #pragma language=extended
177 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
178  #pragma clang diagnostic push
179  #pragma clang diagnostic ignored "-Wc11-extensions"
180  #pragma clang diagnostic ignored "-Wreserved-id-macro"
181 #elif defined (__GNUC__)
182  /* anonymous unions are enabled by default */
183 #elif defined (__TMS470__)
184  /* anonymous unions are enabled by default */
185 #elif defined (__TASKING__)
186  #pragma warning 586
187 #elif defined (__CSMC__)
188  /* anonymous unions are enabled by default */
189 #else
190  #warning Not supported compiler type
191 #endif
192 
193 
194 /* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */
195 #define __CM3_REV 0x0201U /* Core revision r2p1 */
196 #define __MPU_PRESENT 0 /* MG32F157 devices does not provide an MPU */
197 #define __VTOR_PRESENT 1 /* VTOR present or not */
198 #define __NVIC_PRIO_BITS 4 /* Number of Bits used for Priority Levels */
199 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
200 
201 #include "core_cm3.h" /* Processor and core peripherals */
202 #include "system_mg32f157.h" /* System Header */
203 
204 
205 
206 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
207 
208 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
209 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
210 
211 typedef enum {INACTIVE = 0, ACTIVE = !INACTIVE} SignalState;
212 
213 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
214 
215 
216 /* ================================================================================ */
217 /* ================ Device Specific Peripheral Section ================ */
218 /* ================================================================================ */
219 
220 
225 /* ================================================================================ */
226 /* ================ Analog to Digital Converter (ADC) ================ */
227 /* ================================================================================ */
228 typedef struct
229 {
230  __IO uint32_t SR;
231  __IO uint32_t CR1;
232  __IO uint32_t CR2;
233  __IO uint32_t SMPR1;
234  __IO uint32_t SMPR2;
235  __IO uint32_t JOFR1;
236  __IO uint32_t JOFR2;
237  __IO uint32_t JOFR3;
238  __IO uint32_t JOFR4;
239  __IO uint32_t HTR;
240  __IO uint32_t LTR;
241  __IO uint32_t SQR1;
242  __IO uint32_t SQR2;
243  __IO uint32_t SQR3;
244  __IO uint32_t JSQR;
245  __IO uint32_t JDR1;
246  __IO uint32_t JDR2;
247  __IO uint32_t JDR3;
248  __IO uint32_t JDR4;
249  __IO uint32_t DR;
250 } ADC_TypeDef;
251 
252 
253 /* ================================================================================ */
254 /* ================ Backup Registers (BKP) ================ */
255 /* ================================================================================ */
256 typedef struct
257 {
258  uint32_t RESERVED0;
259  __IO uint16_t DR1;
260  uint16_t RESERVED1;
261  __IO uint16_t DR2;
262  uint16_t RESERVED2;
263  __IO uint16_t DR3;
264  uint16_t RESERVED3;
265  __IO uint16_t DR4;
266  uint16_t RESERVED4;
267  __IO uint16_t DR5;
268  uint16_t RESERVED5;
269  __IO uint16_t DR6;
270  uint16_t RESERVED6;
271  __IO uint16_t DR7;
272  uint16_t RESERVED7;
273  __IO uint16_t DR8;
274  uint16_t RESERVED8;
275  __IO uint16_t DR9;
276  uint16_t RESERVED9;
277  __IO uint16_t DR10;
278  uint16_t RESERVED10;
279  __IO uint16_t RTCCR;
280  uint16_t RESERVED11;
281  __IO uint16_t CR;
282  uint16_t RESERVED12;
283  __IO uint16_t CSR;
284  uint16_t RESERVED13[5];
285  __IO uint16_t DR11;
286  uint16_t RESERVED14;
287  __IO uint16_t DR12;
288  uint16_t RESERVED15;
289  __IO uint16_t DR13;
290  uint16_t RESERVED16;
291  __IO uint16_t DR14;
292  uint16_t RESERVED17;
293  __IO uint16_t DR15;
294  uint16_t RESERVED18;
295  __IO uint16_t DR16;
296  uint16_t RESERVED19;
297  __IO uint16_t DR17;
298  uint16_t RESERVED20;
299  __IO uint16_t DR18;
300  uint16_t RESERVED21;
301  __IO uint16_t DR19;
302  uint16_t RESERVED22;
303  __IO uint16_t DR20;
304  uint16_t RESERVED23;
305  __IO uint16_t DR21;
306  uint16_t RESERVED24;
307  __IO uint16_t DR22;
308  uint16_t RESERVED25;
309  __IO uint16_t DR23;
310  uint16_t RESERVED26;
311  __IO uint16_t DR24;
312  uint16_t RESERVED27;
313  __IO uint16_t DR25;
314  uint16_t RESERVED28;
315  __IO uint16_t DR26;
316  uint16_t RESERVED29;
317  __IO uint16_t DR27;
318  uint16_t RESERVED30;
319  __IO uint16_t DR28;
320  uint16_t RESERVED31;
321  __IO uint16_t DR29;
322  uint16_t RESERVED32;
323  __IO uint16_t DR30;
324  uint16_t RESERVED33;
325  __IO uint16_t DR31;
326  uint16_t RESERVED34;
327  __IO uint16_t DR32;
328  uint16_t RESERVED35;
329  __IO uint16_t DR33;
330  uint16_t RESERVED36;
331  __IO uint16_t DR34;
332  uint16_t RESERVED37;
333  __IO uint16_t DR35;
334  uint16_t RESERVED38;
335  __IO uint16_t DR36;
336  uint16_t RESERVED39;
337  __IO uint16_t DR37;
338  uint16_t RESERVED40;
339  __IO uint16_t DR38;
340  uint16_t RESERVED41;
341  __IO uint16_t DR39;
342  uint16_t RESERVED42;
343  __IO uint16_t DR40;
344  uint16_t RESERVED43;
345  __IO uint16_t DR41;
346  uint16_t RESERVED44;
347  __IO uint16_t DR42;
348  uint16_t RESERVED45;
349 } BKP_TypeDef;
350 
351 
352 /* ================================================================================ */
353 /* ================ Controller Area Network (CAN) ================ */
354 /* ================================================================================ */
355 typedef struct
356 {
357  __IO uint32_t ISR_SR_CMR_MR;
359  __IO uint32_t TXBUF;
360  __IO uint32_t RXBUF;
361  __IO uint32_t ACR;
362  __IO uint32_t AMR;
364  __IO uint32_t NBT;
365  __IO uint32_t SSPP_TDCR_DBT;
367  __IO uint32_t TEST;
368 } CAN_TypeDef;
369 
370 
371 /* ================================================================================ */
372 /* ================ Cyclic Redundancy Check (CRC) ================ */
373 /* ================================================================================ */
374 typedef struct
375 {
376  __IO uint32_t DR;
377  __IO uint8_t IDR;
378  uint8_t RESERVED0;
379  uint16_t RESERVED1;
380  __IO uint32_t CR;
381 } CRC_TypeDef;
382 
383 
384 /* ================================================================================ */
385 /* ================ True random number generator (TRNG) ================ */
386 /* ================================================================================ */
387 typedef struct
388 {
389  __IO uint32_t CR;
390  __IO uint32_t SR;
391  __IO uint32_t DR;
392 } TRNG_TypeDef;
393 
394 
395 /* ================================================================================ */
396 /* ================ operational amplifier (OPA) ================ */
397 /* ================================================================================ */
398 typedef struct
399 {
400  __IO uint32_t CSR;
401  __IO uint32_t OTR;
402  __IO uint32_t LPOTR;
403 } OPA_TypeDef;
404 
405 
406 /* ================================================================================ */
407 /* ================ Digital to Analog Converter (DAC) ================ */
408 /* ================================================================================ */
409 typedef struct
410 {
411  __IO uint32_t CR;
412  __IO uint32_t SWTRIGR;
413  __IO uint32_t DHR12R1;
414  __IO uint32_t DHR12L1;
415  __IO uint32_t DHR8R1;
416  __IO uint32_t DHR12R2;
417  __IO uint32_t DHR12L2;
418  __IO uint32_t DHR8R2;
419  __IO uint32_t DHR12RD;
420  __IO uint32_t DHR12LD;
421  __IO uint32_t DHR8RD;
422  __IO uint32_t DOR1;
423  __IO uint32_t DOR2;
424 } DAC_TypeDef;
425 
426 
427 /* ================================================================================ */
428 /* ================ Debug MCU (DEBUG) ================ */
429 /* ================================================================================ */
430 typedef struct
431 {
432  __IO uint32_t IDCODE;
433  __IO uint32_t CR;
435 
436 
437 /* ================================================================================ */
438 /* ================ Advanced Encryption Standard (AES) ================ */
439 /* ================================================================================ */
440 typedef struct
441 {
442  __IO uint32_t CR;
443  __IO uint32_t SR;
444  __IO uint32_t DINR;
445  __IO uint32_t DOUTR;
446  __IO uint32_t KEYR0;
447  __IO uint32_t KEYR1;
448  __IO uint32_t KEYR2;
449  __IO uint32_t KEYR3;
450  __IO uint32_t IVR0;
451  __IO uint32_t IVR1;
452  __IO uint32_t IVR2;
453  __IO uint32_t IVR3;
454 } AES_TypeDef;
455 
456 
457 /* ================================================================================ */
458 /* ============== Direct Memory Access Controller (DMAC) ============= */
459 /* ================================================================================ */
460 typedef struct
461 {
462  struct {
463  __IOM uint32_t SAR; uint32_t Undefined_SAR;
464  __IOM uint32_t DAR; uint32_t Undefined_DAR;
465  __IOM uint32_t LLP; uint32_t Undefined_LLP;
466  __IOM uint32_t CTLL;
467  __IOM uint32_t CTLH;
468  __IOM uint32_t SSTAT; uint32_t Undefined_SSTAT;
469  __IOM uint32_t DSTAT; uint32_t Undefined_DSTAT;
470  __IOM uint32_t SSTATAR; uint32_t Undefined_SSTATAR;
471  __IOM uint32_t DSTATAR; uint32_t Undefined_DSTATAR;
472  __IOM uint32_t CFGL;
473  __IOM uint32_t CFGH;
474  uint32_t RESERVED0[4];
475  } Ch[7];
476  uint32_t RESERVED1[22];
477  __IM uint32_t RawTfr; uint32_t Undefined_RawTfr;
478  __IM uint32_t RawBlock; uint32_t Undefined_RawBlock;
479  __IM uint32_t RawSrcTran; uint32_t Undefined_RawSrcTran;
480  __IM uint32_t RawDstTran; uint32_t Undefined_RawDstTran;
481  __IM uint32_t RawErr; uint32_t Undefined_RawErr;
482  __IM uint32_t StatusTfr; uint32_t Undefined_StatusTfr;
483  __IM uint32_t StatusBlock; uint32_t Undefined_StatusBlock;
484  __IM uint32_t StatusSrcTran; uint32_t Undefined_StatusSrcTran;
485  __IM uint32_t StatusDstTran; uint32_t Undefined_StatusDstTran;
486  __IM uint32_t StatusErr; uint32_t Undefined_StatusErr;
487  __IOM uint32_t MaskTfr; uint32_t Undefined_MaskTfr;
488  __IOM uint32_t MaskBlock; uint32_t Undefined_MaskBlock;
489  __IOM uint32_t MaskSrcTran; uint32_t Undefined_MaskSrcTran;
490  __IOM uint32_t MaskDstTran; uint32_t Undefined_MaskDstTran;
491  __IOM uint32_t MaskErr; uint32_t Undefined_MaskErr;
492  __OM uint32_t ClearTfr; uint32_t Undefined_ClearTfr;
493  __OM uint32_t ClearBlock; uint32_t Undefined_ClearBlock;
494  __OM uint32_t ClearSrcTran; uint32_t Undefined_ClearSrcTran;
495  __OM uint32_t ClearDstTran; uint32_t Undefined_ClearDstTran;
496  __OM uint32_t ClearErr; uint32_t Undefined_ClearErr;
497  __IM uint32_t StatusInt; uint32_t Undefined_StatusInt;
498  __IOM uint32_t ReqSrcReg; uint32_t Undefined_ReqSrcReg;
499  __IOM uint32_t ReqDstReg; uint32_t Undefined_ReqDstReg;
500  __IOM uint32_t SglReqSrcReg; uint32_t Undefined_SglReqSrcReg;
501  __IOM uint32_t SglReqDstReg; uint32_t Undefined_SglReqDstReg;
502  __IOM uint32_t LstSrcReg; uint32_t Undefined_LstSrcReg;
503  __IOM uint32_t LstDstReg; uint32_t Undefined_LstDstReg;
504  __IOM uint32_t DmaCfgReg; uint32_t Undefined_DmaCfgReg;
505  __IOM uint32_t ChEnReg; uint32_t Undefined_ChEnReg;
506 } DMAC_TypeDef;
507 
508 
509 /* ================================================================================ */
510 /* ============== Universal Serial Bus (USB) ============= */
511 /* ================================================================================ */
512 typedef struct
513 {
514  __IOM uint8_t FADDR;
515  __IOM uint8_t POWER;
516  __IM uint16_t INTRTX;
517  __IM uint16_t INTRRX;
518  __IOM uint16_t INTRTXE;
519  __IOM uint16_t INTRRXE;
520  __IM uint8_t INTRUSB;
521  __IOM uint8_t INTRUSBE;
522  __IM uint16_t FRAME;
523  __IOM uint8_t INDEX;
524  __IOM uint8_t TESTMODE;
526  __IOM uint16_t TXMAXP;
527  union {
528  __IOM uint8_t CSR0L;
529  __IOM uint8_t TXCSRL;
530  };
531  union {
532  __IOM uint8_t CSR0H;
533  __IOM uint8_t TXCSRH;
534  };
535  __IOM uint16_t RXMAXP;
536  __IOM uint8_t RXCSRL;
537  __IOM uint8_t RXCSRH;
538  union {
539  __IM uint16_t COUNT0;
540  __IM uint16_t RXCOUNT;
541  };
542  union {
543  __IOM uint8_t TYPE0;
544  __IOM uint8_t TXTYPE;
545  };
546  union {
547  __IOM uint8_t NAKLIMIT0;
548  __IOM uint8_t TXINTERVAL;
549  };
550  __IOM uint8_t RXTYPE;
551  __IOM uint8_t RXINTERVAL;
552  uint8_t RESERVED1;
553  union {
554  __IOM uint8_t CONFIGDATA;
555  __IOM uint8_t FIFOSIZE;
556  };
557 
558  __IOM uint32_t FIFO[16];
560  __IOM uint8_t DEVCTL;
561  __IOM uint8_t MISC;
562  __IOM uint8_t TXFIFOSZ;
563  __IOM uint8_t RXFIFOSZ;
564  __IOM uint16_t TXFIFOADD;
565  __IOM uint16_t RXFIFOADD;
566  union {
567  __OM uint32_t VCONTROL;
568  __IM uint32_t VSTATUS;
569  };
570  __IM uint16_t HWVERS;
571  uint8_t RESERVED2[10];
572  __IM uint8_t EPINFO;
573  __IM uint8_t RAMINFO;
574  __IOM uint8_t LINKINFO;
575  __IOM uint8_t VPLEN;
576  __IOM uint8_t HS_EOF1;
577  __IOM uint8_t FS_EOF1;
578  __IOM uint8_t LS_EOF1;
579  __IOM uint8_t SOFT_RST;
580 } USB_TypeDef;
581 
582 
583 /* ================================================================================ */
584 /* ================ External Interrupt/Event Controller (EXTI) ================ */
585 /* ================================================================================ */
586 typedef struct
587 {
588  __IO uint32_t IMR;
589  __IO uint32_t EMR;
590  __IO uint32_t RTSR;
591  __IO uint32_t FTSR;
592  __IO uint32_t SWIER;
593  __IO uint32_t PR;
594 } EXTI_TypeDef;
595 
596 
597 /* ================================================================================ */
598 /* ================ FLASH Registers (FLASH) ================ */
599 /* ================================================================================ */
600 typedef struct
601 {
602  __IO uint32_t ACR;
603  __IO uint32_t KEYR;
604  __IO uint32_t OPTKEYR;
605  __IO uint32_t SR;
606  __IO uint32_t CR;
607  __IO uint32_t AR;
608  __IO uint32_t RESERVED;
609  __IO uint32_t OBR;
610  __IO uint32_t WRPR;
611  __IO uint32_t OP_MODE;
612 } FLASH_TypeDef;
613 
614 
615 /* ================================================================================ */
616 /* ================ Option Bytes Registers (OP) ================ */
617 /* ================================================================================ */
618 typedef struct
619 {
620  __IO uint16_t RDP;
621  __IO uint16_t USER;
622  __IO uint16_t Data0;
623  __IO uint16_t Data1;
624  __IO uint16_t WRP0;
625  __IO uint16_t WRP1;
626  __IO uint16_t WRP2;
627  __IO uint16_t WRP3;
628 } OB_TypeDef;
629 
630 
631 /* ================================================================================ */
632 /* ================ General-purpose I/Os (GPIO) ================ */
633 /* ================================================================================ */
634 typedef struct
635 {
636  __IO uint32_t CRL;
637  __IO uint32_t CRH;
638  __IO uint32_t IDR;
639  __IO uint32_t ODR;
640  __IO uint32_t BSRR;
641  __IO uint32_t BRR;
642  __IO uint32_t LCKR;
643 } GPIO_TypeDef;
644 
645 
646 /* ================================================================================ */
647 /* ================ Alternate Function I/O (AFIO) ================ */
648 /* ================================================================================ */
649 typedef struct
650 {
651  __IO uint32_t EVCR;
652  __IO uint32_t MAPR;
653  __IO uint32_t EXTICR[4];
654  uint32_t RESERVED0;
655  __IO uint32_t MAPR2;
656 } AFIO_TypeDef;
657 
658 
659 /* ================================================================================ */
660 /* ============== Inter-Integrated Circuit (I2C) ============= */
661 /* ================================================================================ */
662 typedef struct
663 {
664  __IOM uint32_t CON;
665  __IOM uint32_t TAR;
666  __IOM uint32_t SAR;
667  uint32_t RESERVED0;
668  __IOM uint32_t DATA_CMD;
669  __IOM uint32_t SS_SCL_HCNT;
670  __IOM uint32_t SS_SCL_LCNT;
671  __IOM uint32_t FS_SCL_HCNT;
672  __IOM uint32_t FS_SCL_LCNT;
673  uint32_t RESERVED1;
674  uint32_t RESERVED2;
675  __IM uint32_t INTR_STAT;
676  __IOM uint32_t INTR_MASK;
677  __IM uint32_t RAW_INTR_STAT;
678  __IOM uint32_t RX_TL;
679  __IOM uint32_t TX_TL;
680  __IM uint32_t CLR_INTR;
681  __IM uint32_t CLR_RX_UNDER;
682  __IM uint32_t CLR_RX_OVER;
683  __IM uint32_t CLR_TX_OVER;
684  __IM uint32_t CLR_RD_REQ;
685  __IM uint32_t CLR_TX_ABRT;
686  __IM uint32_t CLR_RX_DONE;
687  __IM uint32_t CLR_ACTIVITY;
688  __IM uint32_t CLR_STOP_DET;
689  __IM uint32_t CLR_START_DET;
690  __IM uint32_t CLR_GEN_CALL;
691  __IOM uint32_t ENABLE;
692  __IM uint32_t STATUS;
693  __IM uint32_t TXFLR;
694  __IM uint32_t RXFLR;
695  __IOM uint32_t SDA_HOLD;
696  __IM uint32_t TX_ABRT_SOURCE;
697  uint32_t RESERVED3;
698  __IOM uint32_t DMA_CR;
699  __IOM uint32_t DMA_TDLR;
700  __IOM uint32_t DMA_RDLR;
701  __IOM uint32_t SDA_SETUP;
702  __IOM uint32_t ACK_GENERAL_CALL;
703  __IM uint32_t ENABLE_STATUS;
704  __IOM uint32_t FS_SPKLEN;
705  uint32_t RESERVED4[2];
706  __IOM uint32_t SCL_STUCK_AT_LOW_TIMEOUT;
707  __IOM uint32_t SDA_STUCK_AT_LOW_TIMEOUT;
708  __IM uint32_t CLR_SCL_STUCK_DET;
709  uint32_t RESERVED5;
710  __IOM uint32_t SMBUS_CLK_LOW_SEXT;
711  __IOM uint32_t SMBUS_CLK_LOW_MEXT;
712  __IOM uint32_t SMBUS_THIGH_MAX_IDLE_COUNT;
713  __IM uint32_t SMBUS_INTR_STAT;
714  __IOM uint32_t SMBUS_INTR_MASK;
715  __IM uint32_t SMBUS_RAW_INTR_STAT;
716  __OM uint32_t CLR_SMBUS_INTR;
717  __IOM uint32_t OPTIONAL_SAR;
718  __IOM uint32_t SMBUS_UDID_LSB;
719 } I2C_TypeDef;
720 
721 
722 /* ================================================================================ */
723 /* ================ Independent watchdog (IWDG) ================ */
724 /* ================================================================================ */
725 typedef struct
726 {
727  __IO uint32_t KR;
728  __IO uint32_t PR;
729  __IO uint32_t RLR;
730  __IO uint32_t SR;
731 } IWDG_TypeDef;
732 
733 
734 /* ================================================================================ */
735 /* ================ Power Control (PWR) ================ */
736 /* ================================================================================ */
737 typedef struct
738 {
739  __IO uint32_t CR;
740  __IO uint32_t CSR;
741 } PWR_TypeDef;
742 
743 
744 /* ================================================================================ */
745 /* ================ Reset and Clock Control (RCC) ================ */
746 /* ================================================================================ */
747 typedef struct
748 {
749  __IO uint32_t CR;
750  __IO uint32_t CFGR;
751  __IO uint32_t CIR;
752  __IO uint32_t APB2RSTR;
753  __IO uint32_t APB1RSTR;
754  __IO uint32_t AHBENR;
755  __IO uint32_t APB2ENR;
756  __IO uint32_t APB1ENR;
757  __IO uint32_t BDCR;
758  __IO uint32_t CSR;
759 } RCC_TypeDef;
760 
761 
762 /* ================================================================================ */
763 /* ================ Real-Time Clock (RTC) ================ */
764 /* ================================================================================ */
765 typedef struct
766 {
767  __IO uint16_t CRH;
768  uint16_t RESERVED0;
769  __IO uint16_t CRL;
770  uint16_t RESERVED1;
771  __IO uint16_t PRLH;
772  uint16_t RESERVED2;
773  __IO uint16_t PRLL;
774  uint16_t RESERVED3;
775  __IO uint16_t DIVH;
776  uint16_t RESERVED4;
777  __IO uint16_t DIVL;
778  uint16_t RESERVED5;
779  __IO uint16_t CNTH;
780  uint16_t RESERVED6;
781  __IO uint16_t CNTL;
782  uint16_t RESERVED7;
783  __IO uint16_t ALRH;
784  uint16_t RESERVED8;
785  __IO uint16_t ALRL;
786  uint16_t RESERVED9;
787 } RTC_TypeDef;
788 
789 
790 /* ================================================================================ */
791 /* ================ SD host Interface (SDIO) ================ */
792 /* ================================================================================ */
793 typedef struct
794 {
795  __IO uint32_t CTRL;
796  __IO uint32_t PWREN;
797  __IO uint32_t CLKDIV;
798  __IO uint32_t RESERVED0;
799  __IO uint32_t CLKENA;
800  __IO uint32_t TMOUT;
801  __IO uint32_t CTYPE;
802  __IO uint32_t BLKSIZ;
803  __IO uint32_t BYTCNT;
804  __IO uint32_t INTMASK;
805  __IO uint32_t CMDARG;
806  __IO uint32_t CMD;
807  __IO uint32_t RESP0;
808  __IO uint32_t RESP1;
809  __IO uint32_t RESP2;
810  __IO uint32_t RESP3;
811  __IO uint32_t MINTSTS;
812  __IO uint32_t RINTSTS;
813  __IO uint32_t STATUS;
814  __IO uint32_t FIFOTH;
815  __IO uint32_t CDETECT;
816  __IO uint32_t WRTPRT;
817  __IO uint32_t RESERVED1;
818  __IO uint32_t TCBCNT;
819  __IO uint32_t TBBCNT;
820  __IO uint32_t RESERVED2[7];
821  __IO uint32_t BMOD;
822  __IO uint32_t PLDMND;
823  __IO uint32_t DBADDR;
824  __IO uint32_t IDSTS;
825  __IO uint32_t IDINTEN;
826  __IO uint32_t DSCADDR;
827  __IO uint32_t BUFADDR;
828  __IO uint32_t RESERVED3[25];
829  __IO uint32_t CARDTHRCTL;
830  __IO uint32_t BACK_END_POWER;
831  __IO uint32_t UHS_REG_EXT;
832  __IO uint32_t EMMC_DDR_REG;
833  __IO uint32_t ENABLE_SHIFT;
834  uint32_t RESERVED4[59];
835  __IO uint32_t FIFO;
836 } SDIO_TypeDef;
837 
838 
839 /* ================================================================================ */
840 /* ============== Serial Peripheral Interface (SPI) ============= */
841 /* ================================================================================ */
842 typedef struct
843 {
844  __IO uint16_t CR1;
845  uint16_t RESERVED0;
846  __IO uint16_t CR2;
847  uint16_t RESERVED1;
848  __IO uint16_t SR;
849  uint16_t RESERVED2;
850  __IO uint16_t DR;
851  uint16_t RESERVED3;
852  __IO uint16_t CRCPR;
853  uint16_t RESERVED4;
854  __IO uint16_t RXCRCR;
855  uint16_t RESERVED5;
856  __IO uint16_t TXCRCR;
857  uint16_t RESERVED6;
858  __IO uint16_t I2SCFGR;
859  uint16_t RESERVED7;
860  __IO uint16_t I2SPR;
861  uint16_t RESERVED8;
862 } SPI_TypeDef;
863 
864 
865 /* ================================================================================ */
866 /* ============== Quad-SPI Interface (QSPI) ============= */
867 /* ================================================================================ */
868 typedef struct
869 {
870  __IO uint32_t CR;
871  __IO uint32_t DCR;
872  __IO uint32_t SR;
873  __IO uint32_t FCR;
874  __IO uint32_t DLR;
875  __IO uint32_t CCR;
876  __IO uint32_t AR;
877  __IO uint32_t ABR;
878  __IO uint32_t DR;
879  __IO uint32_t PSMKR;
880  __IO uint32_t PSMAR;
881  __IO uint32_t PIR;
882  __IO uint32_t LPTR;
884 
885 
886 /* ================================================================================ */
887 /* ================ Timer (TIM) ================ */
888 /* ================================================================================ */
889 typedef struct
890 {
891  __IOM uint32_t CR1;
892  __IOM uint32_t CR2;
893  __IOM uint32_t SMCR;
894  __IOM uint32_t DIER;
895  __IOM uint32_t SR;
896  __OM uint32_t EGR;
897  __IOM uint32_t CCMR1;
898  __IOM uint32_t CCMR2;
899  __IOM uint32_t CCER;
900  __IOM uint32_t CNT;
901  __IOM uint32_t PSC;
902  __IOM uint32_t ARR;
903  __IOM uint32_t RCR;
904  __IOM uint32_t CCR1;
905  __IOM uint32_t CCR2;
906  __IOM uint32_t CCR3;
907  __IOM uint32_t CCR4;
908  __IOM uint32_t BDTR;
909  __IOM uint32_t DCR;
910  __IOM uint32_t DMAR;
911 } TIM_TypeDef;
912 
913 
914 /* ================================================================================ */
915 /* ======= Universal Synchronous Asyncronous Receiver / Transmitter (USART) ======= */
916 /* ================================================================================ */
917 typedef struct
918 {
919  __IO uint16_t SR;
920  uint16_t RESERVED0;
921  __IO uint16_t DR;
922  uint16_t RESERVED1;
923  __IO uint16_t BRR;
924  uint16_t RESERVED2;
925  __IO uint16_t CR1;
926  uint16_t RESERVED3;
927  __IO uint16_t CR2;
928  uint16_t RESERVED4;
929  __IO uint16_t CR3;
930  uint16_t RESERVED5;
931  __IO uint16_t GTPR;
932  uint16_t RESERVED6;
933 } USART_TypeDef;
934 
935 
936 /* ================================================================================ */
937 /* ================ Window watchdog (WWDG) ================ */
938 /* ================================================================================ */
939 typedef struct
940 {
941  __IO uint32_t CR;
942  __IO uint32_t CFR;
943  __IO uint32_t SR;
944 } WWDG_TypeDef;
945 
951 /* -------- End of section using anonymous unions and disabling warnings -------- */
952 #if defined (__CC_ARM)
953  #pragma pop
954 #elif defined (__ICCARM__)
955  /* leave anonymous unions enabled */
956 #elif (__ARMCC_VERSION >= 6010050)
957  #pragma clang diagnostic pop
958 #elif defined (__GNUC__)
959  /* anonymous unions are enabled by default */
960 #elif defined (__TMS470__)
961  /* anonymous unions are enabled by default */
962 #elif defined (__TASKING__)
963  #pragma warning restore
964 #elif defined (__CSMC__)
965  /* anonymous unions are enabled by default */
966 #else
967  #warning Not supported compiler type
968 #endif
969 
970 
971 
977 #define FLASH_BASE ((uint32_t)0x08000000)
978 #define SRAM_BASE ((uint32_t)0x20000000)
979 #define PERIPH_BASE ((uint32_t)0x40000000)
981 #define SRAM_BB_BASE ((uint32_t)0x22000000)
982 #define PERIPH_BB_BASE ((uint32_t)0x42000000)
985 #define APB1PERIPH_BASE PERIPH_BASE // 4000_0000
986 #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) // 4001_0000
987 #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) // 4002_0000
988 
989 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) // 4000_0000
990 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) // 4000_0400
991 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) // 4000_0800
992 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) // 4000_0C00
993 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000) // 4000_1000
994 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400) // 4000_1400
995 #define RTC_BASE (APB1PERIPH_BASE + 0x2800) // 4000_2800
996 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) // 4000_2C00
997 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) // 4000_3000
998 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800) // 4000_3800
999 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) // 4000_3C00
1000 #define USART2_BASE (APB1PERIPH_BASE + 0x4400) // 4000_4400
1001 #define USART3_BASE (APB1PERIPH_BASE + 0x4800) // 4000_4800
1002 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00) // 4000_4C00
1003 #define UART5_BASE (APB1PERIPH_BASE + 0x5000) // 4000_5000
1004 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) // 4000_5400
1005 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) // 4000_5800
1006 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400) // 4000_6400
1007 #define BKP_BASE (APB1PERIPH_BASE + 0x6C00) // 4000_6C00
1008 #define PWR_BASE (APB1PERIPH_BASE + 0x7000) // 4000_7000
1009 #define DAC_BASE (APB1PERIPH_BASE + 0x7400) // 4000_7400
1010 
1011 #define AFIO_BASE (APB2PERIPH_BASE + 0x0000) // 4001_0000
1012 #define OPA1_BASE (APB2PERIPH_BASE + 0x0200) // 4001_0200
1013 #define OPA2_BASE (APB2PERIPH_BASE + 0x0280) // 4001_0280
1014 #define OPA3_BASE (APB2PERIPH_BASE + 0x0300) // 4001_0300
1015 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400) // 4001_0400
1016 #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) // 4001_0800
1017 #define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) // 4001_0C00
1018 #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) // 4001_1000
1019 #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) // 4001_1400
1020 #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) // 4001_1800
1021 #define ADC1_BASE (APB2PERIPH_BASE + 0x2400) // 4001_2400
1022 #define ADC2_BASE (APB2PERIPH_BASE + 0x2800) // 4001_2800
1023 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) // 4001_2C00
1024 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) // 4001_3000
1025 #define TIM8_BASE (APB2PERIPH_BASE + 0x3400) // 4001_3400
1026 #define USART1_BASE (APB2PERIPH_BASE + 0x3800) // 4001_3800
1027 #define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) // 4001_3C00
1028 #define QUADSPI_BASE (APB2PERIPH_BASE + 0x4000) // 4001_4000
1029 
1030 #define USB_BASE (PERIPH_BASE + 0x5C00) // 4000_5C00
1031 #define SDIO_BASE (PERIPH_BASE + 0x18000) // 4001_8000
1032 
1033 #define DMAC1_BASE (AHBPERIPH_BASE + 0x0000) // 4002_0000
1034 #define DMAC2_BASE (AHBPERIPH_BASE + 0x0400) // 4002_0400
1035 #define RCC_BASE (AHBPERIPH_BASE + 0x1000) // 4002_1000
1036 #define CRC_BASE (AHBPERIPH_BASE + 0x3000) // 4002_3000
1037 #define TRNG_BASE (AHBPERIPH_BASE + 0x5000) // 4002_5000
1038 #define AES_BASE (AHBPERIPH_BASE + 0x6000) // 4002_6000
1039 
1040 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000)
1041 #define OB_BASE ((uint32_t)0x1FFFF800)
1043 #define DBGMCU_BASE ((uint32_t)0xE0042000)
1053 #define TIM2 (( TIM_TypeDef *) TIM2_BASE)
1054 #define TIM3 (( TIM_TypeDef *) TIM3_BASE)
1055 #define TIM4 (( TIM_TypeDef *) TIM4_BASE)
1056 #define TIM5 (( TIM_TypeDef *) TIM5_BASE)
1057 #define TIM6 (( TIM_TypeDef *) TIM6_BASE)
1058 #define TIM7 (( TIM_TypeDef *) TIM7_BASE)
1059 #define RTC (( RTC_TypeDef *) RTC_BASE)
1060 #define WWDG (( WWDG_TypeDef *) WWDG_BASE)
1061 #define IWDG (( IWDG_TypeDef *) IWDG_BASE)
1062 #define SPI2 (( SPI_TypeDef *) SPI2_BASE)
1063 #define SPI3 (( SPI_TypeDef *) SPI3_BASE)
1064 #define USART2 (( USART_TypeDef *) USART2_BASE)
1065 #define USART3 (( USART_TypeDef *) USART3_BASE)
1066 #define UART4 (( USART_TypeDef *) UART4_BASE)
1067 #define UART5 (( USART_TypeDef *) UART5_BASE)
1068 #define I2C1 (( I2C_TypeDef *) I2C1_BASE)
1069 #define I2C2 (( I2C_TypeDef *) I2C2_BASE)
1070 #define CAN1 (( CAN_TypeDef *) CAN1_BASE)
1071 #define BKP (( BKP_TypeDef *) BKP_BASE)
1072 #define PWR (( PWR_TypeDef *) PWR_BASE)
1073 #define DAC (( DAC_TypeDef *) DAC_BASE)
1074 #define AFIO (( AFIO_TypeDef *) AFIO_BASE)
1075 #define OPA1 (( OPA_TypeDef *) OPA1_BASE)
1076 #define OPA2 (( OPA_TypeDef *) OPA2_BASE)
1077 #define OPA3 (( OPA_TypeDef *) OPA3_BASE)
1078 #define EXTI (( EXTI_TypeDef *) EXTI_BASE)
1079 #define GPIOA (( GPIO_TypeDef *) GPIOA_BASE)
1080 #define GPIOB (( GPIO_TypeDef *) GPIOB_BASE)
1081 #define GPIOC (( GPIO_TypeDef *) GPIOC_BASE)
1082 #define GPIOD (( GPIO_TypeDef *) GPIOD_BASE)
1083 #define GPIOE (( GPIO_TypeDef *) GPIOE_BASE)
1084 #define ADC1 (( ADC_TypeDef *) ADC1_BASE)
1085 #define ADC2 (( ADC_TypeDef *) ADC2_BASE)
1086 #define TIM1 (( TIM_TypeDef *) TIM1_BASE)
1087 #define SPI1 (( SPI_TypeDef *) SPI1_BASE)
1088 #define TIM8 (( TIM_TypeDef *) TIM8_BASE)
1089 #define USART1 (( USART_TypeDef *) USART1_BASE)
1090 #define ADC3 (( ADC_TypeDef *) ADC3_BASE)
1091 #define QUADSPI (( QUADSPI_TypeDef *) QUADSPI_BASE)
1092 #define SDIO (( SDIO_TypeDef *) SDIO_BASE)
1093 #define USB (( USB_TypeDef *) USB_BASE)
1094 #define DMAC1 (( DMAC_TypeDef *) DMAC1_BASE)
1095 #define DMAC2 (( DMAC_TypeDef *) DMAC2_BASE)
1096 #define RCC (( RCC_TypeDef *) RCC_BASE)
1097 #define CRC (( CRC_TypeDef *) CRC_BASE)
1098 #define RNG (( TRNG_TypeDef *) TRNG_BASE)
1099 #define AES (( AES_TypeDef *) AES_BASE)
1100 #define FLASH (( FLASH_TypeDef *) FLASH_R_BASE)
1101 #define OB (( OB_TypeDef *) OB_BASE)
1102 #define DBGMCU (( DBGMCU_TypeDef *) DBGMCU_BASE)
1103 
1116 /******************************************************************************/
1117 /* Peripheral Registers_Bits_Definition */
1118 /******************************************************************************/
1119 
1120 /******************************************************************************/
1121 /* */
1122 /* CRC calculation unit (CRC) */
1123 /* */
1124 /******************************************************************************/
1125 
1126 /******************* Bit definition for CRC_DR register *********************/
1127 #define CRC_DR_DR_Pos (0U)
1128 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
1129 #define CRC_DR_DR CRC_DR_DR_Msk
1131 /******************* Bit definition for CRC_IDR register ********************/
1132 #define CRC_IDR_IDR_Pos (0U)
1133 #define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos)
1134 #define CRC_IDR_IDR CRC_IDR_IDR_Msk
1136 /******************** Bit definition for CRC_CR register ********************/
1137 #define CRC_CR_RESET_Pos (0U)
1138 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
1139 #define CRC_CR_RESET CRC_CR_RESET_Msk
1141 /******************************************************************************/
1142 /* */
1143 /* Power Control (PWR) */
1144 /* */
1145 /******************************************************************************/
1146 
1147 /******************** Bit definition for PWR_CR register ********************/
1148 #define PWR_CR_LPDS_Pos (0U)
1149 #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos)
1150 #define PWR_CR_LPDS PWR_CR_LPDS_Msk
1151 #define PWR_CR_PDDS_Pos (1U)
1152 #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)
1153 #define PWR_CR_PDDS PWR_CR_PDDS_Msk
1154 #define PWR_CR_CWUF_Pos (2U)
1155 #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)
1156 #define PWR_CR_CWUF PWR_CR_CWUF_Msk
1157 #define PWR_CR_CSBF_Pos (3U)
1158 #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)
1159 #define PWR_CR_CSBF PWR_CR_CSBF_Msk
1160 #define PWR_CR_PVDE_Pos (4U)
1161 #define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos)
1162 #define PWR_CR_PVDE PWR_CR_PVDE_Msk
1164 #define PWR_CR_PLS_Pos (5U)
1165 #define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos)
1166 #define PWR_CR_PLS PWR_CR_PLS_Msk
1167 #define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos)
1168 #define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos)
1169 #define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos)
1172 #define PWR_CR_PLS_LEV0 0x00000000U
1173 #define PWR_CR_PLS_LEV1 0x00000020U
1174 #define PWR_CR_PLS_LEV2 0x00000040U
1175 #define PWR_CR_PLS_LEV3 0x00000060U
1176 #define PWR_CR_PLS_LEV4 0x00000080U
1177 #define PWR_CR_PLS_LEV5 0x000000A0U
1178 #define PWR_CR_PLS_LEV6 0x000000C0U
1179 #define PWR_CR_PLS_LEV7 0x000000E0U
1181 /* Legacy defines */
1182 #define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
1183 #define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
1184 #define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
1185 #define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
1186 #define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
1187 #define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
1188 #define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
1189 #define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
1191 #define PWR_CR_DBP_Pos (8U)
1192 #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)
1193 #define PWR_CR_DBP PWR_CR_DBP_Msk
1195 /******************* Bit definition for PWR_CSR register ********************/
1196 #define PWR_CSR_WUF_Pos (0U)
1197 #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)
1198 #define PWR_CSR_WUF PWR_CSR_WUF_Msk
1199 #define PWR_CSR_SBF_Pos (1U)
1200 #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)
1201 #define PWR_CSR_SBF PWR_CSR_SBF_Msk
1202 #define PWR_CSR_PVDO_Pos (2U)
1203 #define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos)
1204 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk
1205 #define PWR_CSR_EWUP_Pos (8U)
1206 #define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos)
1207 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk
1209 /******************************************************************************/
1210 /* */
1211 /* Backup registers (BKP) */
1212 /* */
1213 /******************************************************************************/
1214 
1215 /******************* Bit definition for BKP_DR1 register ********************/
1216 #define BKP_DR1_D_Pos (0U)
1217 #define BKP_DR1_D_Msk (0xFFFFUL << BKP_DR1_D_Pos)
1218 #define BKP_DR1_D BKP_DR1_D_Msk
1220 /******************* Bit definition for BKP_DR2 register ********************/
1221 #define BKP_DR2_D_Pos (0U)
1222 #define BKP_DR2_D_Msk (0xFFFFUL << BKP_DR2_D_Pos)
1223 #define BKP_DR2_D BKP_DR2_D_Msk
1225 /******************* Bit definition for BKP_DR3 register ********************/
1226 #define BKP_DR3_D_Pos (0U)
1227 #define BKP_DR3_D_Msk (0xFFFFUL << BKP_DR3_D_Pos)
1228 #define BKP_DR3_D BKP_DR3_D_Msk
1230 /******************* Bit definition for BKP_DR4 register ********************/
1231 #define BKP_DR4_D_Pos (0U)
1232 #define BKP_DR4_D_Msk (0xFFFFUL << BKP_DR4_D_Pos)
1233 #define BKP_DR4_D BKP_DR4_D_Msk
1235 /******************* Bit definition for BKP_DR5 register ********************/
1236 #define BKP_DR5_D_Pos (0U)
1237 #define BKP_DR5_D_Msk (0xFFFFUL << BKP_DR5_D_Pos)
1238 #define BKP_DR5_D BKP_DR5_D_Msk
1240 /******************* Bit definition for BKP_DR6 register ********************/
1241 #define BKP_DR6_D_Pos (0U)
1242 #define BKP_DR6_D_Msk (0xFFFFUL << BKP_DR6_D_Pos)
1243 #define BKP_DR6_D BKP_DR6_D_Msk
1245 /******************* Bit definition for BKP_DR7 register ********************/
1246 #define BKP_DR7_D_Pos (0U)
1247 #define BKP_DR7_D_Msk (0xFFFFUL << BKP_DR7_D_Pos)
1248 #define BKP_DR7_D BKP_DR7_D_Msk
1250 /******************* Bit definition for BKP_DR8 register ********************/
1251 #define BKP_DR8_D_Pos (0U)
1252 #define BKP_DR8_D_Msk (0xFFFFUL << BKP_DR8_D_Pos)
1253 #define BKP_DR8_D BKP_DR8_D_Msk
1255 /******************* Bit definition for BKP_DR9 register ********************/
1256 #define BKP_DR9_D_Pos (0U)
1257 #define BKP_DR9_D_Msk (0xFFFFUL << BKP_DR9_D_Pos)
1258 #define BKP_DR9_D BKP_DR9_D_Msk
1260 /******************* Bit definition for BKP_DR10 register *******************/
1261 #define BKP_DR10_D_Pos (0U)
1262 #define BKP_DR10_D_Msk (0xFFFFUL << BKP_DR10_D_Pos)
1263 #define BKP_DR10_D BKP_DR10_D_Msk
1265 /******************* Bit definition for BKP_DR11 register *******************/
1266 #define BKP_DR11_D_Pos (0U)
1267 #define BKP_DR11_D_Msk (0xFFFFUL << BKP_DR11_D_Pos)
1268 #define BKP_DR11_D BKP_DR11_D_Msk
1270 /******************* Bit definition for BKP_DR12 register *******************/
1271 #define BKP_DR12_D_Pos (0U)
1272 #define BKP_DR12_D_Msk (0xFFFFUL << BKP_DR12_D_Pos)
1273 #define BKP_DR12_D BKP_DR12_D_Msk
1275 /******************* Bit definition for BKP_DR13 register *******************/
1276 #define BKP_DR13_D_Pos (0U)
1277 #define BKP_DR13_D_Msk (0xFFFFUL << BKP_DR13_D_Pos)
1278 #define BKP_DR13_D BKP_DR13_D_Msk
1280 /******************* Bit definition for BKP_DR14 register *******************/
1281 #define BKP_DR14_D_Pos (0U)
1282 #define BKP_DR14_D_Msk (0xFFFFUL << BKP_DR14_D_Pos)
1283 #define BKP_DR14_D BKP_DR14_D_Msk
1285 /******************* Bit definition for BKP_DR15 register *******************/
1286 #define BKP_DR15_D_Pos (0U)
1287 #define BKP_DR15_D_Msk (0xFFFFUL << BKP_DR15_D_Pos)
1288 #define BKP_DR15_D BKP_DR15_D_Msk
1290 /******************* Bit definition for BKP_DR16 register *******************/
1291 #define BKP_DR16_D_Pos (0U)
1292 #define BKP_DR16_D_Msk (0xFFFFUL << BKP_DR16_D_Pos)
1293 #define BKP_DR16_D BKP_DR16_D_Msk
1295 /******************* Bit definition for BKP_DR17 register *******************/
1296 #define BKP_DR17_D_Pos (0U)
1297 #define BKP_DR17_D_Msk (0xFFFFUL << BKP_DR17_D_Pos)
1298 #define BKP_DR17_D BKP_DR17_D_Msk
1300 /****************** Bit definition for BKP_DR18 register ********************/
1301 #define BKP_DR18_D_Pos (0U)
1302 #define BKP_DR18_D_Msk (0xFFFFUL << BKP_DR18_D_Pos)
1303 #define BKP_DR18_D BKP_DR18_D_Msk
1305 /******************* Bit definition for BKP_DR19 register *******************/
1306 #define BKP_DR19_D_Pos (0U)
1307 #define BKP_DR19_D_Msk (0xFFFFUL << BKP_DR19_D_Pos)
1308 #define BKP_DR19_D BKP_DR19_D_Msk
1310 /******************* Bit definition for BKP_DR20 register *******************/
1311 #define BKP_DR20_D_Pos (0U)
1312 #define BKP_DR20_D_Msk (0xFFFFUL << BKP_DR20_D_Pos)
1313 #define BKP_DR20_D BKP_DR20_D_Msk
1315 /******************* Bit definition for BKP_DR21 register *******************/
1316 #define BKP_DR21_D_Pos (0U)
1317 #define BKP_DR21_D_Msk (0xFFFFUL << BKP_DR21_D_Pos)
1318 #define BKP_DR21_D BKP_DR21_D_Msk
1320 /******************* Bit definition for BKP_DR22 register *******************/
1321 #define BKP_DR22_D_Pos (0U)
1322 #define BKP_DR22_D_Msk (0xFFFFUL << BKP_DR22_D_Pos)
1323 #define BKP_DR22_D BKP_DR22_D_Msk
1325 /******************* Bit definition for BKP_DR23 register *******************/
1326 #define BKP_DR23_D_Pos (0U)
1327 #define BKP_DR23_D_Msk (0xFFFFUL << BKP_DR23_D_Pos)
1328 #define BKP_DR23_D BKP_DR23_D_Msk
1330 /******************* Bit definition for BKP_DR24 register *******************/
1331 #define BKP_DR24_D_Pos (0U)
1332 #define BKP_DR24_D_Msk (0xFFFFUL << BKP_DR24_D_Pos)
1333 #define BKP_DR24_D BKP_DR24_D_Msk
1335 /******************* Bit definition for BKP_DR25 register *******************/
1336 #define BKP_DR25_D_Pos (0U)
1337 #define BKP_DR25_D_Msk (0xFFFFUL << BKP_DR25_D_Pos)
1338 #define BKP_DR25_D BKP_DR25_D_Msk
1340 /******************* Bit definition for BKP_DR26 register *******************/
1341 #define BKP_DR26_D_Pos (0U)
1342 #define BKP_DR26_D_Msk (0xFFFFUL << BKP_DR26_D_Pos)
1343 #define BKP_DR26_D BKP_DR26_D_Msk
1345 /******************* Bit definition for BKP_DR27 register *******************/
1346 #define BKP_DR27_D_Pos (0U)
1347 #define BKP_DR27_D_Msk (0xFFFFUL << BKP_DR27_D_Pos)
1348 #define BKP_DR27_D BKP_DR27_D_Msk
1350 /******************* Bit definition for BKP_DR28 register *******************/
1351 #define BKP_DR28_D_Pos (0U)
1352 #define BKP_DR28_D_Msk (0xFFFFUL << BKP_DR28_D_Pos)
1353 #define BKP_DR28_D BKP_DR28_D_Msk
1355 /******************* Bit definition for BKP_DR29 register *******************/
1356 #define BKP_DR29_D_Pos (0U)
1357 #define BKP_DR29_D_Msk (0xFFFFUL << BKP_DR29_D_Pos)
1358 #define BKP_DR29_D BKP_DR29_D_Msk
1360 /******************* Bit definition for BKP_DR30 register *******************/
1361 #define BKP_DR30_D_Pos (0U)
1362 #define BKP_DR30_D_Msk (0xFFFFUL << BKP_DR30_D_Pos)
1363 #define BKP_DR30_D BKP_DR30_D_Msk
1365 /******************* Bit definition for BKP_DR31 register *******************/
1366 #define BKP_DR31_D_Pos (0U)
1367 #define BKP_DR31_D_Msk (0xFFFFUL << BKP_DR31_D_Pos)
1368 #define BKP_DR31_D BKP_DR31_D_Msk
1370 /******************* Bit definition for BKP_DR32 register *******************/
1371 #define BKP_DR32_D_Pos (0U)
1372 #define BKP_DR32_D_Msk (0xFFFFUL << BKP_DR32_D_Pos)
1373 #define BKP_DR32_D BKP_DR32_D_Msk
1375 /******************* Bit definition for BKP_DR33 register *******************/
1376 #define BKP_DR33_D_Pos (0U)
1377 #define BKP_DR33_D_Msk (0xFFFFUL << BKP_DR33_D_Pos)
1378 #define BKP_DR33_D BKP_DR33_D_Msk
1380 /******************* Bit definition for BKP_DR34 register *******************/
1381 #define BKP_DR34_D_Pos (0U)
1382 #define BKP_DR34_D_Msk (0xFFFFUL << BKP_DR34_D_Pos)
1383 #define BKP_DR34_D BKP_DR34_D_Msk
1385 /******************* Bit definition for BKP_DR35 register *******************/
1386 #define BKP_DR35_D_Pos (0U)
1387 #define BKP_DR35_D_Msk (0xFFFFUL << BKP_DR35_D_Pos)
1388 #define BKP_DR35_D BKP_DR35_D_Msk
1390 /******************* Bit definition for BKP_DR36 register *******************/
1391 #define BKP_DR36_D_Pos (0U)
1392 #define BKP_DR36_D_Msk (0xFFFFUL << BKP_DR36_D_Pos)
1393 #define BKP_DR36_D BKP_DR36_D_Msk
1395 /******************* Bit definition for BKP_DR37 register *******************/
1396 #define BKP_DR37_D_Pos (0U)
1397 #define BKP_DR37_D_Msk (0xFFFFUL << BKP_DR37_D_Pos)
1398 #define BKP_DR37_D BKP_DR37_D_Msk
1400 /******************* Bit definition for BKP_DR38 register *******************/
1401 #define BKP_DR38_D_Pos (0U)
1402 #define BKP_DR38_D_Msk (0xFFFFUL << BKP_DR38_D_Pos)
1403 #define BKP_DR38_D BKP_DR38_D_Msk
1405 /******************* Bit definition for BKP_DR39 register *******************/
1406 #define BKP_DR39_D_Pos (0U)
1407 #define BKP_DR39_D_Msk (0xFFFFUL << BKP_DR39_D_Pos)
1408 #define BKP_DR39_D BKP_DR39_D_Msk
1410 /******************* Bit definition for BKP_DR40 register *******************/
1411 #define BKP_DR40_D_Pos (0U)
1412 #define BKP_DR40_D_Msk (0xFFFFUL << BKP_DR40_D_Pos)
1413 #define BKP_DR40_D BKP_DR40_D_Msk
1415 /******************* Bit definition for BKP_DR41 register *******************/
1416 #define BKP_DR41_D_Pos (0U)
1417 #define BKP_DR41_D_Msk (0xFFFFUL << BKP_DR41_D_Pos)
1418 #define BKP_DR41_D BKP_DR41_D_Msk
1420 /******************* Bit definition for BKP_DR42 register *******************/
1421 #define BKP_DR42_D_Pos (0U)
1422 #define BKP_DR42_D_Msk (0xFFFFUL << BKP_DR42_D_Pos)
1423 #define BKP_DR42_D BKP_DR42_D_Msk
1425 #define RTC_BKP_NUMBER 42
1426 
1427 /****************** Bit definition for BKP_RTCCR register *******************/
1428 #define BKP_RTCCR_CAL_Pos (0U)
1429 #define BKP_RTCCR_CAL_Msk (0x7FUL << BKP_RTCCR_CAL_Pos)
1430 #define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk
1431 #define BKP_RTCCR_CCO_Pos (7U)
1432 #define BKP_RTCCR_CCO_Msk (0x1UL << BKP_RTCCR_CCO_Pos)
1433 #define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk
1434 #define BKP_RTCCR_ASOE_Pos (8U)
1435 #define BKP_RTCCR_ASOE_Msk (0x1UL << BKP_RTCCR_ASOE_Pos)
1436 #define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk
1437 #define BKP_RTCCR_ASOS_Pos (9U)
1438 #define BKP_RTCCR_ASOS_Msk (0x1UL << BKP_RTCCR_ASOS_Pos)
1439 #define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk
1441 /******************** Bit definition for BKP_CR register ********************/
1442 #define BKP_CR_TPE_Pos (0U)
1443 #define BKP_CR_TPE_Msk (0x1UL << BKP_CR_TPE_Pos)
1444 #define BKP_CR_TPE BKP_CR_TPE_Msk
1445 #define BKP_CR_TPAL_Pos (1U)
1446 #define BKP_CR_TPAL_Msk (0x1UL << BKP_CR_TPAL_Pos)
1447 #define BKP_CR_TPAL BKP_CR_TPAL_Msk
1449 /******************* Bit definition for BKP_CSR register ********************/
1450 #define BKP_CSR_CTE_Pos (0U)
1451 #define BKP_CSR_CTE_Msk (0x1UL << BKP_CSR_CTE_Pos)
1452 #define BKP_CSR_CTE BKP_CSR_CTE_Msk
1453 #define BKP_CSR_CTI_Pos (1U)
1454 #define BKP_CSR_CTI_Msk (0x1UL << BKP_CSR_CTI_Pos)
1455 #define BKP_CSR_CTI BKP_CSR_CTI_Msk
1456 #define BKP_CSR_TPIE_Pos (2U)
1457 #define BKP_CSR_TPIE_Msk (0x1UL << BKP_CSR_TPIE_Pos)
1458 #define BKP_CSR_TPIE BKP_CSR_TPIE_Msk
1459 #define BKP_CSR_TEF_Pos (8U)
1460 #define BKP_CSR_TEF_Msk (0x1UL << BKP_CSR_TEF_Pos)
1461 #define BKP_CSR_TEF BKP_CSR_TEF_Msk
1462 #define BKP_CSR_TIF_Pos (9U)
1463 #define BKP_CSR_TIF_Msk (0x1UL << BKP_CSR_TIF_Pos)
1464 #define BKP_CSR_TIF BKP_CSR_TIF_Msk
1466 /******************************************************************************/
1467 /* */
1468 /* Reset and Clock Control (RCC) */
1469 /* */
1470 /******************************************************************************/
1471 
1472 /******************** Bit definition for RCC_CR register ********************/
1473 #define RCC_CR_HSION_Pos (0U)
1474 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
1475 #define RCC_CR_HSION RCC_CR_HSION_Msk
1476 #define RCC_CR_HSIRDY_Pos (1U)
1477 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
1478 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
1479 #define RCC_CR_HSITRIM_Pos (3U)
1480 #define RCC_CR_HSITRIM_Msk (0xFUL << RCC_CR_HSITRIM_Pos)
1481 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
1482 #define RCC_CR_HSICAL_Pos (7U)
1483 #define RCC_CR_HSICAL_Msk (0x1FFUL << RCC_CR_HSICAL_Pos)
1484 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
1485 #define RCC_CR_HSEON_Pos (16U)
1486 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
1487 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
1488 #define RCC_CR_HSERDY_Pos (17U)
1489 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
1490 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
1491 #define RCC_CR_HSEBYP_Pos (18U)
1492 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
1493 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
1494 #define RCC_CR_CSSON_Pos (19U)
1495 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
1496 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
1497 #define RCC_CR_HSEDL_Pos (20U)
1498 #define RCC_CR_HSEDL_Msk (0x7UL << RCC_CR_HSEDL_Pos)
1499 #define RCC_CR_HSEDL RCC_CR_HSEDL_Msk
1500 #define RCC_CR_PLLON_Pos (24U)
1501 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
1502 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
1503 #define RCC_CR_PLLRDY_Pos (25U)
1504 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
1505 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
1507 /******************* Bit definition for RCC_CFGR register *******************/
1508 
1509 #define RCC_CFGR_SW_Pos (0U)
1510 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
1511 #define RCC_CFGR_SW RCC_CFGR_SW_Msk
1512 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
1513 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
1515 #define RCC_CFGR_SW_HSI 0x00000000U
1516 #define RCC_CFGR_SW_HSE 0x00000001U
1517 #define RCC_CFGR_SW_PLL 0x00000002U
1520 #define RCC_CFGR_SWS_Pos (2U)
1521 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
1522 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
1523 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
1524 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
1526 #define RCC_CFGR_SWS_HSI 0x00000000U
1527 #define RCC_CFGR_SWS_HSE 0x00000004U
1528 #define RCC_CFGR_SWS_PLL 0x00000008U
1531 #define RCC_CFGR_HPRE_Pos (4U)
1532 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
1533 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
1534 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
1535 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
1536 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
1537 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
1539 #define RCC_CFGR_HPRE_DIV1 0x00000000U
1540 #define RCC_CFGR_HPRE_DIV2 0x00000080U
1541 #define RCC_CFGR_HPRE_DIV4 0x00000090U
1542 #define RCC_CFGR_HPRE_DIV8 0x000000A0U
1543 #define RCC_CFGR_HPRE_DIV16 0x000000B0U
1544 #define RCC_CFGR_HPRE_DIV64 0x000000C0U
1545 #define RCC_CFGR_HPRE_DIV128 0x000000D0U
1546 #define RCC_CFGR_HPRE_DIV256 0x000000E0U
1547 #define RCC_CFGR_HPRE_DIV512 0x000000F0U
1550 #define RCC_CFGR_PPRE1_Pos (8U)
1551 #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
1552 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
1553 #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
1554 #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
1555 #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
1557 #define RCC_CFGR_PPRE1_DIV1 0x00000000U
1558 #define RCC_CFGR_PPRE1_DIV2 0x00000400U
1559 #define RCC_CFGR_PPRE1_DIV4 0x00000500U
1560 #define RCC_CFGR_PPRE1_DIV8 0x00000600U
1561 #define RCC_CFGR_PPRE1_DIV16 0x00000700U
1564 #define RCC_CFGR_PPRE2_Pos (11U)
1565 #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
1566 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
1567 #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
1568 #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
1569 #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
1571 #define RCC_CFGR_PPRE2_DIV1 0x00000000U
1572 #define RCC_CFGR_PPRE2_DIV2 0x00002000U
1573 #define RCC_CFGR_PPRE2_DIV4 0x00002800U
1574 #define RCC_CFGR_PPRE2_DIV8 0x00003000U
1575 #define RCC_CFGR_PPRE2_DIV16 0x00003800U
1578 #define RCC_CFGR_ADCPRE_Pos (14U)
1579 #define RCC_CFGR_ADCPRE_Msk (0x3UL << RCC_CFGR_ADCPRE_Pos)
1580 #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk
1581 #define RCC_CFGR_ADCPRE_0 (0x1UL << RCC_CFGR_ADCPRE_Pos)
1582 #define RCC_CFGR_ADCPRE_1 (0x2UL << RCC_CFGR_ADCPRE_Pos)
1584 #define RCC_CFGR_ADCPRE_DIV2 0x00000000U
1585 #define RCC_CFGR_ADCPRE_DIV4 0x00004000U
1586 #define RCC_CFGR_ADCPRE_DIV6 0x00008000U
1587 #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U
1589 #define RCC_CFGR_PLLSRC_Pos (16U)
1590 #define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos)
1591 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk
1593 #define RCC_CFGR_PLLSRC_HSI_DIV2 0x00000000U
1594 #define RCC_CFGR_PLLSRC_HSE 0x00010000U
1596 #define RCC_CFGR_PLLXTPRE_Pos (17U)
1597 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos)
1598 #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk
1601 #define RCC_CFGR_PLLMULL_Pos (18U)
1602 #define RCC_CFGR_PLLMULL_Msk (0xFUL << RCC_CFGR_PLLMULL_Pos)
1603 #define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk
1604 #define RCC_CFGR_PLLMULL_0 (0x1UL << RCC_CFGR_PLLMULL_Pos)
1605 #define RCC_CFGR_PLLMULL_1 (0x2UL << RCC_CFGR_PLLMULL_Pos)
1606 #define RCC_CFGR_PLLMULL_2 (0x4UL << RCC_CFGR_PLLMULL_Pos)
1607 #define RCC_CFGR_PLLMULL_3 (0x8UL << RCC_CFGR_PLLMULL_Pos)
1609 #define RCC_CFGR_PLLXTPRE_HSE 0x00000000U
1610 #define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U
1612 #define RCC_CFGR_PLLMULL2 0x00000000U
1613 #define RCC_CFGR_PLLMULL3_Pos (18U)
1614 #define RCC_CFGR_PLLMULL3_Msk (0x1UL << RCC_CFGR_PLLMULL3_Pos)
1615 #define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk
1616 #define RCC_CFGR_PLLMULL4_Pos (19U)
1617 #define RCC_CFGR_PLLMULL4_Msk (0x1UL << RCC_CFGR_PLLMULL4_Pos)
1618 #define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk
1619 #define RCC_CFGR_PLLMULL5_Pos (18U)
1620 #define RCC_CFGR_PLLMULL5_Msk (0x3UL << RCC_CFGR_PLLMULL5_Pos)
1621 #define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk
1622 #define RCC_CFGR_PLLMULL6_Pos (20U)
1623 #define RCC_CFGR_PLLMULL6_Msk (0x1UL << RCC_CFGR_PLLMULL6_Pos)
1624 #define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk
1625 #define RCC_CFGR_PLLMULL7_Pos (18U)
1626 #define RCC_CFGR_PLLMULL7_Msk (0x5UL << RCC_CFGR_PLLMULL7_Pos)
1627 #define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk
1628 #define RCC_CFGR_PLLMULL8_Pos (19U)
1629 #define RCC_CFGR_PLLMULL8_Msk (0x3UL << RCC_CFGR_PLLMULL8_Pos)
1630 #define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk
1631 #define RCC_CFGR_PLLMULL9_Pos (18U)
1632 #define RCC_CFGR_PLLMULL9_Msk (0x7UL << RCC_CFGR_PLLMULL9_Pos)
1633 #define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk
1634 #define RCC_CFGR_PLLMULL10_Pos (21U)
1635 #define RCC_CFGR_PLLMULL10_Msk (0x1UL << RCC_CFGR_PLLMULL10_Pos)
1636 #define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk
1637 #define RCC_CFGR_PLLMULL11_Pos (18U)
1638 #define RCC_CFGR_PLLMULL11_Msk (0x9UL << RCC_CFGR_PLLMULL11_Pos)
1639 #define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk
1640 #define RCC_CFGR_PLLMULL12_Pos (19U)
1641 #define RCC_CFGR_PLLMULL12_Msk (0x5UL << RCC_CFGR_PLLMULL12_Pos)
1642 #define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk
1643 #define RCC_CFGR_PLLMULL13_Pos (18U)
1644 #define RCC_CFGR_PLLMULL13_Msk (0xBUL << RCC_CFGR_PLLMULL13_Pos)
1645 #define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk
1646 #define RCC_CFGR_PLLMULL14_Pos (20U)
1647 #define RCC_CFGR_PLLMULL14_Msk (0x3UL << RCC_CFGR_PLLMULL14_Pos)
1648 #define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk
1649 #define RCC_CFGR_PLLMULL15_Pos (18U)
1650 #define RCC_CFGR_PLLMULL15_Msk (0xDUL << RCC_CFGR_PLLMULL15_Pos)
1651 #define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk
1652 #define RCC_CFGR_PLLMULL16_Pos (19U)
1653 #define RCC_CFGR_PLLMULL16_Msk (0x7UL << RCC_CFGR_PLLMULL16_Pos)
1654 #define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk
1655 #define RCC_CFGR_USBPRE_Pos (22U)
1656 #define RCC_CFGR_USBPRE_Msk (0x1UL << RCC_CFGR_USBPRE_Pos)
1657 #define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk
1660 #define RCC_CFGR_MCO_Pos (24U)
1661 #define RCC_CFGR_MCO_Msk (0x7UL << RCC_CFGR_MCO_Pos)
1662 #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk
1663 #define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos)
1664 #define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos)
1665 #define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos)
1667 #define RCC_CFGR_MCO_NOCLOCK 0x00000000U
1668 #define RCC_CFGR_MCO_SYSCLK 0x04000000U
1669 #define RCC_CFGR_MCO_HSI 0x05000000U
1670 #define RCC_CFGR_MCO_HSE 0x06000000U
1671 #define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U
1674 #define RCC_CIR_LSIRDYF_Pos (0U)
1675 #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)
1676 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
1677 #define RCC_CIR_LSERDYF_Pos (1U)
1678 #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)
1679 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
1680 #define RCC_CIR_HSIRDYF_Pos (2U)
1681 #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)
1682 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
1683 #define RCC_CIR_HSERDYF_Pos (3U)
1684 #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)
1685 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
1686 #define RCC_CIR_PLLRDYF_Pos (4U)
1687 #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)
1688 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
1689 #define RCC_CIR_CSSF_Pos (7U)
1690 #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)
1691 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
1692 #define RCC_CIR_LSIRDYIE_Pos (8U)
1693 #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)
1694 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
1695 #define RCC_CIR_LSERDYIE_Pos (9U)
1696 #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)
1697 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
1698 #define RCC_CIR_HSIRDYIE_Pos (10U)
1699 #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)
1700 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
1701 #define RCC_CIR_HSERDYIE_Pos (11U)
1702 #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)
1703 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
1704 #define RCC_CIR_PLLRDYIE_Pos (12U)
1705 #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)
1706 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
1707 #define RCC_CIR_LSIRDYC_Pos (16U)
1708 #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)
1709 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
1710 #define RCC_CIR_LSERDYC_Pos (17U)
1711 #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)
1712 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
1713 #define RCC_CIR_HSIRDYC_Pos (18U)
1714 #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)
1715 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
1716 #define RCC_CIR_HSERDYC_Pos (19U)
1717 #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)
1718 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
1719 #define RCC_CIR_PLLRDYC_Pos (20U)
1720 #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)
1721 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
1722 #define RCC_CIR_CSSC_Pos (23U)
1723 #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)
1724 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
1726 /***************** Bit definition for RCC_APB2RSTR register *****************/
1727 #define RCC_APB2RSTR_AFIORST_Pos (0U)
1728 #define RCC_APB2RSTR_AFIORST_Msk (0x1UL << RCC_APB2RSTR_AFIORST_Pos)
1729 #define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk
1730 #define RCC_APB2RSTR_IOPARST_Pos (2U)
1731 #define RCC_APB2RSTR_IOPARST_Msk (0x1UL << RCC_APB2RSTR_IOPARST_Pos)
1732 #define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk
1733 #define RCC_APB2RSTR_IOPBRST_Pos (3U)
1734 #define RCC_APB2RSTR_IOPBRST_Msk (0x1UL << RCC_APB2RSTR_IOPBRST_Pos)
1735 #define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk
1736 #define RCC_APB2RSTR_IOPCRST_Pos (4U)
1737 #define RCC_APB2RSTR_IOPCRST_Msk (0x1UL << RCC_APB2RSTR_IOPCRST_Pos)
1738 #define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk
1739 #define RCC_APB2RSTR_IOPDRST_Pos (5U)
1740 #define RCC_APB2RSTR_IOPDRST_Msk (0x1UL << RCC_APB2RSTR_IOPDRST_Pos)
1741 #define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk
1742 #define RCC_APB2RSTR_IOPERST_Pos (6U)
1743 #define RCC_APB2RSTR_IOPERST_Msk (0x1UL << RCC_APB2RSTR_IOPERST_Pos)
1744 #define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk
1745 #define RCC_APB2RSTR_ADC1RST_Pos (9U)
1746 #define RCC_APB2RSTR_ADC1RST_Msk (0x1UL << RCC_APB2RSTR_ADC1RST_Pos)
1747 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk
1748 #define RCC_APB2RSTR_ADC2RST_Pos (10U)
1749 #define RCC_APB2RSTR_ADC2RST_Msk (0x1UL << RCC_APB2RSTR_ADC2RST_Pos)
1750 #define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk
1751 #define RCC_APB2RSTR_TIM1RST_Pos (11U)
1752 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
1753 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
1754 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
1755 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
1756 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
1757 #define RCC_APB2RSTR_TIM8RST_Pos (13U)
1758 #define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
1759 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
1760 #define RCC_APB2RSTR_USART1RST_Pos (14U)
1761 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
1762 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
1763 #define RCC_APB2RSTR_ADC3RST_Pos (15U)
1764 #define RCC_APB2RSTR_ADC3RST_Msk (0x1UL << RCC_APB2RSTR_ADC3RST_Pos)
1765 #define RCC_APB2RSTR_ADC3RST RCC_APB2RSTR_ADC3RST_Msk
1767 /***************** Bit definition for RCC_APB1RSTR register *****************/
1768 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
1769 #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)
1770 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
1771 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
1772 #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
1773 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
1774 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
1775 #define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)
1776 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
1777 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
1778 #define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)
1779 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
1780 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
1781 #define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)
1782 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
1783 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
1784 #define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)
1785 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
1786 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
1787 #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
1788 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
1789 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
1790 #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)
1791 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
1792 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
1793 #define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)
1794 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
1795 #define RCC_APB1RSTR_USART2RST_Pos (17U)
1796 #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)
1797 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
1798 #define RCC_APB1RSTR_USART3RST_Pos (18U)
1799 #define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos)
1800 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
1801 #define RCC_APB1RSTR_UART4RST_Pos (19U)
1802 #define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos)
1803 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
1804 #define RCC_APB1RSTR_UART5RST_Pos (20U)
1805 #define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos)
1806 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
1807 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
1808 #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
1809 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
1810 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
1811 #define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)
1812 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
1813 #define RCC_APB1RSTR_USBRST_Pos (23U)
1814 #define RCC_APB1RSTR_USBRST_Msk (0x1UL << RCC_APB1RSTR_USBRST_Pos)
1815 #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk
1816 #define RCC_APB1RSTR_CAN1RST_Pos (25U)
1817 #define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)
1818 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
1819 #define RCC_APB1RSTR_BKPRST_Pos (27U)
1820 #define RCC_APB1RSTR_BKPRST_Msk (0x1UL << RCC_APB1RSTR_BKPRST_Pos)
1821 #define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk
1822 #define RCC_APB1RSTR_PWRRST_Pos (28U)
1823 #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
1824 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
1825 #define RCC_APB1RSTR_DACRST_Pos (29U)
1826 #define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos)
1827 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
1829 /****************** Bit definition for RCC_AHBENR register ******************/
1830 #define RCC_AHBENR_DMAC1EN_Pos (0U)
1831 #define RCC_AHBENR_DMAC1EN_Msk (0x1UL << RCC_AHBENR_DMAC1EN_Pos)
1832 #define RCC_AHBENR_DMAC1EN RCC_AHBENR_DMAC1EN_Msk
1833 #define RCC_AHBENR_DMAC2EN_Pos (1U)
1834 #define RCC_AHBENR_DMAC2EN_Msk (0x1UL << RCC_AHBENR_DMAC2EN_Pos)
1835 #define RCC_AHBENR_DMAC2EN RCC_AHBENR_DMAC2EN_Msk
1836 #define RCC_AHBENR_SRAMEN_Pos (2U)
1837 #define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos)
1838 #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk
1839 #define RCC_AHBENR_FLITFEN_Pos (4U)
1840 #define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos)
1841 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk
1842 #define RCC_AHBENR_RNGEN_Pos (5U)
1843 #define RCC_AHBENR_RNGEN_Msk (0x1UL << RCC_AHBENR_RNGEN_Pos)
1844 #define RCC_AHBENR_RNGEN RCC_AHBENR_RNGEN_Msk
1845 #define RCC_AHBENR_CRCEN_Pos (6U)
1846 #define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos)
1847 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk
1848 #define RCC_AHBENR_AESEN_Pos (7U)
1849 #define RCC_AHBENR_AESEN_Msk (0x1UL << RCC_AHBENR_AESEN_Pos)
1850 #define RCC_AHBENR_AESEN RCC_AHBENR_AESEN_Msk
1851 #define RCC_AHBENR_QUADSPIEN_Pos (8U)
1852 #define RCC_AHBENR_QUADSPIEN_Msk (0x1UL << RCC_AHBENR_QUADSPIEN_Pos)
1853 #define RCC_AHBENR_QUADSPIIEN RCC_AHBENR_QUADSPIEN_Msk
1854 #define RCC_AHBENR_SDIOEN_Pos (10U)
1855 #define RCC_AHBENR_SDIOEN_Msk (0x1UL << RCC_AHBENR_SDIOEN_Pos)
1856 #define RCC_AHBENR_SDIOEN RCC_AHBENR_SDIOEN_Msk
1858 /****************** Bit definition for RCC_APB2ENR register *****************/
1859 #define RCC_APB2ENR_AFIOEN_Pos (0U)
1860 #define RCC_APB2ENR_AFIOEN_Msk (0x1UL << RCC_APB2ENR_AFIOEN_Pos)
1861 #define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk
1862 #define RCC_APB2ENR_IOPAEN_Pos (2U)
1863 #define RCC_APB2ENR_IOPAEN_Msk (0x1UL << RCC_APB2ENR_IOPAEN_Pos)
1864 #define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk
1865 #define RCC_APB2ENR_IOPBEN_Pos (3U)
1866 #define RCC_APB2ENR_IOPBEN_Msk (0x1UL << RCC_APB2ENR_IOPBEN_Pos)
1867 #define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk
1868 #define RCC_APB2ENR_IOPCEN_Pos (4U)
1869 #define RCC_APB2ENR_IOPCEN_Msk (0x1UL << RCC_APB2ENR_IOPCEN_Pos)
1870 #define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk
1871 #define RCC_APB2ENR_IOPDEN_Pos (5U)
1872 #define RCC_APB2ENR_IOPDEN_Msk (0x1UL << RCC_APB2ENR_IOPDEN_Pos)
1873 #define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk
1874 #define RCC_APB2ENR_IOPEEN_Pos (6U)
1875 #define RCC_APB2ENR_IOPEEN_Msk (0x1UL << RCC_APB2ENR_IOPEEN_Pos)
1876 #define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk
1877 #define RCC_APB2ENR_ADC1EN_Pos (9U)
1878 #define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos)
1879 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
1880 #define RCC_APB2ENR_ADC2EN_Pos (10U)
1881 #define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos)
1882 #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
1883 #define RCC_APB2ENR_TIM1EN_Pos (11U)
1884 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
1885 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
1886 #define RCC_APB2ENR_SPI1EN_Pos (12U)
1887 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
1888 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
1889 #define RCC_APB2ENR_TIM8EN_Pos (13U)
1890 #define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
1891 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
1892 #define RCC_APB2ENR_USART1EN_Pos (14U)
1893 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
1894 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
1895 #define RCC_APB2ENR_ADC3EN_Pos (15U)
1896 #define RCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos)
1897 #define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
1899 /***************** Bit definition for RCC_APB1ENR register ******************/
1900 #define RCC_APB1ENR_TIM2EN_Pos (0U)
1901 #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
1902 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
1903 #define RCC_APB1ENR_TIM3EN_Pos (1U)
1904 #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
1905 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
1906 #define RCC_APB1ENR_TIM4EN_Pos (2U)
1907 #define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)
1908 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
1909 #define RCC_APB1ENR_TIM5EN_Pos (3U)
1910 #define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos)
1911 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
1912 #define RCC_APB1ENR_TIM6EN_Pos (4U)
1913 #define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)
1914 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
1915 #define RCC_APB1ENR_TIM7EN_Pos (5U)
1916 #define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)
1917 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
1918 #define RCC_APB1ENR_WWDGEN_Pos (11U)
1919 #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
1920 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
1921 #define RCC_APB1ENR_SPI2EN_Pos (14U)
1922 #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)
1923 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
1924 #define RCC_APB1ENR_SPI3EN_Pos (15U)
1925 #define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos)
1926 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
1927 #define RCC_APB1ENR_USART2EN_Pos (17U)
1928 #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)
1929 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
1930 #define RCC_APB1ENR_USART3EN_Pos (18U)
1931 #define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)
1932 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
1933 #define RCC_APB1ENR_UART4EN_Pos (19U)
1934 #define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos)
1935 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
1936 #define RCC_APB1ENR_UART5EN_Pos (20U)
1937 #define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos)
1938 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
1939 #define RCC_APB1ENR_I2C1EN_Pos (21U)
1940 #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
1941 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
1942 #define RCC_APB1ENR_I2C2EN_Pos (22U)
1943 #define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)
1944 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
1945 #define RCC_APB1ENR_USBEN_Pos (23U)
1946 #define RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos)
1947 #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk
1948 #define RCC_APB1ENR_CAN1EN_Pos (25U)
1949 #define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos)
1950 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
1951 #define RCC_APB1ENR_BKPEN_Pos (27U)
1952 #define RCC_APB1ENR_BKPEN_Msk (0x1UL << RCC_APB1ENR_BKPEN_Pos)
1953 #define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk
1954 #define RCC_APB1ENR_PWREN_Pos (28U)
1955 #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)
1956 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
1957 #define RCC_APB1ENR_DACEN_Pos (29U)
1958 #define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos)
1959 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
1961 /******************* Bit definition for RCC_BDCR register *******************/
1962 #define RCC_BDCR_LSEON_Pos (0U)
1963 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
1964 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
1965 #define RCC_BDCR_LSERDY_Pos (1U)
1966 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
1967 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
1968 #define RCC_BDCR_LSEBYP_Pos (2U)
1969 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
1970 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
1971 #define RCC_BDCR_LSEDL_Pos (3U)
1972 #define RCC_BDCR_LSEDL_Msk (0xFUL << RCC_BDCR_LSEDL_Pos)
1973 #define RCC_BDCR_LSEDL RCC_BDCR_LSEDL_Msk
1975 #define RCC_BDCR_RTCSEL_Pos (8U)
1976 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
1977 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
1978 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
1979 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
1982 #define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U
1983 #define RCC_BDCR_RTCSEL_LSE 0x00000100U
1984 #define RCC_BDCR_RTCSEL_LSI 0x00000200U
1985 #define RCC_BDCR_RTCSEL_HSE 0x00000300U
1987 #define RCC_BDCR_RTCEN_Pos (15U)
1988 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
1989 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
1990 #define RCC_BDCR_BDRST_Pos (16U)
1991 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
1992 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
1994 /******************* Bit definition for RCC_CSR register ********************/
1995 #define RCC_CSR_LSION_Pos (0U)
1996 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
1997 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
1998 #define RCC_CSR_LSIRDY_Pos (1U)
1999 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
2000 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
2001 #define RCC_CSR_RMVF_Pos (24U)
2002 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
2003 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
2004 #define RCC_CSR_PINRSTF_Pos (26U)
2005 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
2006 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
2007 #define RCC_CSR_PORRSTF_Pos (27U)
2008 #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)
2009 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
2010 #define RCC_CSR_SFTRSTF_Pos (28U)
2011 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
2012 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
2013 #define RCC_CSR_IWDGRSTF_Pos (29U)
2014 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
2015 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
2016 #define RCC_CSR_WWDGRSTF_Pos (30U)
2017 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
2018 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
2019 #define RCC_CSR_LPWRRSTF_Pos (31U)
2020 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
2021 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
2023 /******************************************************************************/
2024 /* */
2025 /* General Purpose and Alternate Function I/O (GPIO) */
2026 /* */
2027 /******************************************************************************/
2028 
2029 /******************* Bit definition for GPIO_CRL register *******************/
2030 #define GPIO_CRL_MODE_Pos (0U)
2031 #define GPIO_CRL_MODE_Msk (0x33333333UL << GPIO_CRL_MODE_Pos)
2032 #define GPIO_CRL_MODE GPIO_CRL_MODE_Msk
2034 #define GPIO_CRL_MODE0_Pos (0U)
2035 #define GPIO_CRL_MODE0_Msk (0x3UL << GPIO_CRL_MODE0_Pos)
2036 #define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk
2037 #define GPIO_CRL_MODE0_0 (0x1UL << GPIO_CRL_MODE0_Pos)
2038 #define GPIO_CRL_MODE0_1 (0x2UL << GPIO_CRL_MODE0_Pos)
2040 #define GPIO_CRL_MODE1_Pos (4U)
2041 #define GPIO_CRL_MODE1_Msk (0x3UL << GPIO_CRL_MODE1_Pos)
2042 #define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk
2043 #define GPIO_CRL_MODE1_0 (0x1UL << GPIO_CRL_MODE1_Pos)
2044 #define GPIO_CRL_MODE1_1 (0x2UL << GPIO_CRL_MODE1_Pos)
2046 #define GPIO_CRL_MODE2_Pos (8U)
2047 #define GPIO_CRL_MODE2_Msk (0x3UL << GPIO_CRL_MODE2_Pos)
2048 #define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk
2049 #define GPIO_CRL_MODE2_0 (0x1UL << GPIO_CRL_MODE2_Pos)
2050 #define GPIO_CRL_MODE2_1 (0x2UL << GPIO_CRL_MODE2_Pos)
2052 #define GPIO_CRL_MODE3_Pos (12U)
2053 #define GPIO_CRL_MODE3_Msk (0x3UL << GPIO_CRL_MODE3_Pos)
2054 #define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk
2055 #define GPIO_CRL_MODE3_0 (0x1UL << GPIO_CRL_MODE3_Pos)
2056 #define GPIO_CRL_MODE3_1 (0x2UL << GPIO_CRL_MODE3_Pos)
2058 #define GPIO_CRL_MODE4_Pos (16U)
2059 #define GPIO_CRL_MODE4_Msk (0x3UL << GPIO_CRL_MODE4_Pos)
2060 #define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk
2061 #define GPIO_CRL_MODE4_0 (0x1UL << GPIO_CRL_MODE4_Pos)
2062 #define GPIO_CRL_MODE4_1 (0x2UL << GPIO_CRL_MODE4_Pos)
2064 #define GPIO_CRL_MODE5_Pos (20U)
2065 #define GPIO_CRL_MODE5_Msk (0x3UL << GPIO_CRL_MODE5_Pos)
2066 #define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk
2067 #define GPIO_CRL_MODE5_0 (0x1UL << GPIO_CRL_MODE5_Pos)
2068 #define GPIO_CRL_MODE5_1 (0x2UL << GPIO_CRL_MODE5_Pos)
2070 #define GPIO_CRL_MODE6_Pos (24U)
2071 #define GPIO_CRL_MODE6_Msk (0x3UL << GPIO_CRL_MODE6_Pos)
2072 #define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk
2073 #define GPIO_CRL_MODE6_0 (0x1UL << GPIO_CRL_MODE6_Pos)
2074 #define GPIO_CRL_MODE6_1 (0x2UL << GPIO_CRL_MODE6_Pos)
2076 #define GPIO_CRL_MODE7_Pos (28U)
2077 #define GPIO_CRL_MODE7_Msk (0x3UL << GPIO_CRL_MODE7_Pos)
2078 #define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk
2079 #define GPIO_CRL_MODE7_0 (0x1UL << GPIO_CRL_MODE7_Pos)
2080 #define GPIO_CRL_MODE7_1 (0x2UL << GPIO_CRL_MODE7_Pos)
2082 #define GPIO_CRL_CNF_Pos (2U)
2083 #define GPIO_CRL_CNF_Msk (0x33333333UL << GPIO_CRL_CNF_Pos)
2084 #define GPIO_CRL_CNF GPIO_CRL_CNF_Msk
2086 #define GPIO_CRL_CNF0_Pos (2U)
2087 #define GPIO_CRL_CNF0_Msk (0x3UL << GPIO_CRL_CNF0_Pos)
2088 #define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk
2089 #define GPIO_CRL_CNF0_0 (0x1UL << GPIO_CRL_CNF0_Pos)
2090 #define GPIO_CRL_CNF0_1 (0x2UL << GPIO_CRL_CNF0_Pos)
2092 #define GPIO_CRL_CNF1_Pos (6U)
2093 #define GPIO_CRL_CNF1_Msk (0x3UL << GPIO_CRL_CNF1_Pos)
2094 #define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk
2095 #define GPIO_CRL_CNF1_0 (0x1UL << GPIO_CRL_CNF1_Pos)
2096 #define GPIO_CRL_CNF1_1 (0x2UL << GPIO_CRL_CNF1_Pos)
2098 #define GPIO_CRL_CNF2_Pos (10U)
2099 #define GPIO_CRL_CNF2_Msk (0x3UL << GPIO_CRL_CNF2_Pos)
2100 #define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk
2101 #define GPIO_CRL_CNF2_0 (0x1UL << GPIO_CRL_CNF2_Pos)
2102 #define GPIO_CRL_CNF2_1 (0x2UL << GPIO_CRL_CNF2_Pos)
2104 #define GPIO_CRL_CNF3_Pos (14U)
2105 #define GPIO_CRL_CNF3_Msk (0x3UL << GPIO_CRL_CNF3_Pos)
2106 #define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk
2107 #define GPIO_CRL_CNF3_0 (0x1UL << GPIO_CRL_CNF3_Pos)
2108 #define GPIO_CRL_CNF3_1 (0x2UL << GPIO_CRL_CNF3_Pos)
2110 #define GPIO_CRL_CNF4_Pos (18U)
2111 #define GPIO_CRL_CNF4_Msk (0x3UL << GPIO_CRL_CNF4_Pos)
2112 #define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk
2113 #define GPIO_CRL_CNF4_0 (0x1UL << GPIO_CRL_CNF4_Pos)
2114 #define GPIO_CRL_CNF4_1 (0x2UL << GPIO_CRL_CNF4_Pos)
2116 #define GPIO_CRL_CNF5_Pos (22U)
2117 #define GPIO_CRL_CNF5_Msk (0x3UL << GPIO_CRL_CNF5_Pos)
2118 #define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk
2119 #define GPIO_CRL_CNF5_0 (0x1UL << GPIO_CRL_CNF5_Pos)
2120 #define GPIO_CRL_CNF5_1 (0x2UL << GPIO_CRL_CNF5_Pos)
2122 #define GPIO_CRL_CNF6_Pos (26U)
2123 #define GPIO_CRL_CNF6_Msk (0x3UL << GPIO_CRL_CNF6_Pos)
2124 #define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk
2125 #define GPIO_CRL_CNF6_0 (0x1UL << GPIO_CRL_CNF6_Pos)
2126 #define GPIO_CRL_CNF6_1 (0x2UL << GPIO_CRL_CNF6_Pos)
2128 #define GPIO_CRL_CNF7_Pos (30U)
2129 #define GPIO_CRL_CNF7_Msk (0x3UL << GPIO_CRL_CNF7_Pos)
2130 #define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk
2131 #define GPIO_CRL_CNF7_0 (0x1UL << GPIO_CRL_CNF7_Pos)
2132 #define GPIO_CRL_CNF7_1 (0x2UL << GPIO_CRL_CNF7_Pos)
2134 /******************* Bit definition for GPIO_CRH register *******************/
2135 #define GPIO_CRH_MODE_Pos (0U)
2136 #define GPIO_CRH_MODE_Msk (0x33333333UL << GPIO_CRH_MODE_Pos)
2137 #define GPIO_CRH_MODE GPIO_CRH_MODE_Msk
2139 #define GPIO_CRH_MODE8_Pos (0U)
2140 #define GPIO_CRH_MODE8_Msk (0x3UL << GPIO_CRH_MODE8_Pos)
2141 #define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk
2142 #define GPIO_CRH_MODE8_0 (0x1UL << GPIO_CRH_MODE8_Pos)
2143 #define GPIO_CRH_MODE8_1 (0x2UL << GPIO_CRH_MODE8_Pos)
2145 #define GPIO_CRH_MODE9_Pos (4U)
2146 #define GPIO_CRH_MODE9_Msk (0x3UL << GPIO_CRH_MODE9_Pos)
2147 #define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk
2148 #define GPIO_CRH_MODE9_0 (0x1UL << GPIO_CRH_MODE9_Pos)
2149 #define GPIO_CRH_MODE9_1 (0x2UL << GPIO_CRH_MODE9_Pos)
2151 #define GPIO_CRH_MODE10_Pos (8U)
2152 #define GPIO_CRH_MODE10_Msk (0x3UL << GPIO_CRH_MODE10_Pos)
2153 #define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk
2154 #define GPIO_CRH_MODE10_0 (0x1UL << GPIO_CRH_MODE10_Pos)
2155 #define GPIO_CRH_MODE10_1 (0x2UL << GPIO_CRH_MODE10_Pos)
2157 #define GPIO_CRH_MODE11_Pos (12U)
2158 #define GPIO_CRH_MODE11_Msk (0x3UL << GPIO_CRH_MODE11_Pos)
2159 #define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk
2160 #define GPIO_CRH_MODE11_0 (0x1UL << GPIO_CRH_MODE11_Pos)
2161 #define GPIO_CRH_MODE11_1 (0x2UL << GPIO_CRH_MODE11_Pos)
2163 #define GPIO_CRH_MODE12_Pos (16U)
2164 #define GPIO_CRH_MODE12_Msk (0x3UL << GPIO_CRH_MODE12_Pos)
2165 #define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk
2166 #define GPIO_CRH_MODE12_0 (0x1UL << GPIO_CRH_MODE12_Pos)
2167 #define GPIO_CRH_MODE12_1 (0x2UL << GPIO_CRH_MODE12_Pos)
2169 #define GPIO_CRH_MODE13_Pos (20U)
2170 #define GPIO_CRH_MODE13_Msk (0x3UL << GPIO_CRH_MODE13_Pos)
2171 #define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk
2172 #define GPIO_CRH_MODE13_0 (0x1UL << GPIO_CRH_MODE13_Pos)
2173 #define GPIO_CRH_MODE13_1 (0x2UL << GPIO_CRH_MODE13_Pos)
2175 #define GPIO_CRH_MODE14_Pos (24U)
2176 #define GPIO_CRH_MODE14_Msk (0x3UL << GPIO_CRH_MODE14_Pos)
2177 #define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk
2178 #define GPIO_CRH_MODE14_0 (0x1UL << GPIO_CRH_MODE14_Pos)
2179 #define GPIO_CRH_MODE14_1 (0x2UL << GPIO_CRH_MODE14_Pos)
2181 #define GPIO_CRH_MODE15_Pos (28U)
2182 #define GPIO_CRH_MODE15_Msk (0x3UL << GPIO_CRH_MODE15_Pos)
2183 #define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk
2184 #define GPIO_CRH_MODE15_0 (0x1UL << GPIO_CRH_MODE15_Pos)
2185 #define GPIO_CRH_MODE15_1 (0x2UL << GPIO_CRH_MODE15_Pos)
2187 #define GPIO_CRH_CNF_Pos (2U)
2188 #define GPIO_CRH_CNF_Msk (0x33333333UL << GPIO_CRH_CNF_Pos)
2189 #define GPIO_CRH_CNF GPIO_CRH_CNF_Msk
2191 #define GPIO_CRH_CNF8_Pos (2U)
2192 #define GPIO_CRH_CNF8_Msk (0x3UL << GPIO_CRH_CNF8_Pos)
2193 #define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk
2194 #define GPIO_CRH_CNF8_0 (0x1UL << GPIO_CRH_CNF8_Pos)
2195 #define GPIO_CRH_CNF8_1 (0x2UL << GPIO_CRH_CNF8_Pos)
2197 #define GPIO_CRH_CNF9_Pos (6U)
2198 #define GPIO_CRH_CNF9_Msk (0x3UL << GPIO_CRH_CNF9_Pos)
2199 #define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk
2200 #define GPIO_CRH_CNF9_0 (0x1UL << GPIO_CRH_CNF9_Pos)
2201 #define GPIO_CRH_CNF9_1 (0x2UL << GPIO_CRH_CNF9_Pos)
2203 #define GPIO_CRH_CNF10_Pos (10U)
2204 #define GPIO_CRH_CNF10_Msk (0x3UL << GPIO_CRH_CNF10_Pos)
2205 #define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk
2206 #define GPIO_CRH_CNF10_0 (0x1UL << GPIO_CRH_CNF10_Pos)
2207 #define GPIO_CRH_CNF10_1 (0x2UL << GPIO_CRH_CNF10_Pos)
2209 #define GPIO_CRH_CNF11_Pos (14U)
2210 #define GPIO_CRH_CNF11_Msk (0x3UL << GPIO_CRH_CNF11_Pos)
2211 #define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk
2212 #define GPIO_CRH_CNF11_0 (0x1UL << GPIO_CRH_CNF11_Pos)
2213 #define GPIO_CRH_CNF11_1 (0x2UL << GPIO_CRH_CNF11_Pos)
2215 #define GPIO_CRH_CNF12_Pos (18U)
2216 #define GPIO_CRH_CNF12_Msk (0x3UL << GPIO_CRH_CNF12_Pos)
2217 #define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk
2218 #define GPIO_CRH_CNF12_0 (0x1UL << GPIO_CRH_CNF12_Pos)
2219 #define GPIO_CRH_CNF12_1 (0x2UL << GPIO_CRH_CNF12_Pos)
2221 #define GPIO_CRH_CNF13_Pos (22U)
2222 #define GPIO_CRH_CNF13_Msk (0x3UL << GPIO_CRH_CNF13_Pos)
2223 #define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk
2224 #define GPIO_CRH_CNF13_0 (0x1UL << GPIO_CRH_CNF13_Pos)
2225 #define GPIO_CRH_CNF13_1 (0x2UL << GPIO_CRH_CNF13_Pos)
2227 #define GPIO_CRH_CNF14_Pos (26U)
2228 #define GPIO_CRH_CNF14_Msk (0x3UL << GPIO_CRH_CNF14_Pos)
2229 #define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk
2230 #define GPIO_CRH_CNF14_0 (0x1UL << GPIO_CRH_CNF14_Pos)
2231 #define GPIO_CRH_CNF14_1 (0x2UL << GPIO_CRH_CNF14_Pos)
2233 #define GPIO_CRH_CNF15_Pos (30U)
2234 #define GPIO_CRH_CNF15_Msk (0x3UL << GPIO_CRH_CNF15_Pos)
2235 #define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk
2236 #define GPIO_CRH_CNF15_0 (0x1UL << GPIO_CRH_CNF15_Pos)
2237 #define GPIO_CRH_CNF15_1 (0x2UL << GPIO_CRH_CNF15_Pos)
2240 #define GPIO_IDR_IDR0_Pos (0U)
2241 #define GPIO_IDR_IDR0_Msk (0x1UL << GPIO_IDR_IDR0_Pos)
2242 #define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk
2243 #define GPIO_IDR_IDR1_Pos (1U)
2244 #define GPIO_IDR_IDR1_Msk (0x1UL << GPIO_IDR_IDR1_Pos)
2245 #define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk
2246 #define GPIO_IDR_IDR2_Pos (2U)
2247 #define GPIO_IDR_IDR2_Msk (0x1UL << GPIO_IDR_IDR2_Pos)
2248 #define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk
2249 #define GPIO_IDR_IDR3_Pos (3U)
2250 #define GPIO_IDR_IDR3_Msk (0x1UL << GPIO_IDR_IDR3_Pos)
2251 #define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk
2252 #define GPIO_IDR_IDR4_Pos (4U)
2253 #define GPIO_IDR_IDR4_Msk (0x1UL << GPIO_IDR_IDR4_Pos)
2254 #define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk
2255 #define GPIO_IDR_IDR5_Pos (5U)
2256 #define GPIO_IDR_IDR5_Msk (0x1UL << GPIO_IDR_IDR5_Pos)
2257 #define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk
2258 #define GPIO_IDR_IDR6_Pos (6U)
2259 #define GPIO_IDR_IDR6_Msk (0x1UL << GPIO_IDR_IDR6_Pos)
2260 #define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk
2261 #define GPIO_IDR_IDR7_Pos (7U)
2262 #define GPIO_IDR_IDR7_Msk (0x1UL << GPIO_IDR_IDR7_Pos)
2263 #define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk
2264 #define GPIO_IDR_IDR8_Pos (8U)
2265 #define GPIO_IDR_IDR8_Msk (0x1UL << GPIO_IDR_IDR8_Pos)
2266 #define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk
2267 #define GPIO_IDR_IDR9_Pos (9U)
2268 #define GPIO_IDR_IDR9_Msk (0x1UL << GPIO_IDR_IDR9_Pos)
2269 #define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk
2270 #define GPIO_IDR_IDR10_Pos (10U)
2271 #define GPIO_IDR_IDR10_Msk (0x1UL << GPIO_IDR_IDR10_Pos)
2272 #define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk
2273 #define GPIO_IDR_IDR11_Pos (11U)
2274 #define GPIO_IDR_IDR11_Msk (0x1UL << GPIO_IDR_IDR11_Pos)
2275 #define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk
2276 #define GPIO_IDR_IDR12_Pos (12U)
2277 #define GPIO_IDR_IDR12_Msk (0x1UL << GPIO_IDR_IDR12_Pos)
2278 #define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk
2279 #define GPIO_IDR_IDR13_Pos (13U)
2280 #define GPIO_IDR_IDR13_Msk (0x1UL << GPIO_IDR_IDR13_Pos)
2281 #define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk
2282 #define GPIO_IDR_IDR14_Pos (14U)
2283 #define GPIO_IDR_IDR14_Msk (0x1UL << GPIO_IDR_IDR14_Pos)
2284 #define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk
2285 #define GPIO_IDR_IDR15_Pos (15U)
2286 #define GPIO_IDR_IDR15_Msk (0x1UL << GPIO_IDR_IDR15_Pos)
2287 #define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk
2289 /******************* Bit definition for GPIO_ODR register *******************/
2290 #define GPIO_ODR_ODR0_Pos (0U)
2291 #define GPIO_ODR_ODR0_Msk (0x1UL << GPIO_ODR_ODR0_Pos)
2292 #define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk
2293 #define GPIO_ODR_ODR1_Pos (1U)
2294 #define GPIO_ODR_ODR1_Msk (0x1UL << GPIO_ODR_ODR1_Pos)
2295 #define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk
2296 #define GPIO_ODR_ODR2_Pos (2U)
2297 #define GPIO_ODR_ODR2_Msk (0x1UL << GPIO_ODR_ODR2_Pos)
2298 #define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk
2299 #define GPIO_ODR_ODR3_Pos (3U)
2300 #define GPIO_ODR_ODR3_Msk (0x1UL << GPIO_ODR_ODR3_Pos)
2301 #define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk
2302 #define GPIO_ODR_ODR4_Pos (4U)
2303 #define GPIO_ODR_ODR4_Msk (0x1UL << GPIO_ODR_ODR4_Pos)
2304 #define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk
2305 #define GPIO_ODR_ODR5_Pos (5U)
2306 #define GPIO_ODR_ODR5_Msk (0x1UL << GPIO_ODR_ODR5_Pos)
2307 #define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk
2308 #define GPIO_ODR_ODR6_Pos (6U)
2309 #define GPIO_ODR_ODR6_Msk (0x1UL << GPIO_ODR_ODR6_Pos)
2310 #define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk
2311 #define GPIO_ODR_ODR7_Pos (7U)
2312 #define GPIO_ODR_ODR7_Msk (0x1UL << GPIO_ODR_ODR7_Pos)
2313 #define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk
2314 #define GPIO_ODR_ODR8_Pos (8U)
2315 #define GPIO_ODR_ODR8_Msk (0x1UL << GPIO_ODR_ODR8_Pos)
2316 #define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk
2317 #define GPIO_ODR_ODR9_Pos (9U)
2318 #define GPIO_ODR_ODR9_Msk (0x1UL << GPIO_ODR_ODR9_Pos)
2319 #define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk
2320 #define GPIO_ODR_ODR10_Pos (10U)
2321 #define GPIO_ODR_ODR10_Msk (0x1UL << GPIO_ODR_ODR10_Pos)
2322 #define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk
2323 #define GPIO_ODR_ODR11_Pos (11U)
2324 #define GPIO_ODR_ODR11_Msk (0x1UL << GPIO_ODR_ODR11_Pos)
2325 #define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk
2326 #define GPIO_ODR_ODR12_Pos (12U)
2327 #define GPIO_ODR_ODR12_Msk (0x1UL << GPIO_ODR_ODR12_Pos)
2328 #define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk
2329 #define GPIO_ODR_ODR13_Pos (13U)
2330 #define GPIO_ODR_ODR13_Msk (0x1UL << GPIO_ODR_ODR13_Pos)
2331 #define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk
2332 #define GPIO_ODR_ODR14_Pos (14U)
2333 #define GPIO_ODR_ODR14_Msk (0x1UL << GPIO_ODR_ODR14_Pos)
2334 #define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk
2335 #define GPIO_ODR_ODR15_Pos (15U)
2336 #define GPIO_ODR_ODR15_Msk (0x1UL << GPIO_ODR_ODR15_Pos)
2337 #define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk
2339 /****************** Bit definition for GPIO_BSRR register *******************/
2340 #define GPIO_BSRR_BS0_Pos (0U)
2341 #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
2342 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
2343 #define GPIO_BSRR_BS1_Pos (1U)
2344 #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
2345 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
2346 #define GPIO_BSRR_BS2_Pos (2U)
2347 #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
2348 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
2349 #define GPIO_BSRR_BS3_Pos (3U)
2350 #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
2351 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
2352 #define GPIO_BSRR_BS4_Pos (4U)
2353 #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
2354 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
2355 #define GPIO_BSRR_BS5_Pos (5U)
2356 #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
2357 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
2358 #define GPIO_BSRR_BS6_Pos (6U)
2359 #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
2360 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
2361 #define GPIO_BSRR_BS7_Pos (7U)
2362 #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
2363 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
2364 #define GPIO_BSRR_BS8_Pos (8U)
2365 #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
2366 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
2367 #define GPIO_BSRR_BS9_Pos (9U)
2368 #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
2369 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
2370 #define GPIO_BSRR_BS10_Pos (10U)
2371 #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
2372 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
2373 #define GPIO_BSRR_BS11_Pos (11U)
2374 #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
2375 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
2376 #define GPIO_BSRR_BS12_Pos (12U)
2377 #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
2378 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
2379 #define GPIO_BSRR_BS13_Pos (13U)
2380 #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
2381 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
2382 #define GPIO_BSRR_BS14_Pos (14U)
2383 #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
2384 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
2385 #define GPIO_BSRR_BS15_Pos (15U)
2386 #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
2387 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
2389 #define GPIO_BSRR_BR0_Pos (16U)
2390 #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
2391 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
2392 #define GPIO_BSRR_BR1_Pos (17U)
2393 #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
2394 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
2395 #define GPIO_BSRR_BR2_Pos (18U)
2396 #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
2397 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
2398 #define GPIO_BSRR_BR3_Pos (19U)
2399 #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
2400 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
2401 #define GPIO_BSRR_BR4_Pos (20U)
2402 #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
2403 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
2404 #define GPIO_BSRR_BR5_Pos (21U)
2405 #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
2406 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
2407 #define GPIO_BSRR_BR6_Pos (22U)
2408 #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
2409 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
2410 #define GPIO_BSRR_BR7_Pos (23U)
2411 #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
2412 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
2413 #define GPIO_BSRR_BR8_Pos (24U)
2414 #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
2415 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
2416 #define GPIO_BSRR_BR9_Pos (25U)
2417 #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
2418 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
2419 #define GPIO_BSRR_BR10_Pos (26U)
2420 #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
2421 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
2422 #define GPIO_BSRR_BR11_Pos (27U)
2423 #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
2424 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
2425 #define GPIO_BSRR_BR12_Pos (28U)
2426 #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
2427 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
2428 #define GPIO_BSRR_BR13_Pos (29U)
2429 #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
2430 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
2431 #define GPIO_BSRR_BR14_Pos (30U)
2432 #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
2433 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
2434 #define GPIO_BSRR_BR15_Pos (31U)
2435 #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
2436 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
2438 /******************* Bit definition for GPIO_BRR register *******************/
2439 #define GPIO_BRR_BR0_Pos (0U)
2440 #define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos)
2441 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
2442 #define GPIO_BRR_BR1_Pos (1U)
2443 #define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos)
2444 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
2445 #define GPIO_BRR_BR2_Pos (2U)
2446 #define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos)
2447 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
2448 #define GPIO_BRR_BR3_Pos (3U)
2449 #define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos)
2450 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
2451 #define GPIO_BRR_BR4_Pos (4U)
2452 #define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos)
2453 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
2454 #define GPIO_BRR_BR5_Pos (5U)
2455 #define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos)
2456 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
2457 #define GPIO_BRR_BR6_Pos (6U)
2458 #define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos)
2459 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
2460 #define GPIO_BRR_BR7_Pos (7U)
2461 #define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos)
2462 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
2463 #define GPIO_BRR_BR8_Pos (8U)
2464 #define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos)
2465 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
2466 #define GPIO_BRR_BR9_Pos (9U)
2467 #define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos)
2468 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
2469 #define GPIO_BRR_BR10_Pos (10U)
2470 #define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos)
2471 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
2472 #define GPIO_BRR_BR11_Pos (11U)
2473 #define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos)
2474 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
2475 #define GPIO_BRR_BR12_Pos (12U)
2476 #define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos)
2477 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
2478 #define GPIO_BRR_BR13_Pos (13U)
2479 #define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos)
2480 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
2481 #define GPIO_BRR_BR14_Pos (14U)
2482 #define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos)
2483 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
2484 #define GPIO_BRR_BR15_Pos (15U)
2485 #define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos)
2486 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
2488 /****************** Bit definition for GPIO_LCKR register *******************/
2489 #define GPIO_LCKR_LCK0_Pos (0U)
2490 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
2491 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
2492 #define GPIO_LCKR_LCK1_Pos (1U)
2493 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
2494 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
2495 #define GPIO_LCKR_LCK2_Pos (2U)
2496 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
2497 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
2498 #define GPIO_LCKR_LCK3_Pos (3U)
2499 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
2500 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
2501 #define GPIO_LCKR_LCK4_Pos (4U)
2502 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
2503 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
2504 #define GPIO_LCKR_LCK5_Pos (5U)
2505 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
2506 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
2507 #define GPIO_LCKR_LCK6_Pos (6U)
2508 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
2509 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
2510 #define GPIO_LCKR_LCK7_Pos (7U)
2511 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
2512 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
2513 #define GPIO_LCKR_LCK8_Pos (8U)
2514 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
2515 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
2516 #define GPIO_LCKR_LCK9_Pos (9U)
2517 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
2518 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
2519 #define GPIO_LCKR_LCK10_Pos (10U)
2520 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
2521 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
2522 #define GPIO_LCKR_LCK11_Pos (11U)
2523 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
2524 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
2525 #define GPIO_LCKR_LCK12_Pos (12U)
2526 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
2527 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
2528 #define GPIO_LCKR_LCK13_Pos (13U)
2529 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
2530 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
2531 #define GPIO_LCKR_LCK14_Pos (14U)
2532 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
2533 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
2534 #define GPIO_LCKR_LCK15_Pos (15U)
2535 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
2536 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
2537 #define GPIO_LCKR_LCKK_Pos (16U)
2538 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
2539 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
2541 /****************** Bit definition for AFIO_EVCR register *******************/
2542 #define AFIO_EVCR_PIN_Pos (0U)
2543 #define AFIO_EVCR_PIN_Msk (0xFUL << AFIO_EVCR_PIN_Pos)
2544 #define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk
2545 #define AFIO_EVCR_PIN_0 (0x1UL << AFIO_EVCR_PIN_Pos)
2546 #define AFIO_EVCR_PIN_1 (0x2UL << AFIO_EVCR_PIN_Pos)
2547 #define AFIO_EVCR_PIN_2 (0x4UL << AFIO_EVCR_PIN_Pos)
2548 #define AFIO_EVCR_PIN_3 (0x8UL << AFIO_EVCR_PIN_Pos)
2551 #define AFIO_EVCR_PIN_PX0 0x00000000U
2552 #define AFIO_EVCR_PIN_PX1_Pos (0U)
2553 #define AFIO_EVCR_PIN_PX1_Msk (0x1UL << AFIO_EVCR_PIN_PX1_Pos)
2554 #define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk
2555 #define AFIO_EVCR_PIN_PX2_Pos (1U)
2556 #define AFIO_EVCR_PIN_PX2_Msk (0x1UL << AFIO_EVCR_PIN_PX2_Pos)
2557 #define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk
2558 #define AFIO_EVCR_PIN_PX3_Pos (0U)
2559 #define AFIO_EVCR_PIN_PX3_Msk (0x3UL << AFIO_EVCR_PIN_PX3_Pos)
2560 #define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk
2561 #define AFIO_EVCR_PIN_PX4_Pos (2U)
2562 #define AFIO_EVCR_PIN_PX4_Msk (0x1UL << AFIO_EVCR_PIN_PX4_Pos)
2563 #define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk
2564 #define AFIO_EVCR_PIN_PX5_Pos (0U)
2565 #define AFIO_EVCR_PIN_PX5_Msk (0x5UL << AFIO_EVCR_PIN_PX5_Pos)
2566 #define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk
2567 #define AFIO_EVCR_PIN_PX6_Pos (1U)
2568 #define AFIO_EVCR_PIN_PX6_Msk (0x3UL << AFIO_EVCR_PIN_PX6_Pos)
2569 #define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk
2570 #define AFIO_EVCR_PIN_PX7_Pos (0U)
2571 #define AFIO_EVCR_PIN_PX7_Msk (0x7UL << AFIO_EVCR_PIN_PX7_Pos)
2572 #define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk
2573 #define AFIO_EVCR_PIN_PX8_Pos (3U)
2574 #define AFIO_EVCR_PIN_PX8_Msk (0x1UL << AFIO_EVCR_PIN_PX8_Pos)
2575 #define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk
2576 #define AFIO_EVCR_PIN_PX9_Pos (0U)
2577 #define AFIO_EVCR_PIN_PX9_Msk (0x9UL << AFIO_EVCR_PIN_PX9_Pos)
2578 #define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk
2579 #define AFIO_EVCR_PIN_PX10_Pos (1U)
2580 #define AFIO_EVCR_PIN_PX10_Msk (0x5UL << AFIO_EVCR_PIN_PX10_Pos)
2581 #define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk
2582 #define AFIO_EVCR_PIN_PX11_Pos (0U)
2583 #define AFIO_EVCR_PIN_PX11_Msk (0xBUL << AFIO_EVCR_PIN_PX11_Pos)
2584 #define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk
2585 #define AFIO_EVCR_PIN_PX12_Pos (2U)
2586 #define AFIO_EVCR_PIN_PX12_Msk (0x3UL << AFIO_EVCR_PIN_PX12_Pos)
2587 #define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk
2588 #define AFIO_EVCR_PIN_PX13_Pos (0U)
2589 #define AFIO_EVCR_PIN_PX13_Msk (0xDUL << AFIO_EVCR_PIN_PX13_Pos)
2590 #define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk
2591 #define AFIO_EVCR_PIN_PX14_Pos (1U)
2592 #define AFIO_EVCR_PIN_PX14_Msk (0x7UL << AFIO_EVCR_PIN_PX14_Pos)
2593 #define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk
2594 #define AFIO_EVCR_PIN_PX15_Pos (0U)
2595 #define AFIO_EVCR_PIN_PX15_Msk (0xFUL << AFIO_EVCR_PIN_PX15_Pos)
2596 #define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk
2598 #define AFIO_EVCR_PORT_Pos (4U)
2599 #define AFIO_EVCR_PORT_Msk (0x7UL << AFIO_EVCR_PORT_Pos)
2600 #define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk
2601 #define AFIO_EVCR_PORT_0 (0x1UL << AFIO_EVCR_PORT_Pos)
2602 #define AFIO_EVCR_PORT_1 (0x2UL << AFIO_EVCR_PORT_Pos)
2603 #define AFIO_EVCR_PORT_2 (0x4UL << AFIO_EVCR_PORT_Pos)
2606 #define AFIO_EVCR_PORT_PA 0x00000000
2607 #define AFIO_EVCR_PORT_PB_Pos (4U)
2608 #define AFIO_EVCR_PORT_PB_Msk (0x1UL << AFIO_EVCR_PORT_PB_Pos)
2609 #define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk
2610 #define AFIO_EVCR_PORT_PC_Pos (5U)
2611 #define AFIO_EVCR_PORT_PC_Msk (0x1UL << AFIO_EVCR_PORT_PC_Pos)
2612 #define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk
2613 #define AFIO_EVCR_PORT_PD_Pos (4U)
2614 #define AFIO_EVCR_PORT_PD_Msk (0x3UL << AFIO_EVCR_PORT_PD_Pos)
2615 #define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk
2616 #define AFIO_EVCR_PORT_PE_Pos (6U)
2617 #define AFIO_EVCR_PORT_PE_Msk (0x1UL << AFIO_EVCR_PORT_PE_Pos)
2618 #define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk
2620 #define AFIO_EVCR_EVOE_Pos (7U)
2621 #define AFIO_EVCR_EVOE_Msk (0x1UL << AFIO_EVCR_EVOE_Pos)
2622 #define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk
2624 /****************** Bit definition for AFIO_MAPR register *******************/
2625 #define AFIO_MAPR_SPI1_REMAP_Pos (0U)
2626 #define AFIO_MAPR_SPI1_REMAP_Msk (0x1UL << AFIO_MAPR_SPI1_REMAP_Pos)
2627 #define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk
2628 #define AFIO_MAPR_I2C1_REMAP_Pos (1U)
2629 #define AFIO_MAPR_I2C1_REMAP_Msk (0x1UL << AFIO_MAPR_I2C1_REMAP_Pos)
2630 #define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk
2631 #define AFIO_MAPR_USART1_REMAP_Pos (2U)
2632 #define AFIO_MAPR_USART1_REMAP_Msk (0x1UL << AFIO_MAPR_USART1_REMAP_Pos)
2633 #define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk
2634 #define AFIO_MAPR_USART2_REMAP_Pos (3U)
2635 #define AFIO_MAPR_USART2_REMAP_Msk (0x1UL << AFIO_MAPR_USART2_REMAP_Pos)
2636 #define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk
2638 #define AFIO_MAPR_USART3_REMAP_Pos (4U)
2639 #define AFIO_MAPR_USART3_REMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_Pos)
2640 #define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk
2641 #define AFIO_MAPR_USART3_REMAP_0 (0x1UL << AFIO_MAPR_USART3_REMAP_Pos)
2642 #define AFIO_MAPR_USART3_REMAP_1 (0x2UL << AFIO_MAPR_USART3_REMAP_Pos)
2644 /* USART3_REMAP configuration */
2645 #define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U
2646 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
2647 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos)
2648 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk
2649 #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
2650 #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos)
2651 #define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk
2653 #define AFIO_MAPR_TIM1_REMAP_Pos (6U)
2654 #define AFIO_MAPR_TIM1_REMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_Pos)
2655 #define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk
2656 #define AFIO_MAPR_TIM1_REMAP_0 (0x1UL << AFIO_MAPR_TIM1_REMAP_Pos)
2657 #define AFIO_MAPR_TIM1_REMAP_1 (0x2UL << AFIO_MAPR_TIM1_REMAP_Pos)
2660 #define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U
2661 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
2662 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos)
2663 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk
2664 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
2665 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos)
2666 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk
2668 #define AFIO_MAPR_TIM2_REMAP_Pos (8U)
2669 #define AFIO_MAPR_TIM2_REMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_Pos)
2670 #define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk
2671 #define AFIO_MAPR_TIM2_REMAP_0 (0x1UL << AFIO_MAPR_TIM2_REMAP_Pos)
2672 #define AFIO_MAPR_TIM2_REMAP_1 (0x2UL << AFIO_MAPR_TIM2_REMAP_Pos)
2675 #define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U
2676 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
2677 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos)
2678 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk
2679 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
2680 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos)
2681 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk
2682 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
2683 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos)
2684 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk
2686 #define AFIO_MAPR_TIM3_REMAP_Pos (10U)
2687 #define AFIO_MAPR_TIM3_REMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_Pos)
2688 #define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk
2689 #define AFIO_MAPR_TIM3_REMAP_0 (0x1UL << AFIO_MAPR_TIM3_REMAP_Pos)
2690 #define AFIO_MAPR_TIM3_REMAP_1 (0x2UL << AFIO_MAPR_TIM3_REMAP_Pos)
2693 #define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U
2694 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
2695 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos)
2696 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk
2697 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
2698 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos)
2699 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk
2701 #define AFIO_MAPR_TIM4_REMAP_Pos (12U)
2702 #define AFIO_MAPR_TIM4_REMAP_Msk (0x1UL << AFIO_MAPR_TIM4_REMAP_Pos)
2703 #define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk
2705 #define AFIO_MAPR_CAN_REMAP_Pos (13U)
2706 #define AFIO_MAPR_CAN_REMAP_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_Pos)
2707 #define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk
2708 #define AFIO_MAPR_CAN_REMAP_0 (0x1UL << AFIO_MAPR_CAN_REMAP_Pos)
2709 #define AFIO_MAPR_CAN_REMAP_1 (0x2UL << AFIO_MAPR_CAN_REMAP_Pos)
2712 #define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U
2713 #define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U)
2714 #define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1UL << AFIO_MAPR_CAN_REMAP_REMAP2_Pos)
2715 #define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk
2716 #define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U)
2717 #define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_REMAP3_Pos)
2718 #define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk
2720 #define AFIO_MAPR_PD01_REMAP_Pos (15U)
2721 #define AFIO_MAPR_PD01_REMAP_Msk (0x1UL << AFIO_MAPR_PD01_REMAP_Pos)
2722 #define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk
2723 #define AFIO_MAPR_TIM5CH4_IREMAP_Pos (16U)
2724 #define AFIO_MAPR_TIM5CH4_IREMAP_Msk (0x1UL << AFIO_MAPR_TIM5CH4_IREMAP_Pos)
2725 #define AFIO_MAPR_TIM5CH4_IREMAP AFIO_MAPR_TIM5CH4_IREMAP_Msk
2726 #define AFIO_MAPR_ADC1_ETRGINJ_REMAP_Pos (17U)
2727 #define AFIO_MAPR_ADC1_ETRGINJ_REMAP_Msk (0x1UL << AFIO_MAPR_ADC1_ETRGINJ_REMAP_Pos)
2728 #define AFIO_MAPR_ADC1_ETRGINJ_REMAP AFIO_MAPR_ADC1_ETRGINJ_REMAP_Msk
2729 #define AFIO_MAPR_ADC1_ETRGREG_REMAP_Pos (18U)
2730 #define AFIO_MAPR_ADC1_ETRGREG_REMAP_Msk (0x1UL << AFIO_MAPR_ADC1_ETRGREG_REMAP_Pos)
2731 #define AFIO_MAPR_ADC1_ETRGREG_REMAP AFIO_MAPR_ADC1_ETRGREG_REMAP_Msk
2732 #define AFIO_MAPR_ADC2_ETRGINJ_REMAP_Pos (19U)
2733 #define AFIO_MAPR_ADC2_ETRGINJ_REMAP_Msk (0x1UL << AFIO_MAPR_ADC2_ETRGINJ_REMAP_Pos)
2734 #define AFIO_MAPR_ADC2_ETRGINJ_REMAP AFIO_MAPR_ADC2_ETRGINJ_REMAP_Msk
2735 #define AFIO_MAPR_ADC2_ETRGREG_REMAP_Pos (20U)
2736 #define AFIO_MAPR_ADC2_ETRGREG_REMAP_Msk (0x1UL << AFIO_MAPR_ADC2_ETRGREG_REMAP_Pos)
2737 #define AFIO_MAPR_ADC2_ETRGREG_REMAP AFIO_MAPR_ADC2_ETRGREG_REMAP_Msk
2738 #define AFIO_MAPR_QUADSPI_REMAP_Pos (21U)
2739 #define AFIO_MAPR_QUADSPI_REMAP_Msk (0x1U << AFIO_MAPR_QUADSPI_REMAP_Pos)
2740 #define AFIO_MAPR_QUADSPI_REMAP AFIO_MAPR_QUADSPI_REMAP_Msk
2743 #define AFIO_MAPR_SWJ_CFG_Pos (24U)
2744 #define AFIO_MAPR_SWJ_CFG_Msk (0x7UL << AFIO_MAPR_SWJ_CFG_Pos)
2745 #define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk
2746 #define AFIO_MAPR_SWJ_CFG_0 (0x1UL << AFIO_MAPR_SWJ_CFG_Pos)
2747 #define AFIO_MAPR_SWJ_CFG_1 (0x2UL << AFIO_MAPR_SWJ_CFG_Pos)
2748 #define AFIO_MAPR_SWJ_CFG_2 (0x4UL << AFIO_MAPR_SWJ_CFG_Pos)
2750 #define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U
2751 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
2752 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos)
2753 #define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk
2754 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
2755 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos)
2756 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk
2757 #define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
2758 #define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_DISABLE_Pos)
2759 #define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk
2761 /***************** Bit definition for AFIO_EXTICR1 register *****************/
2762 #define AFIO_EXTICR1_EXTI0_Pos (0U)
2763 #define AFIO_EXTICR1_EXTI0_Msk (0xFUL << AFIO_EXTICR1_EXTI0_Pos)
2764 #define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk
2765 #define AFIO_EXTICR1_EXTI1_Pos (4U)
2766 #define AFIO_EXTICR1_EXTI1_Msk (0xFUL << AFIO_EXTICR1_EXTI1_Pos)
2767 #define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk
2768 #define AFIO_EXTICR1_EXTI2_Pos (8U)
2769 #define AFIO_EXTICR1_EXTI2_Msk (0xFUL << AFIO_EXTICR1_EXTI2_Pos)
2770 #define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk
2771 #define AFIO_EXTICR1_EXTI3_Pos (12U)
2772 #define AFIO_EXTICR1_EXTI3_Msk (0xFUL << AFIO_EXTICR1_EXTI3_Pos)
2773 #define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk
2776 #define AFIO_EXTICR1_EXTI0_PA 0x00000000U
2777 #define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
2778 #define AFIO_EXTICR1_EXTI0_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PB_Pos)
2779 #define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk
2780 #define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
2781 #define AFIO_EXTICR1_EXTI0_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PC_Pos)
2782 #define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk
2783 #define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
2784 #define AFIO_EXTICR1_EXTI0_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PD_Pos)
2785 #define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk
2786 #define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
2787 #define AFIO_EXTICR1_EXTI0_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PE_Pos)
2788 #define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk
2789 #define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
2790 #define AFIO_EXTICR1_EXTI0_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI0_PF_Pos)
2791 #define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk
2792 #define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
2793 #define AFIO_EXTICR1_EXTI0_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PG_Pos)
2794 #define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk
2797 #define AFIO_EXTICR1_EXTI1_PA 0x00000000U
2798 #define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
2799 #define AFIO_EXTICR1_EXTI1_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PB_Pos)
2800 #define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk
2801 #define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
2802 #define AFIO_EXTICR1_EXTI1_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PC_Pos)
2803 #define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk
2804 #define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
2805 #define AFIO_EXTICR1_EXTI1_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PD_Pos)
2806 #define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk
2807 #define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
2808 #define AFIO_EXTICR1_EXTI1_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PE_Pos)
2809 #define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk
2810 #define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
2811 #define AFIO_EXTICR1_EXTI1_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI1_PF_Pos)
2812 #define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk
2813 #define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
2814 #define AFIO_EXTICR1_EXTI1_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PG_Pos)
2815 #define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk
2818 #define AFIO_EXTICR1_EXTI2_PA 0x00000000U
2819 #define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
2820 #define AFIO_EXTICR1_EXTI2_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PB_Pos)
2821 #define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk
2822 #define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
2823 #define AFIO_EXTICR1_EXTI2_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PC_Pos)
2824 #define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk
2825 #define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
2826 #define AFIO_EXTICR1_EXTI2_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PD_Pos)
2827 #define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk
2828 #define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
2829 #define AFIO_EXTICR1_EXTI2_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PE_Pos)
2830 #define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk
2831 #define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
2832 #define AFIO_EXTICR1_EXTI2_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI2_PF_Pos)
2833 #define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk
2834 #define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
2835 #define AFIO_EXTICR1_EXTI2_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PG_Pos)
2836 #define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk
2839 #define AFIO_EXTICR1_EXTI3_PA 0x00000000U
2840 #define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
2841 #define AFIO_EXTICR1_EXTI3_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PB_Pos)
2842 #define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk
2843 #define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
2844 #define AFIO_EXTICR1_EXTI3_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PC_Pos)
2845 #define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk
2846 #define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
2847 #define AFIO_EXTICR1_EXTI3_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PD_Pos)
2848 #define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk
2849 #define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
2850 #define AFIO_EXTICR1_EXTI3_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PE_Pos)
2851 #define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk
2852 #define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
2853 #define AFIO_EXTICR1_EXTI3_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI3_PF_Pos)
2854 #define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk
2855 #define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
2856 #define AFIO_EXTICR1_EXTI3_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PG_Pos)
2857 #define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk
2859 /***************** Bit definition for AFIO_EXTICR2 register *****************/
2860 #define AFIO_EXTICR2_EXTI4_Pos (0U)
2861 #define AFIO_EXTICR2_EXTI4_Msk (0xFUL << AFIO_EXTICR2_EXTI4_Pos)
2862 #define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk
2863 #define AFIO_EXTICR2_EXTI5_Pos (4U)
2864 #define AFIO_EXTICR2_EXTI5_Msk (0xFUL << AFIO_EXTICR2_EXTI5_Pos)
2865 #define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk
2866 #define AFIO_EXTICR2_EXTI6_Pos (8U)
2867 #define AFIO_EXTICR2_EXTI6_Msk (0xFUL << AFIO_EXTICR2_EXTI6_Pos)
2868 #define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk
2869 #define AFIO_EXTICR2_EXTI7_Pos (12U)
2870 #define AFIO_EXTICR2_EXTI7_Msk (0xFUL << AFIO_EXTICR2_EXTI7_Pos)
2871 #define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk
2874 #define AFIO_EXTICR2_EXTI4_PA 0x00000000U
2875 #define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
2876 #define AFIO_EXTICR2_EXTI4_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PB_Pos)
2877 #define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk
2878 #define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
2879 #define AFIO_EXTICR2_EXTI4_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PC_Pos)
2880 #define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk
2881 #define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
2882 #define AFIO_EXTICR2_EXTI4_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PD_Pos)
2883 #define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk
2884 #define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
2885 #define AFIO_EXTICR2_EXTI4_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PE_Pos)
2886 #define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk
2887 #define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
2888 #define AFIO_EXTICR2_EXTI4_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI4_PF_Pos)
2889 #define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk
2890 #define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
2891 #define AFIO_EXTICR2_EXTI4_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PG_Pos)
2892 #define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk
2894 /* EXTI5 configuration */
2895 #define AFIO_EXTICR2_EXTI5_PA 0x00000000U
2896 #define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
2897 #define AFIO_EXTICR2_EXTI5_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PB_Pos)
2898 #define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk
2899 #define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
2900 #define AFIO_EXTICR2_EXTI5_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PC_Pos)
2901 #define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk
2902 #define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
2903 #define AFIO_EXTICR2_EXTI5_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PD_Pos)
2904 #define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk
2905 #define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
2906 #define AFIO_EXTICR2_EXTI5_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PE_Pos)
2907 #define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk
2908 #define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
2909 #define AFIO_EXTICR2_EXTI5_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI5_PF_Pos)
2910 #define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk
2911 #define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
2912 #define AFIO_EXTICR2_EXTI5_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PG_Pos)
2913 #define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk
2916 #define AFIO_EXTICR2_EXTI6_PA 0x00000000U
2917 #define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
2918 #define AFIO_EXTICR2_EXTI6_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PB_Pos)
2919 #define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk
2920 #define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
2921 #define AFIO_EXTICR2_EXTI6_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PC_Pos)
2922 #define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk
2923 #define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
2924 #define AFIO_EXTICR2_EXTI6_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PD_Pos)
2925 #define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk
2926 #define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
2927 #define AFIO_EXTICR2_EXTI6_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PE_Pos)
2928 #define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk
2929 #define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
2930 #define AFIO_EXTICR2_EXTI6_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI6_PF_Pos)
2931 #define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk
2932 #define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
2933 #define AFIO_EXTICR2_EXTI6_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PG_Pos)
2934 #define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk
2937 #define AFIO_EXTICR2_EXTI7_PA 0x00000000U
2938 #define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
2939 #define AFIO_EXTICR2_EXTI7_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PB_Pos)
2940 #define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk
2941 #define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
2942 #define AFIO_EXTICR2_EXTI7_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PC_Pos)
2943 #define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk
2944 #define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
2945 #define AFIO_EXTICR2_EXTI7_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PD_Pos)
2946 #define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk
2947 #define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
2948 #define AFIO_EXTICR2_EXTI7_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PE_Pos)
2949 #define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk
2950 #define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
2951 #define AFIO_EXTICR2_EXTI7_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI7_PF_Pos)
2952 #define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk
2953 #define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
2954 #define AFIO_EXTICR2_EXTI7_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PG_Pos)
2955 #define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk
2957 /***************** Bit definition for AFIO_EXTICR3 register *****************/
2958 #define AFIO_EXTICR3_EXTI8_Pos (0U)
2959 #define AFIO_EXTICR3_EXTI8_Msk (0xFUL << AFIO_EXTICR3_EXTI8_Pos)
2960 #define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk
2961 #define AFIO_EXTICR3_EXTI9_Pos (4U)
2962 #define AFIO_EXTICR3_EXTI9_Msk (0xFUL << AFIO_EXTICR3_EXTI9_Pos)
2963 #define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk
2964 #define AFIO_EXTICR3_EXTI10_Pos (8U)
2965 #define AFIO_EXTICR3_EXTI10_Msk (0xFUL << AFIO_EXTICR3_EXTI10_Pos)
2966 #define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk
2967 #define AFIO_EXTICR3_EXTI11_Pos (12U)
2968 #define AFIO_EXTICR3_EXTI11_Msk (0xFUL << AFIO_EXTICR3_EXTI11_Pos)
2969 #define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk
2972 #define AFIO_EXTICR3_EXTI8_PA 0x00000000U
2973 #define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
2974 #define AFIO_EXTICR3_EXTI8_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PB_Pos)
2975 #define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk
2976 #define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
2977 #define AFIO_EXTICR3_EXTI8_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PC_Pos)
2978 #define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk
2979 #define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
2980 #define AFIO_EXTICR3_EXTI8_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PD_Pos)
2981 #define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk
2982 #define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
2983 #define AFIO_EXTICR3_EXTI8_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PE_Pos)
2984 #define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk
2985 #define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
2986 #define AFIO_EXTICR3_EXTI8_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI8_PF_Pos)
2987 #define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk
2988 #define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
2989 #define AFIO_EXTICR3_EXTI8_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PG_Pos)
2990 #define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk
2993 #define AFIO_EXTICR3_EXTI9_PA 0x00000000U
2994 #define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
2995 #define AFIO_EXTICR3_EXTI9_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PB_Pos)
2996 #define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk
2997 #define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
2998 #define AFIO_EXTICR3_EXTI9_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PC_Pos)
2999 #define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk
3000 #define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
3001 #define AFIO_EXTICR3_EXTI9_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PD_Pos)
3002 #define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk
3003 #define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
3004 #define AFIO_EXTICR3_EXTI9_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PE_Pos)
3005 #define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk
3006 #define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
3007 #define AFIO_EXTICR3_EXTI9_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI9_PF_Pos)
3008 #define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk
3009 #define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
3010 #define AFIO_EXTICR3_EXTI9_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PG_Pos)
3011 #define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk
3014 #define AFIO_EXTICR3_EXTI10_PA 0x00000000U
3015 #define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
3016 #define AFIO_EXTICR3_EXTI10_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PB_Pos)
3017 #define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk
3018 #define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
3019 #define AFIO_EXTICR3_EXTI10_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PC_Pos)
3020 #define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk
3021 #define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
3022 #define AFIO_EXTICR3_EXTI10_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PD_Pos)
3023 #define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk
3024 #define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
3025 #define AFIO_EXTICR3_EXTI10_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PE_Pos)
3026 #define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk
3027 #define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
3028 #define AFIO_EXTICR3_EXTI10_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI10_PF_Pos)
3029 #define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk
3030 #define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
3031 #define AFIO_EXTICR3_EXTI10_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PG_Pos)
3032 #define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk
3035 #define AFIO_EXTICR3_EXTI11_PA 0x00000000U
3036 #define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
3037 #define AFIO_EXTICR3_EXTI11_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PB_Pos)
3038 #define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk
3039 #define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
3040 #define AFIO_EXTICR3_EXTI11_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PC_Pos)
3041 #define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk
3042 #define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
3043 #define AFIO_EXTICR3_EXTI11_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PD_Pos)
3044 #define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk
3045 #define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
3046 #define AFIO_EXTICR3_EXTI11_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PE_Pos)
3047 #define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk
3048 #define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
3049 #define AFIO_EXTICR3_EXTI11_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI11_PF_Pos)
3050 #define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk
3051 #define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
3052 #define AFIO_EXTICR3_EXTI11_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PG_Pos)
3053 #define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk
3055 /***************** Bit definition for AFIO_EXTICR4 register *****************/
3056 #define AFIO_EXTICR4_EXTI12_Pos (0U)
3057 #define AFIO_EXTICR4_EXTI12_Msk (0xFUL << AFIO_EXTICR4_EXTI12_Pos)
3058 #define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk
3059 #define AFIO_EXTICR4_EXTI13_Pos (4U)
3060 #define AFIO_EXTICR4_EXTI13_Msk (0xFUL << AFIO_EXTICR4_EXTI13_Pos)
3061 #define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk
3062 #define AFIO_EXTICR4_EXTI14_Pos (8U)
3063 #define AFIO_EXTICR4_EXTI14_Msk (0xFUL << AFIO_EXTICR4_EXTI14_Pos)
3064 #define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk
3065 #define AFIO_EXTICR4_EXTI15_Pos (12U)
3066 #define AFIO_EXTICR4_EXTI15_Msk (0xFUL << AFIO_EXTICR4_EXTI15_Pos)
3067 #define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk
3069 /* EXTI12 configuration */
3070 #define AFIO_EXTICR4_EXTI12_PA 0x00000000U
3071 #define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
3072 #define AFIO_EXTICR4_EXTI12_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PB_Pos)
3073 #define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk
3074 #define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
3075 #define AFIO_EXTICR4_EXTI12_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PC_Pos)
3076 #define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk
3077 #define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
3078 #define AFIO_EXTICR4_EXTI12_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PD_Pos)
3079 #define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk
3080 #define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
3081 #define AFIO_EXTICR4_EXTI12_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PE_Pos)
3082 #define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk
3083 #define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
3084 #define AFIO_EXTICR4_EXTI12_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI12_PF_Pos)
3085 #define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk
3086 #define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
3087 #define AFIO_EXTICR4_EXTI12_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PG_Pos)
3088 #define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk
3090 /* EXTI13 configuration */
3091 #define AFIO_EXTICR4_EXTI13_PA 0x00000000U
3092 #define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
3093 #define AFIO_EXTICR4_EXTI13_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PB_Pos)
3094 #define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk
3095 #define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
3096 #define AFIO_EXTICR4_EXTI13_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PC_Pos)
3097 #define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk
3098 #define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
3099 #define AFIO_EXTICR4_EXTI13_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PD_Pos)
3100 #define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk
3101 #define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
3102 #define AFIO_EXTICR4_EXTI13_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PE_Pos)
3103 #define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk
3104 #define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
3105 #define AFIO_EXTICR4_EXTI13_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI13_PF_Pos)
3106 #define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk
3107 #define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
3108 #define AFIO_EXTICR4_EXTI13_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PG_Pos)
3109 #define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk
3112 #define AFIO_EXTICR4_EXTI14_PA 0x00000000U
3113 #define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
3114 #define AFIO_EXTICR4_EXTI14_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PB_Pos)
3115 #define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk
3116 #define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
3117 #define AFIO_EXTICR4_EXTI14_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PC_Pos)
3118 #define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk
3119 #define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
3120 #define AFIO_EXTICR4_EXTI14_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PD_Pos)
3121 #define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk
3122 #define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
3123 #define AFIO_EXTICR4_EXTI14_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PE_Pos)
3124 #define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk
3125 #define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
3126 #define AFIO_EXTICR4_EXTI14_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI14_PF_Pos)
3127 #define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk
3128 #define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
3129 #define AFIO_EXTICR4_EXTI14_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PG_Pos)
3130 #define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk
3133 #define AFIO_EXTICR4_EXTI15_PA 0x00000000U
3134 #define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
3135 #define AFIO_EXTICR4_EXTI15_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PB_Pos)
3136 #define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk
3137 #define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
3138 #define AFIO_EXTICR4_EXTI15_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PC_Pos)
3139 #define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk
3140 #define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
3141 #define AFIO_EXTICR4_EXTI15_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PD_Pos)
3142 #define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk
3143 #define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
3144 #define AFIO_EXTICR4_EXTI15_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PE_Pos)
3145 #define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk
3146 #define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
3147 #define AFIO_EXTICR4_EXTI15_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI15_PF_Pos)
3148 #define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk
3149 #define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
3150 #define AFIO_EXTICR4_EXTI15_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PG_Pos)
3151 #define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk
3153 /******************************************************************************/
3154 /* */
3155 /* External Interrupt/Event Controller (EXTI) */
3156 /* */
3157 /******************************************************************************/
3158 
3159 /******************* Bit definition for EXTI_IMR register *******************/
3160 #define EXTI_IMR_MR0_Pos (0U)
3161 #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)
3162 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk
3163 #define EXTI_IMR_MR1_Pos (1U)
3164 #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)
3165 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk
3166 #define EXTI_IMR_MR2_Pos (2U)
3167 #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)
3168 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk
3169 #define EXTI_IMR_MR3_Pos (3U)
3170 #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)
3171 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk
3172 #define EXTI_IMR_MR4_Pos (4U)
3173 #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)
3174 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk
3175 #define EXTI_IMR_MR5_Pos (5U)
3176 #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)
3177 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk
3178 #define EXTI_IMR_MR6_Pos (6U)
3179 #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)
3180 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk
3181 #define EXTI_IMR_MR7_Pos (7U)
3182 #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)
3183 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk
3184 #define EXTI_IMR_MR8_Pos (8U)
3185 #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)
3186 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk
3187 #define EXTI_IMR_MR9_Pos (9U)
3188 #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)
3189 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk
3190 #define EXTI_IMR_MR10_Pos (10U)
3191 #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)
3192 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk
3193 #define EXTI_IMR_MR11_Pos (11U)
3194 #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)
3195 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk
3196 #define EXTI_IMR_MR12_Pos (12U)
3197 #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)
3198 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk
3199 #define EXTI_IMR_MR13_Pos (13U)
3200 #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)
3201 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk
3202 #define EXTI_IMR_MR14_Pos (14U)
3203 #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)
3204 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk
3205 #define EXTI_IMR_MR15_Pos (15U)
3206 #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)
3207 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk
3208 #define EXTI_IMR_MR16_Pos (16U)
3209 #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)
3210 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk
3211 #define EXTI_IMR_MR17_Pos (17U)
3212 #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)
3213 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk
3214 #define EXTI_IMR_MR18_Pos (18U)
3215 #define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)
3216 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk
3218 /******************* Bit definition for EXTI_EMR register *******************/
3219 #define EXTI_EMR_MR0_Pos (0U)
3220 #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)
3221 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk
3222 #define EXTI_EMR_MR1_Pos (1U)
3223 #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)
3224 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk
3225 #define EXTI_EMR_MR2_Pos (2U)
3226 #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)
3227 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk
3228 #define EXTI_EMR_MR3_Pos (3U)
3229 #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)
3230 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk
3231 #define EXTI_EMR_MR4_Pos (4U)
3232 #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)
3233 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk
3234 #define EXTI_EMR_MR5_Pos (5U)
3235 #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)
3236 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk
3237 #define EXTI_EMR_MR6_Pos (6U)
3238 #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)
3239 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk
3240 #define EXTI_EMR_MR7_Pos (7U)
3241 #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)
3242 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk
3243 #define EXTI_EMR_MR8_Pos (8U)
3244 #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)
3245 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk
3246 #define EXTI_EMR_MR9_Pos (9U)
3247 #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)
3248 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk
3249 #define EXTI_EMR_MR10_Pos (10U)
3250 #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)
3251 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk
3252 #define EXTI_EMR_MR11_Pos (11U)
3253 #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)
3254 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk
3255 #define EXTI_EMR_MR12_Pos (12U)
3256 #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)
3257 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk
3258 #define EXTI_EMR_MR13_Pos (13U)
3259 #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)
3260 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk
3261 #define EXTI_EMR_MR14_Pos (14U)
3262 #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)
3263 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk
3264 #define EXTI_EMR_MR15_Pos (15U)
3265 #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)
3266 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk
3267 #define EXTI_EMR_MR16_Pos (16U)
3268 #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)
3269 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk
3270 #define EXTI_EMR_MR17_Pos (17U)
3271 #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)
3272 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk
3273 #define EXTI_EMR_MR18_Pos (18U)
3274 #define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)
3275 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk
3277 /****************** Bit definition for EXTI_RTSR register *******************/
3278 #define EXTI_RTSR_TR0_Pos (0U)
3279 #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)
3280 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk
3281 #define EXTI_RTSR_TR1_Pos (1U)
3282 #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)
3283 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk
3284 #define EXTI_RTSR_TR2_Pos (2U)
3285 #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)
3286 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk
3287 #define EXTI_RTSR_TR3_Pos (3U)
3288 #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)
3289 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk
3290 #define EXTI_RTSR_TR4_Pos (4U)
3291 #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)
3292 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk
3293 #define EXTI_RTSR_TR5_Pos (5U)
3294 #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)
3295 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk
3296 #define EXTI_RTSR_TR6_Pos (6U)
3297 #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)
3298 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk
3299 #define EXTI_RTSR_TR7_Pos (7U)
3300 #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)
3301 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk
3302 #define EXTI_RTSR_TR8_Pos (8U)
3303 #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)
3304 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk
3305 #define EXTI_RTSR_TR9_Pos (9U)
3306 #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)
3307 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk
3308 #define EXTI_RTSR_TR10_Pos (10U)
3309 #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)
3310 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk
3311 #define EXTI_RTSR_TR11_Pos (11U)
3312 #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)
3313 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk
3314 #define EXTI_RTSR_TR12_Pos (12U)
3315 #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)
3316 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk
3317 #define EXTI_RTSR_TR13_Pos (13U)
3318 #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)
3319 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk
3320 #define EXTI_RTSR_TR14_Pos (14U)
3321 #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)
3322 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk
3323 #define EXTI_RTSR_TR15_Pos (15U)
3324 #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)
3325 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk
3326 #define EXTI_RTSR_TR16_Pos (16U)
3327 #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)
3328 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk
3329 #define EXTI_RTSR_TR17_Pos (17U)
3330 #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)
3331 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk
3332 #define EXTI_RTSR_TR18_Pos (18U)
3333 #define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)
3334 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk
3336 /****************** Bit definition for EXTI_FTSR register *******************/
3337 #define EXTI_FTSR_TR0_Pos (0U)
3338 #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)
3339 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk
3340 #define EXTI_FTSR_TR1_Pos (1U)
3341 #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)
3342 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk
3343 #define EXTI_FTSR_TR2_Pos (2U)
3344 #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)
3345 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk
3346 #define EXTI_FTSR_TR3_Pos (3U)
3347 #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)
3348 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk
3349 #define EXTI_FTSR_TR4_Pos (4U)
3350 #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)
3351 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk
3352 #define EXTI_FTSR_TR5_Pos (5U)
3353 #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)
3354 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk
3355 #define EXTI_FTSR_TR6_Pos (6U)
3356 #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)
3357 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk
3358 #define EXTI_FTSR_TR7_Pos (7U)
3359 #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)
3360 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk
3361 #define EXTI_FTSR_TR8_Pos (8U)
3362 #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)
3363 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk
3364 #define EXTI_FTSR_TR9_Pos (9U)
3365 #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)
3366 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk
3367 #define EXTI_FTSR_TR10_Pos (10U)
3368 #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)
3369 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk
3370 #define EXTI_FTSR_TR11_Pos (11U)
3371 #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)
3372 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk
3373 #define EXTI_FTSR_TR12_Pos (12U)
3374 #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)
3375 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk
3376 #define EXTI_FTSR_TR13_Pos (13U)
3377 #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)
3378 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk
3379 #define EXTI_FTSR_TR14_Pos (14U)
3380 #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)
3381 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk
3382 #define EXTI_FTSR_TR15_Pos (15U)
3383 #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)
3384 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk
3385 #define EXTI_FTSR_TR16_Pos (16U)
3386 #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)
3387 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk
3388 #define EXTI_FTSR_TR17_Pos (17U)
3389 #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)
3390 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk
3391 #define EXTI_FTSR_TR18_Pos (18U)
3392 #define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)
3393 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk
3395 /****************** Bit definition for EXTI_SWIER register ******************/
3396 #define EXTI_SWIER_SWIER0_Pos (0U)
3397 #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)
3398 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk
3399 #define EXTI_SWIER_SWIER1_Pos (1U)
3400 #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)
3401 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk
3402 #define EXTI_SWIER_SWIER2_Pos (2U)
3403 #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)
3404 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk
3405 #define EXTI_SWIER_SWIER3_Pos (3U)
3406 #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)
3407 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk
3408 #define EXTI_SWIER_SWIER4_Pos (4U)
3409 #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)
3410 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk
3411 #define EXTI_SWIER_SWIER5_Pos (5U)
3412 #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)
3413 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk
3414 #define EXTI_SWIER_SWIER6_Pos (6U)
3415 #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)
3416 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk
3417 #define EXTI_SWIER_SWIER7_Pos (7U)
3418 #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)
3419 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk
3420 #define EXTI_SWIER_SWIER8_Pos (8U)
3421 #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)
3422 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk
3423 #define EXTI_SWIER_SWIER9_Pos (9U)
3424 #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)
3425 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk
3426 #define EXTI_SWIER_SWIER10_Pos (10U)
3427 #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)
3428 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk
3429 #define EXTI_SWIER_SWIER11_Pos (11U)
3430 #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)
3431 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk
3432 #define EXTI_SWIER_SWIER12_Pos (12U)
3433 #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)
3434 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk
3435 #define EXTI_SWIER_SWIER13_Pos (13U)
3436 #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)
3437 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk
3438 #define EXTI_SWIER_SWIER14_Pos (14U)
3439 #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)
3440 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk
3441 #define EXTI_SWIER_SWIER15_Pos (15U)
3442 #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)
3443 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk
3444 #define EXTI_SWIER_SWIER16_Pos (16U)
3445 #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)
3446 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk
3447 #define EXTI_SWIER_SWIER17_Pos (17U)
3448 #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)
3449 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk
3450 #define EXTI_SWIER_SWIER18_Pos (18U)
3451 #define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)
3452 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk
3454 /******************* Bit definition for EXTI_PR register ********************/
3455 #define EXTI_PR_PR0_Pos (0U)
3456 #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)
3457 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk
3458 #define EXTI_PR_PR1_Pos (1U)
3459 #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)
3460 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk
3461 #define EXTI_PR_PR2_Pos (2U)
3462 #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)
3463 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk
3464 #define EXTI_PR_PR3_Pos (3U)
3465 #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)
3466 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk
3467 #define EXTI_PR_PR4_Pos (4U)
3468 #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)
3469 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk
3470 #define EXTI_PR_PR5_Pos (5U)
3471 #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)
3472 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk
3473 #define EXTI_PR_PR6_Pos (6U)
3474 #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)
3475 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk
3476 #define EXTI_PR_PR7_Pos (7U)
3477 #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)
3478 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk
3479 #define EXTI_PR_PR8_Pos (8U)
3480 #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)
3481 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk
3482 #define EXTI_PR_PR9_Pos (9U)
3483 #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)
3484 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk
3485 #define EXTI_PR_PR10_Pos (10U)
3486 #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)
3487 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk
3488 #define EXTI_PR_PR11_Pos (11U)
3489 #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)
3490 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk
3491 #define EXTI_PR_PR12_Pos (12U)
3492 #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)
3493 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk
3494 #define EXTI_PR_PR13_Pos (13U)
3495 #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)
3496 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk
3497 #define EXTI_PR_PR14_Pos (14U)
3498 #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)
3499 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk
3500 #define EXTI_PR_PR15_Pos (15U)
3501 #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)
3502 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk
3503 #define EXTI_PR_PR16_Pos (16U)
3504 #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)
3505 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk
3506 #define EXTI_PR_PR17_Pos (17U)
3507 #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)
3508 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk
3509 #define EXTI_PR_PR18_Pos (18U)
3510 #define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)
3511 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk
3513 /******************************************************************************/
3514 /* */
3515 /* Direct Memory Access Controller (DMAC) */
3516 /* */
3517 /******************************************************************************/
3518 
3519 /******************************* Bit definition for DMAC_CTLLx register *******************************/
3520 #define DMAC_CTLL_INT_EN (0x1U << 0)
3522 #define DMAC_CTLL_DST_TR_WIDTH_Msk (0x7U << 1)
3523 #define DMAC_CTLL_DST_TR_WIDTH_8 (0x0U << 1)
3524 #define DMAC_CTLL_DST_TR_WIDTH_16 (0x1U << 1)
3525 #define DMAC_CTLL_DST_TR_WIDTH_32 (0x2U << 1)
3527 #define DMAC_CTLL_SRC_TR_WIDTH_Msk (0x7U << 4)
3528 #define DMAC_CTLL_SRC_TR_WIDTH_8 (0x0U << 4)
3529 #define DMAC_CTLL_SRC_TR_WIDTH_16 (0x1U << 4)
3530 #define DMAC_CTLL_SRC_TR_WIDTH_32 (0x2U << 4)
3532 #define DMAC_CTLL_DINC_Msk (0x3U << 7)
3533 #define DMAC_CTLL_DINC_INC (0x0U << 7)
3534 #define DMAC_CTLL_DINC_DEC (0x1U << 7)
3535 #define DMAC_CTLL_DINC_NO (0x2U << 7)
3537 #define DMAC_CTLL_SINC_Msk (0x3U << 9)
3538 #define DMAC_CTLL_SINC_INC (0x0U << 9)
3539 #define DMAC_CTLL_SINC_DEC (0x1U << 9)
3540 #define DMAC_CTLL_SINC_NO (0x2U << 9)
3542 #define DMAC_CTLL_DEST_MSIZE_Msk (0x7U << 11)
3543 #define DMAC_CTLL_DEST_MSIZE_1 (0x0U << 11)
3544 #define DMAC_CTLL_DEST_MSIZE_4 (0x1U << 11)
3545 #define DMAC_CTLL_DEST_MSIZE_8 (0x2U << 11)
3546 #define DMAC_CTLL_DEST_MSIZE_16 (0x3U << 11)
3547 #define DMAC_CTLL_DEST_MSIZE_32 (0x4U << 11)
3548 #define DMAC_CTLL_DEST_MSIZE_64 (0x5U << 11)
3549 #define DMAC_CTLL_DEST_MSIZE_128 (0x6U << 11)
3550 #define DMAC_CTLL_DEST_MSIZE_256 (0x7U << 11)
3552 #define DMAC_CTLL_SRC_MSIZE_Msk (0x7U << 14)
3553 #define DMAC_CTLL_SRC_MSIZE_1 (0x0U << 14)
3554 #define DMAC_CTLL_SRC_MSIZE_4 (0x1U << 14)
3555 #define DMAC_CTLL_SRC_MSIZE_8 (0x2U << 14)
3556 #define DMAC_CTLL_SRC_MSIZE_16 (0x3U << 14)
3557 #define DMAC_CTLL_SRC_MSIZE_32 (0x4U << 14)
3558 #define DMAC_CTLL_SRC_MSIZE_64 (0x5U << 14)
3559 #define DMAC_CTLL_SRC_MSIZE_128 (0x6U << 14)
3560 #define DMAC_CTLL_SRC_MSIZE_256 (0x7U << 14)
3562 #define DMAC_CTLL_SRC_GATHER_EN (0x1U << 17)
3563 #define DMAC_CTLL_DST_SCATTER_EN (0x1U << 18)
3565 #define DMAC_CTLL_TT_FC_Msk (0x7U << 20)
3566 #define DMAC_CTLL_TT_FC_M2M_DMAC (0x0U << 20)
3567 #define DMAC_CTLL_TT_FC_M2P_DMAC (0x1U << 20)
3568 #define DMAC_CTLL_TT_FC_P2M_DMAC (0x2U << 20)
3569 #define DMAC_CTLL_TT_FC_P2P_DMAC (0x3U << 20)
3570 #define DMAC_CTLL_TT_FC_P2M_PERIPH (0x4U << 20)
3571 #define DMAC_CTLL_TT_FC_P2P_SRC_PERIPH (0x5U << 20)
3572 #define DMAC_CTLL_TT_FC_M2P_PERIPH (0x6U << 20)
3573 #define DMAC_CTLL_TT_FC_P2P_DST_PERIPH (0x7U << 20)
3575 #define DMAC_CTLL_LLP_DST_EN (0x1U << 27)
3576 #define DMAC_CTLL_LLP_SRC_EN (0x1U << 28)
3578 /******************************* Bit definition for DMAC_CTLHx register *******************************/
3579 #define DMAC_CTLH_BLOCK_TS_Msk (0xFFFU)
3580 #define DMAC_CTLH_DONE (0x1U << 12)
3582 /******************************* Bit definition for DMAC_CFGLx register *******************************/
3583 #define DMAC_CFGL_CH_PRIOR_Msk (0x7U << 5)
3584 #define DMAC_CFGL_CH_SUSP (0x1U << 8)
3585 #define DMAC_CFGL_FIFO_EMPTY (0x1U << 9)
3586 #define DMAC_CFGL_HS_SEL_DST (0x1U << 10)
3587 #define DMAC_CFGL_HS_SEL_SRC (0x1U << 11)
3589 #define DMAC_CFGL_DST_HS_POL (0x1U << 18)
3590 #define DMAC_CFGL_SRC_HS_POL (0x1U << 19)
3592 #define DMAC_CFGL_RELOAD_SRC (0x1U << 30)
3593 #define DMAC_CFGL_RELOAD_DST (0x1U << 31)
3595 /******************************* Bit definition for DMAC_CFGHx register *******************************/
3596 #define DMAC_CFGH_FIFO_MODE (0x1U << 1)
3597 #define DMAC_CFGH_DS_UPD_EN (0x1U << 5)
3598 #define DMAC_CFGH_SS_UPD_EN (0x1U << 6)
3600 #define DMAC_CFGH_SRC_PER_Msk (0xFU << 7)
3601 #define DMAC_CFGH_DEST_PER_Msk (0xFU << 11)
3603 /******************************************************************************/
3604 /* */
3605 /* Analog to Digital Converter (ADC) */
3606 /* */
3607 /******************************************************************************/
3608 
3609 /******************** Bit definition for ADC_SR register ********************/
3610 #define ADC_SR_AWD_Pos (0U)
3611 #define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos)
3612 #define ADC_SR_AWD ADC_SR_AWD_Msk
3613 #define ADC_SR_EOC_Pos (1U)
3614 #define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos)
3615 #define ADC_SR_EOC ADC_SR_EOC_Msk
3616 #define ADC_SR_JEOC_Pos (2U)
3617 #define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos)
3618 #define ADC_SR_JEOC ADC_SR_JEOC_Msk
3619 #define ADC_SR_JSTRT_Pos (3U)
3620 #define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos)
3621 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk
3622 #define ADC_SR_STRT_Pos (4U)
3623 #define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos)
3624 #define ADC_SR_STRT ADC_SR_STRT_Msk
3626 /******************* Bit definition for ADC_CR1 register ********************/
3627 #define ADC_CR1_AWDCH_Pos (0U)
3628 #define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos)
3629 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk
3630 #define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos)
3631 #define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos)
3632 #define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos)
3633 #define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos)
3634 #define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos)
3636 #define ADC_CR1_EOCIE_Pos (5U)
3637 #define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos)
3638 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk
3639 #define ADC_CR1_AWDIE_Pos (6U)
3640 #define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos)
3641 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk
3642 #define ADC_CR1_JEOCIE_Pos (7U)
3643 #define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos)
3644 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk
3645 #define ADC_CR1_SCAN_Pos (8U)
3646 #define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos)
3647 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk
3648 #define ADC_CR1_AWDSGL_Pos (9U)
3649 #define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos)
3650 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk
3651 #define ADC_CR1_JAUTO_Pos (10U)
3652 #define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos)
3653 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk
3654 #define ADC_CR1_DISCEN_Pos (11U)
3655 #define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos)
3656 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk
3657 #define ADC_CR1_JDISCEN_Pos (12U)
3658 #define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos)
3659 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk
3661 #define ADC_CR1_DISCNUM_Pos (13U)
3662 #define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos)
3663 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk
3664 #define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos)
3665 #define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos)
3666 #define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos)
3668 #define ADC_CR1_DUALMOD_Pos (16U)
3669 #define ADC_CR1_DUALMOD_Msk (0xFUL << ADC_CR1_DUALMOD_Pos)
3670 #define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk
3671 #define ADC_CR1_DUALMOD_0 (0x1UL << ADC_CR1_DUALMOD_Pos)
3672 #define ADC_CR1_DUALMOD_1 (0x2UL << ADC_CR1_DUALMOD_Pos)
3673 #define ADC_CR1_DUALMOD_2 (0x4UL << ADC_CR1_DUALMOD_Pos)
3674 #define ADC_CR1_DUALMOD_3 (0x8UL << ADC_CR1_DUALMOD_Pos)
3676 #define ADC_CR1_JAWDEN_Pos (22U)
3677 #define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos)
3678 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk
3679 #define ADC_CR1_AWDEN_Pos (23U)
3680 #define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos)
3681 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk
3683 /******************* Bit definition for ADC_CR2 register ********************/
3684 #define ADC_CR2_ADON_Pos (0U)
3685 #define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos)
3686 #define ADC_CR2_ADON ADC_CR2_ADON_Msk
3687 #define ADC_CR2_CONT_Pos (1U)
3688 #define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos)
3689 #define ADC_CR2_CONT ADC_CR2_CONT_Msk
3690 #define ADC_CR2_CAL_Pos (2U)
3691 #define ADC_CR2_CAL_Msk (0x1UL << ADC_CR2_CAL_Pos)
3692 #define ADC_CR2_CAL ADC_CR2_CAL_Msk
3693 #define ADC_CR2_RSTCAL_Pos (3U)
3694 #define ADC_CR2_RSTCAL_Msk (0x1UL << ADC_CR2_RSTCAL_Pos)
3695 #define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk
3696 #define ADC_CR2_DMA_Pos (8U)
3697 #define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos)
3698 #define ADC_CR2_DMA ADC_CR2_DMA_Msk
3699 #define ADC_CR2_ALIGN_Pos (11U)
3700 #define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos)
3701 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk
3703 #define ADC_CR2_JEXTSEL_Pos (12U)
3704 #define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos)
3705 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk
3706 #define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos)
3707 #define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos)
3708 #define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos)
3710 #define ADC_CR2_JEXTTRIG_Pos (15U)
3711 #define ADC_CR2_JEXTTRIG_Msk (0x1UL << ADC_CR2_JEXTTRIG_Pos)
3712 #define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk
3714 #define ADC_CR2_EXTSEL_Pos (17U)
3715 #define ADC_CR2_EXTSEL_Msk (0x7UL << ADC_CR2_EXTSEL_Pos)
3716 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk
3717 #define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos)
3718 #define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos)
3719 #define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos)
3721 #define ADC_CR2_EXTTRIG_Pos (20U)
3722 #define ADC_CR2_EXTTRIG_Msk (0x1UL << ADC_CR2_EXTTRIG_Pos)
3723 #define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk
3724 #define ADC_CR2_JSWSTART_Pos (21U)
3725 #define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos)
3726 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk
3727 #define ADC_CR2_SWSTART_Pos (22U)
3728 #define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos)
3729 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk
3730 #define ADC_CR2_TSVREFE_Pos (23U)
3731 #define ADC_CR2_TSVREFE_Msk (0x1UL << ADC_CR2_TSVREFE_Pos)
3732 #define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk
3734 /****************** Bit definition for ADC_SMPR1 register *******************/
3735 #define ADC_SMPR1_SMP10_Pos (0U)
3736 #define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos)
3737 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk
3738 #define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos)
3739 #define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos)
3740 #define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos)
3742 #define ADC_SMPR1_SMP11_Pos (3U)
3743 #define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos)
3744 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk
3745 #define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos)
3746 #define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos)
3747 #define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos)
3749 #define ADC_SMPR1_SMP12_Pos (6U)
3750 #define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos)
3751 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk
3752 #define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos)
3753 #define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos)
3754 #define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos)
3756 #define ADC_SMPR1_SMP13_Pos (9U)
3757 #define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos)
3758 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk
3759 #define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos)
3760 #define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos)
3761 #define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos)
3763 #define ADC_SMPR1_SMP14_Pos (12U)
3764 #define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos)
3765 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk
3766 #define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos)
3767 #define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos)
3768 #define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos)
3770 #define ADC_SMPR1_SMP15_Pos (15U)
3771 #define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos)
3772 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk
3773 #define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos)
3774 #define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos)
3775 #define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos)
3777 #define ADC_SMPR1_SMP16_Pos (18U)
3778 #define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos)
3779 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk
3780 #define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos)
3781 #define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos)
3782 #define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos)
3784 #define ADC_SMPR1_SMP17_Pos (21U)
3785 #define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos)
3786 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk
3787 #define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos)
3788 #define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos)
3789 #define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos)
3791 /****************** Bit definition for ADC_SMPR2 register *******************/
3792 #define ADC_SMPR2_SMP0_Pos (0U)
3793 #define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos)
3794 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk
3795 #define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos)
3796 #define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos)
3797 #define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos)
3799 #define ADC_SMPR2_SMP1_Pos (3U)
3800 #define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos)
3801 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk
3802 #define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos)
3803 #define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos)
3804 #define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos)
3806 #define ADC_SMPR2_SMP2_Pos (6U)
3807 #define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos)
3808 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk
3809 #define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos)
3810 #define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos)
3811 #define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos)
3813 #define ADC_SMPR2_SMP3_Pos (9U)
3814 #define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos)
3815 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk
3816 #define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos)
3817 #define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos)
3818 #define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos)
3820 #define ADC_SMPR2_SMP4_Pos (12U)
3821 #define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos)
3822 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk
3823 #define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos)
3824 #define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos)
3825 #define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos)
3827 #define ADC_SMPR2_SMP5_Pos (15U)
3828 #define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos)
3829 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk
3830 #define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos)
3831 #define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos)
3832 #define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos)
3834 #define ADC_SMPR2_SMP6_Pos (18U)
3835 #define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos)
3836 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk
3837 #define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos)
3838 #define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos)
3839 #define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos)
3841 #define ADC_SMPR2_SMP7_Pos (21U)
3842 #define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos)
3843 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk
3844 #define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos)
3845 #define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos)
3846 #define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos)
3848 #define ADC_SMPR2_SMP8_Pos (24U)
3849 #define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos)
3850 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk
3851 #define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos)
3852 #define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos)
3853 #define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos)
3855 #define ADC_SMPR2_SMP9_Pos (27U)
3856 #define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos)
3857 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk
3858 #define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos)
3859 #define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos)
3860 #define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos)
3862 /****************** Bit definition for ADC_JOFR1 register *******************/
3863 #define ADC_JOFR1_JOFFSET1_Pos (0U)
3864 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)
3865 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk
3867 /****************** Bit definition for ADC_JOFR2 register *******************/
3868 #define ADC_JOFR2_JOFFSET2_Pos (0U)
3869 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)
3870 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk
3872 /****************** Bit definition for ADC_JOFR3 register *******************/
3873 #define ADC_JOFR3_JOFFSET3_Pos (0U)
3874 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)
3875 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk
3877 /****************** Bit definition for ADC_JOFR4 register *******************/
3878 #define ADC_JOFR4_JOFFSET4_Pos (0U)
3879 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)
3880 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk
3882 /******************* Bit definition for ADC_HTR register ********************/
3883 #define ADC_HTR_HT_Pos (0U)
3884 #define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos)
3885 #define ADC_HTR_HT ADC_HTR_HT_Msk
3887 /******************* Bit definition for ADC_LTR register ********************/
3888 #define ADC_LTR_LT_Pos (0U)
3889 #define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos)
3890 #define ADC_LTR_LT ADC_LTR_LT_Msk
3892 /******************* Bit definition for ADC_SQR1 register *******************/
3893 #define ADC_SQR1_SQ13_Pos (0U)
3894 #define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos)
3895 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk
3896 #define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos)
3897 #define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos)
3898 #define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos)
3899 #define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos)
3900 #define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos)
3902 #define ADC_SQR1_SQ14_Pos (5U)
3903 #define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos)
3904 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk
3905 #define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos)
3906 #define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos)
3907 #define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos)
3908 #define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos)
3909 #define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos)
3911 #define ADC_SQR1_SQ15_Pos (10U)
3912 #define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos)
3913 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk
3914 #define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos)
3915 #define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos)
3916 #define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos)
3917 #define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos)
3918 #define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos)
3920 #define ADC_SQR1_SQ16_Pos (15U)
3921 #define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos)
3922 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk
3923 #define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos)
3924 #define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos)
3925 #define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos)
3926 #define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos)
3927 #define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos)
3929 #define ADC_SQR1_L_Pos (20U)
3930 #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
3931 #define ADC_SQR1_L ADC_SQR1_L_Msk
3932 #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
3933 #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
3934 #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
3935 #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
3937 /******************* Bit definition for ADC_SQR2 register *******************/
3938 #define ADC_SQR2_SQ7_Pos (0U)
3939 #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
3940 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
3941 #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
3942 #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
3943 #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
3944 #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
3945 #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
3947 #define ADC_SQR2_SQ8_Pos (5U)
3948 #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
3949 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
3950 #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
3951 #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
3952 #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
3953 #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
3954 #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
3956 #define ADC_SQR2_SQ9_Pos (10U)
3957 #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
3958 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
3959 #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
3960 #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
3961 #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
3962 #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
3963 #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
3965 #define ADC_SQR2_SQ10_Pos (15U)
3966 #define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos)
3967 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk
3968 #define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos)
3969 #define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos)
3970 #define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos)
3971 #define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos)
3972 #define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos)
3974 #define ADC_SQR2_SQ11_Pos (20U)
3975 #define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos)
3976 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk
3977 #define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos)
3978 #define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos)
3979 #define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos)
3980 #define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos)
3981 #define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos)
3983 #define ADC_SQR2_SQ12_Pos (25U)
3984 #define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos)
3985 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk
3986 #define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos)
3987 #define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos)
3988 #define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos)
3989 #define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos)
3990 #define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos)
3992 /******************* Bit definition for ADC_SQR3 register *******************/
3993 #define ADC_SQR3_SQ1_Pos (0U)
3994 #define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos)
3995 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk
3996 #define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos)
3997 #define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos)
3998 #define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos)
3999 #define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos)
4000 #define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos)
4002 #define ADC_SQR3_SQ2_Pos (5U)
4003 #define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos)
4004 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk
4005 #define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos)
4006 #define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos)
4007 #define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos)
4008 #define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos)
4009 #define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos)
4011 #define ADC_SQR3_SQ3_Pos (10U)
4012 #define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos)
4013 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk
4014 #define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos)
4015 #define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos)
4016 #define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos)
4017 #define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos)
4018 #define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos)
4020 #define ADC_SQR3_SQ4_Pos (15U)
4021 #define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos)
4022 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk
4023 #define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos)
4024 #define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos)
4025 #define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos)
4026 #define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos)
4027 #define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos)
4029 #define ADC_SQR3_SQ5_Pos (20U)
4030 #define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos)
4031 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk
4032 #define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos)
4033 #define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos)
4034 #define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos)
4035 #define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos)
4036 #define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos)
4038 #define ADC_SQR3_SQ6_Pos (25U)
4039 #define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos)
4040 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk
4041 #define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos)
4042 #define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos)
4043 #define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos)
4044 #define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos)
4045 #define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos)
4047 /******************* Bit definition for ADC_JSQR register *******************/
4048 #define ADC_JSQR_JSQ1_Pos (0U)
4049 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
4050 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
4051 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
4052 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
4053 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
4054 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
4055 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
4057 #define ADC_JSQR_JSQ2_Pos (5U)
4058 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
4059 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
4060 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
4061 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
4062 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
4063 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
4064 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
4066 #define ADC_JSQR_JSQ3_Pos (10U)
4067 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
4068 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
4069 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
4070 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
4071 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
4072 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
4073 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
4075 #define ADC_JSQR_JSQ4_Pos (15U)
4076 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
4077 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
4078 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
4079 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
4080 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
4081 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
4082 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
4084 #define ADC_JSQR_JL_Pos (20U)
4085 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
4086 #define ADC_JSQR_JL ADC_JSQR_JL_Msk
4087 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
4088 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
4090 /******************* Bit definition for ADC_JDR1 register *******************/
4091 #define ADC_JDR1_JDATA_Pos (0U)
4092 #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)
4093 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
4095 /******************* Bit definition for ADC_JDR2 register *******************/
4096 #define ADC_JDR2_JDATA_Pos (0U)
4097 #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)
4098 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
4100 /******************* Bit definition for ADC_JDR3 register *******************/
4101 #define ADC_JDR3_JDATA_Pos (0U)
4102 #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)
4103 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
4105 /******************* Bit definition for ADC_JDR4 register *******************/
4106 #define ADC_JDR4_JDATA_Pos (0U)
4107 #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)
4108 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
4110 /******************** Bit definition for ADC_DR register ********************/
4111 #define ADC_DR_DATA_Pos (0U)
4112 #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)
4113 #define ADC_DR_DATA ADC_DR_DATA_Msk
4114 #define ADC_DR_ADC2DATA_Pos (16U)
4115 #define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos)
4116 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk
4118 /******************************************************************************/
4119 /* */
4120 /* Digital to Analog Converter (DAC) */
4121 /* */
4122 /******************************************************************************/
4123 
4124 /******************** Bit definition for DAC_CR register ********************/
4125 #define DAC_CR_EN1_Pos (0U)
4126 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
4127 #define DAC_CR_EN1 DAC_CR_EN1_Msk
4128 #define DAC_CR_BOFF1_Pos (1U)
4129 #define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos)
4130 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk
4131 #define DAC_CR_TEN1_Pos (2U)
4132 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
4133 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk
4135 #define DAC_CR_TSEL1_Pos (3U)
4136 #define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)
4137 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
4138 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
4139 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
4140 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
4142 #define DAC_CR_WAVE1_Pos (6U)
4143 #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
4144 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
4145 #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
4146 #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
4148 #define DAC_CR_MAMP1_Pos (8U)
4149 #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
4150 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
4151 #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
4152 #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
4153 #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
4154 #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
4156 #define DAC_CR_DMAEN1_Pos (12U)
4157 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
4158 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
4159 #define DAC_CR_EN2_Pos (16U)
4160 #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
4161 #define DAC_CR_EN2 DAC_CR_EN2_Msk
4162 #define DAC_CR_BOFF2_Pos (17U)
4163 #define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos)
4164 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk
4165 #define DAC_CR_TEN2_Pos (18U)
4166 #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
4167 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk
4169 #define DAC_CR_TSEL2_Pos (19U)
4170 #define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)
4171 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
4172 #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
4173 #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
4174 #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
4176 #define DAC_CR_WAVE2_Pos (22U)
4177 #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
4178 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
4179 #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
4180 #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
4182 #define DAC_CR_MAMP2_Pos (24U)
4183 #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
4184 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
4185 #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
4186 #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
4187 #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
4188 #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
4190 #define DAC_CR_DMAEN2_Pos (28U)
4191 #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
4192 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
4194 /***************** Bit definition for DAC_SWTRIGR register ******************/
4195 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
4196 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
4197 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
4198 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
4199 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
4200 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
4202 /***************** Bit definition for DAC_DHR12R1 register ******************/
4203 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
4204 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
4205 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
4207 /***************** Bit definition for DAC_DHR12L1 register ******************/
4208 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
4209 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
4210 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
4212 /****************** Bit definition for DAC_DHR8R1 register ******************/
4213 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
4214 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
4215 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
4217 /***************** Bit definition for DAC_DHR12R2 register ******************/
4218 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
4219 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
4220 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
4222 /***************** Bit definition for DAC_DHR12L2 register ******************/
4223 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
4224 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
4225 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
4227 /****************** Bit definition for DAC_DHR8R2 register ******************/
4228 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
4229 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
4230 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
4232 /***************** Bit definition for DAC_DHR12RD register ******************/
4233 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
4234 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
4235 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
4236 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
4237 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
4238 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
4240 /***************** Bit definition for DAC_DHR12LD register ******************/
4241 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
4242 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
4243 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
4244 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
4245 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
4246 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
4248 /****************** Bit definition for DAC_DHR8RD register ******************/
4249 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
4250 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
4251 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
4252 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
4253 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
4254 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
4256 /******************* Bit definition for DAC_DOR1 register *******************/
4257 #define DAC_DOR1_DACC1DOR_Pos (0U)
4258 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
4259 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
4261 /******************* Bit definition for DAC_DOR2 register *******************/
4262 #define DAC_DOR2_DACC2DOR_Pos (0U)
4263 #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
4264 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
4266 /*****************************************************************************/
4267 /* */
4268 /* Timers (TIM) */
4269 /* */
4270 /*****************************************************************************/
4271 /******************* Bit definition for TIM_CR1 register *******************/
4272 #define TIM_CR1_CEN_Pos (0U)
4273 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
4274 #define TIM_CR1_CEN TIM_CR1_CEN_Msk
4275 #define TIM_CR1_UDIS_Pos (1U)
4276 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
4277 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
4278 #define TIM_CR1_URS_Pos (2U)
4279 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
4280 #define TIM_CR1_URS TIM_CR1_URS_Msk
4281 #define TIM_CR1_OPM_Pos (3U)
4282 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
4283 #define TIM_CR1_OPM TIM_CR1_OPM_Msk
4284 #define TIM_CR1_DIR_Pos (4U)
4285 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
4286 #define TIM_CR1_DIR TIM_CR1_DIR_Msk
4288 #define TIM_CR1_CMS_Pos (5U)
4289 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
4290 #define TIM_CR1_CMS TIM_CR1_CMS_Msk
4291 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
4292 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
4294 #define TIM_CR1_ARPE_Pos (7U)
4295 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
4296 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
4298 #define TIM_CR1_CKD_Pos (8U)
4299 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
4300 #define TIM_CR1_CKD TIM_CR1_CKD_Msk
4301 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
4302 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
4304 /******************* Bit definition for TIM_CR2 register *******************/
4305 #define TIM_CR2_CCPC_Pos (0U)
4306 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
4307 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
4308 #define TIM_CR2_CCUS_Pos (2U)
4309 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
4310 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
4311 #define TIM_CR2_CCDS_Pos (3U)
4312 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
4313 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
4315 #define TIM_CR2_MMS_Pos (4U)
4316 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
4317 #define TIM_CR2_MMS TIM_CR2_MMS_Msk
4318 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
4319 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
4320 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
4322 #define TIM_CR2_TI1S_Pos (7U)
4323 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
4324 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
4325 #define TIM_CR2_OIS1_Pos (8U)
4326 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
4327 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
4328 #define TIM_CR2_OIS1N_Pos (9U)
4329 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
4330 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
4331 #define TIM_CR2_OIS2_Pos (10U)
4332 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
4333 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
4334 #define TIM_CR2_OIS2N_Pos (11U)
4335 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
4336 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
4337 #define TIM_CR2_OIS3_Pos (12U)
4338 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
4339 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
4340 #define TIM_CR2_OIS3N_Pos (13U)
4341 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
4342 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
4343 #define TIM_CR2_OIS4_Pos (14U)
4344 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
4345 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
4347 /******************* Bit definition for TIM_SMCR register ******************/
4348 #define TIM_SMCR_SMS_Pos (0U)
4349 #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos)
4350 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
4351 #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos)
4352 #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos)
4353 #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos)
4355 #define TIM_SMCR_TS_Pos (4U)
4356 #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
4357 #define TIM_SMCR_TS TIM_SMCR_TS_Msk
4358 #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
4359 #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
4360 #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
4362 #define TIM_SMCR_MSM_Pos (7U)
4363 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
4364 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
4366 #define TIM_SMCR_ETF_Pos (8U)
4367 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
4368 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
4369 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
4370 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
4371 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
4372 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
4374 #define TIM_SMCR_ETPS_Pos (12U)
4375 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
4376 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
4377 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
4378 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
4380 #define TIM_SMCR_ECE_Pos (14U)
4381 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
4382 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
4383 #define TIM_SMCR_ETP_Pos (15U)
4384 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
4385 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
4387 /******************* Bit definition for TIM_DIER register ******************/
4388 #define TIM_DIER_UIE_Pos (0U)
4389 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
4390 #define TIM_DIER_UIE TIM_DIER_UIE_Msk
4391 #define TIM_DIER_CC1IE_Pos (1U)
4392 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
4393 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
4394 #define TIM_DIER_CC2IE_Pos (2U)
4395 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
4396 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
4397 #define TIM_DIER_CC3IE_Pos (3U)
4398 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
4399 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
4400 #define TIM_DIER_CC4IE_Pos (4U)
4401 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
4402 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
4403 #define TIM_DIER_COMIE_Pos (5U)
4404 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
4405 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
4406 #define TIM_DIER_TIE_Pos (6U)
4407 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
4408 #define TIM_DIER_TIE TIM_DIER_TIE_Msk
4409 #define TIM_DIER_BIE_Pos (7U)
4410 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
4411 #define TIM_DIER_BIE TIM_DIER_BIE_Msk
4412 #define TIM_DIER_UDE_Pos (8U)
4413 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
4414 #define TIM_DIER_UDE TIM_DIER_UDE_Msk
4415 #define TIM_DIER_CC1DE_Pos (9U)
4416 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
4417 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
4418 #define TIM_DIER_CC2DE_Pos (10U)
4419 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
4420 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
4421 #define TIM_DIER_CC3DE_Pos (11U)
4422 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
4423 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
4424 #define TIM_DIER_CC4DE_Pos (12U)
4425 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
4426 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
4427 #define TIM_DIER_COMDE_Pos (13U)
4428 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
4429 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
4430 #define TIM_DIER_TDE_Pos (14U)
4431 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
4432 #define TIM_DIER_TDE TIM_DIER_TDE_Msk
4434 /******************** Bit definition for TIM_SR register *******************/
4435 #define TIM_SR_UIF_Pos (0U)
4436 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
4437 #define TIM_SR_UIF TIM_SR_UIF_Msk
4438 #define TIM_SR_CC1IF_Pos (1U)
4439 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
4440 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
4441 #define TIM_SR_CC2IF_Pos (2U)
4442 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
4443 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
4444 #define TIM_SR_CC3IF_Pos (3U)
4445 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
4446 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
4447 #define TIM_SR_CC4IF_Pos (4U)
4448 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
4449 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
4450 #define TIM_SR_COMIF_Pos (5U)
4451 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
4452 #define TIM_SR_COMIF TIM_SR_COMIF_Msk
4453 #define TIM_SR_TIF_Pos (6U)
4454 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
4455 #define TIM_SR_TIF TIM_SR_TIF_Msk
4456 #define TIM_SR_BIF_Pos (7U)
4457 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
4458 #define TIM_SR_BIF TIM_SR_BIF_Msk
4459 #define TIM_SR_CC1OF_Pos (9U)
4460 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
4461 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
4462 #define TIM_SR_CC2OF_Pos (10U)
4463 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
4464 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
4465 #define TIM_SR_CC3OF_Pos (11U)
4466 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
4467 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
4468 #define TIM_SR_CC4OF_Pos (12U)
4469 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
4470 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
4472 /******************* Bit definition for TIM_EGR register *******************/
4473 #define TIM_EGR_UG_Pos (0U)
4474 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
4475 #define TIM_EGR_UG TIM_EGR_UG_Msk
4476 #define TIM_EGR_CC1G_Pos (1U)
4477 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
4478 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
4479 #define TIM_EGR_CC2G_Pos (2U)
4480 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
4481 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
4482 #define TIM_EGR_CC3G_Pos (3U)
4483 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
4484 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
4485 #define TIM_EGR_CC4G_Pos (4U)
4486 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
4487 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
4488 #define TIM_EGR_COMG_Pos (5U)
4489 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
4490 #define TIM_EGR_COMG TIM_EGR_COMG_Msk
4491 #define TIM_EGR_TG_Pos (6U)
4492 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
4493 #define TIM_EGR_TG TIM_EGR_TG_Msk
4494 #define TIM_EGR_BG_Pos (7U)
4495 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
4496 #define TIM_EGR_BG TIM_EGR_BG_Msk
4498 /****************** Bit definition for TIM_CCMR1 register ******************/
4499 #define TIM_CCMR1_CC1S_Pos (0U)
4500 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
4501 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
4502 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
4503 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
4505 #define TIM_CCMR1_OC1FE_Pos (2U)
4506 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
4507 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
4508 #define TIM_CCMR1_OC1PE_Pos (3U)
4509 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
4510 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
4512 #define TIM_CCMR1_OC1M_Pos (4U)
4513 #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos)
4514 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
4515 #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos)
4516 #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos)
4517 #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos)
4519 #define TIM_CCMR1_OC1CE_Pos (7U)
4520 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
4521 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
4523 #define TIM_CCMR1_CC2S_Pos (8U)
4524 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
4525 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
4526 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
4527 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
4529 #define TIM_CCMR1_OC2FE_Pos (10U)
4530 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
4531 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
4532 #define TIM_CCMR1_OC2PE_Pos (11U)
4533 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
4534 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
4536 #define TIM_CCMR1_OC2M_Pos (12U)
4537 #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos)
4538 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
4539 #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos)
4540 #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos)
4541 #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos)
4543 #define TIM_CCMR1_OC2CE_Pos (15U)
4544 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
4545 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
4547 #define TIM_CCMR1_IC1PSC_Pos (2U)
4548 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
4549 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
4550 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
4551 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
4553 #define TIM_CCMR1_IC1F_Pos (4U)
4554 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
4555 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
4556 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
4557 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
4558 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
4559 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
4561 #define TIM_CCMR1_IC2PSC_Pos (10U)
4562 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
4563 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
4564 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
4565 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
4567 #define TIM_CCMR1_IC2F_Pos (12U)
4568 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
4569 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
4570 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
4571 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
4572 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
4573 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
4575 /****************** Bit definition for TIM_CCMR2 register ******************/
4576 #define TIM_CCMR2_CC3S_Pos (0U)
4577 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
4578 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
4579 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
4580 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
4582 #define TIM_CCMR2_OC3FE_Pos (2U)
4583 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
4584 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
4585 #define TIM_CCMR2_OC3PE_Pos (3U)
4586 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
4587 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
4589 #define TIM_CCMR2_OC3M_Pos (4U)
4590 #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos)
4591 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
4592 #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)
4593 #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)
4594 #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)
4596 #define TIM_CCMR2_OC3CE_Pos (7U)
4597 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
4598 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
4600 #define TIM_CCMR2_CC4S_Pos (8U)
4601 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
4602 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
4603 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
4604 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
4606 #define TIM_CCMR2_OC4FE_Pos (10U)
4607 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
4608 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
4609 #define TIM_CCMR2_OC4PE_Pos (11U)
4610 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
4611 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
4613 #define TIM_CCMR2_OC4M_Pos (12U)
4614 #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos)
4615 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
4616 #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)
4617 #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)
4618 #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)
4620 #define TIM_CCMR2_OC4CE_Pos (15U)
4621 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
4622 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
4624 #define TIM_CCMR2_IC3PSC_Pos (2U)
4625 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
4626 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
4627 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
4628 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
4630 #define TIM_CCMR2_IC3F_Pos (4U)
4631 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
4632 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
4633 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
4634 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
4635 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
4636 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
4638 #define TIM_CCMR2_IC4PSC_Pos (10U)
4639 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
4640 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
4641 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
4642 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
4644 #define TIM_CCMR2_IC4F_Pos (12U)
4645 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
4646 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
4647 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
4648 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
4649 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
4650 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
4652 /******************* Bit definition for TIM_CCER register ******************/
4653 #define TIM_CCER_CC1E_Pos (0U)
4654 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
4655 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
4656 #define TIM_CCER_CC1P_Pos (1U)
4657 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
4658 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
4659 #define TIM_CCER_CC1NE_Pos (2U)
4660 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
4661 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
4662 #define TIM_CCER_CC1NP_Pos (3U)
4663 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
4664 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
4665 #define TIM_CCER_CC2E_Pos (4U)
4666 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
4667 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
4668 #define TIM_CCER_CC2P_Pos (5U)
4669 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
4670 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
4671 #define TIM_CCER_CC2NE_Pos (6U)
4672 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
4673 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
4674 #define TIM_CCER_CC2NP_Pos (7U)
4675 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
4676 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
4677 #define TIM_CCER_CC3E_Pos (8U)
4678 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
4679 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
4680 #define TIM_CCER_CC3P_Pos (9U)
4681 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
4682 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
4683 #define TIM_CCER_CC3NE_Pos (10U)
4684 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
4685 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
4686 #define TIM_CCER_CC3NP_Pos (11U)
4687 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
4688 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
4689 #define TIM_CCER_CC4E_Pos (12U)
4690 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
4691 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
4692 #define TIM_CCER_CC4P_Pos (13U)
4693 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
4694 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
4696 /******************* Bit definition for TIM_CNT register *******************/
4697 #define TIM_CNT_CNT_Pos (0U)
4698 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
4699 #define TIM_CNT_CNT TIM_CNT_CNT_Msk
4701 /******************* Bit definition for TIM_PSC register *******************/
4702 #define TIM_PSC_PSC_Pos (0U)
4703 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
4704 #define TIM_PSC_PSC TIM_PSC_PSC_Msk
4706 /******************* Bit definition for TIM_ARR register *******************/
4707 #define TIM_ARR_ARR_Pos (0U)
4708 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
4709 #define TIM_ARR_ARR TIM_ARR_ARR_Msk
4711 /******************* Bit definition for TIM_RCR register *******************/
4712 #define TIM_RCR_REP_Pos (0U)
4713 #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)
4714 #define TIM_RCR_REP TIM_RCR_REP_Msk
4716 /******************* Bit definition for TIM_CCR1 register ******************/
4717 #define TIM_CCR1_CCR1_Pos (0U)
4718 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
4719 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
4721 /******************* Bit definition for TIM_CCR2 register ******************/
4722 #define TIM_CCR2_CCR2_Pos (0U)
4723 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
4724 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
4726 /******************* Bit definition for TIM_CCR3 register ******************/
4727 #define TIM_CCR3_CCR3_Pos (0U)
4728 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
4729 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
4731 /******************* Bit definition for TIM_CCR4 register ******************/
4732 #define TIM_CCR4_CCR4_Pos (0U)
4733 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
4734 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
4736 /******************* Bit definition for TIM_BDTR register ******************/
4737 #define TIM_BDTR_DTG_Pos (0U)
4738 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
4739 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
4740 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
4741 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
4742 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
4743 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
4744 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
4745 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
4746 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
4747 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
4749 #define TIM_BDTR_LOCK_Pos (8U)
4750 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
4751 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
4752 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
4753 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
4755 #define TIM_BDTR_OSSI_Pos (10U)
4756 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
4757 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
4758 #define TIM_BDTR_OSSR_Pos (11U)
4759 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
4760 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
4761 #define TIM_BDTR_BKE_Pos (12U)
4762 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
4763 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
4764 #define TIM_BDTR_BKP_Pos (13U)
4765 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
4766 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
4767 #define TIM_BDTR_AOE_Pos (14U)
4768 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
4769 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
4770 #define TIM_BDTR_MOE_Pos (15U)
4771 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
4772 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
4774 /******************* Bit definition for TIM_DCR register *******************/
4775 #define TIM_DCR_DBA_Pos (0U)
4776 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
4777 #define TIM_DCR_DBA TIM_DCR_DBA_Msk
4778 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
4779 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
4780 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
4781 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
4782 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
4784 #define TIM_DCR_DBL_Pos (8U)
4785 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
4786 #define TIM_DCR_DBL TIM_DCR_DBL_Msk
4787 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
4788 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
4789 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
4790 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
4791 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
4793 /******************* Bit definition for TIM_DMAR register ******************/
4794 #define TIM_DMAR_DMAB_Pos (0U)
4795 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
4796 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
4798 /******************************************************************************/
4799 /* */
4800 /* Controller Area Network (CAN) */
4801 /* */
4802 /******************************************************************************/
4803 
4804 /*************** Bit definition for CAN_ISR_SR_CMR_MR register **************/
4805 #define CAN_MR_AFM_Pos (0U)
4806 #define CAN_MR_AFM_Msk (0x1UL << CAN_MR_AFM_Pos)
4807 #define CAN_MR_AFM CAN_MR_AFM_Msk
4808 #define CAN_MR_LOM_Pos (1U)
4809 #define CAN_MR_LOM_Msk (0x1UL << CAN_MR_LOM_Pos)
4810 #define CAN_MR_LOM CAN_MR_LOM_Msk
4811 #define CAN_MR_RM_Pos (2U)
4812 #define CAN_MR_RM_Msk (0x1UL << CAN_MR_RM_Pos)
4813 #define CAN_MR_RM CAN_MR_RM_Msk
4815 #define CAN_CMR_AT_Pos (9U)
4816 #define CAN_CMR_AT_Msk (0x1UL << CAN_CMR_AT_Pos)
4817 #define CAN_CMR_AT CAN_CMR_AT_Msk
4818 #define CAN_CMR_TR_Pos (10U)
4819 #define CAN_CMR_TR_Msk (0x1UL << CAN_CMR_TR_Pos)
4820 #define CAN_CMR_TR CAN_CMR_TR_Msk
4822 #define CAN_SR_BS_Pos (16U)
4823 #define CAN_SR_BS_Msk (0x1UL << CAN_SR_BS_Pos)
4824 #define CAN_SR_BS CAN_SR_BS_Msk
4825 #define CAN_SR_ES_Pos (17U)
4826 #define CAN_SR_ES_Msk (0x1UL << CAN_SR_ES_Pos)
4827 #define CAN_SR_ES CAN_SR_ES_Msk
4828 #define CAN_SR_TS_Pos (18U)
4829 #define CAN_SR_TS_Msk (0x1UL << CAN_SR_TS_Pos)
4830 #define CAN_SR_TS CAN_SR_TS_Msk
4831 #define CAN_SR_RS_Pos (19U)
4832 #define CAN_SR_RS_Msk (0x1UL << CAN_SR_RS_Pos)
4833 #define CAN_SR_RS CAN_SR_RS_Msk
4834 #define CAN_SR_TBS_Pos (21U)
4835 #define CAN_SR_TBS_Msk (0x1UL << CAN_SR_TBS_Pos)
4836 #define CAN_SR_TBS CAN_SR_TBS_Msk
4837 #define CAN_SR_DSO_Pos (22U)
4838 #define CAN_SR_DSO_Msk (0x1UL << CAN_SR_DSO_Pos)
4839 #define CAN_SR_DSO CAN_SR_DSO_Msk
4840 #define CAN_SR_RBS_Pos (23U)
4841 #define CAN_SR_RBS_Msk (0x1UL << CAN_SR_RBS_Pos)
4842 #define CAN_SR_RBS CAN_SR_RBS_Msk
4844 #define CAN_ISR_DOI_Pos (24U)
4845 #define CAN_ISR_DOI_Msk (0x1UL << CAN_ISR_DOI_Pos)
4846 #define CAN_ISR_DOI CAN_ISR_DOI_Msk
4847 #define CAN_ISR_BEI_Pos (25U)
4848 #define CAN_ISR_BEI_Msk (0x1UL << CAN_ISR_BEI_Pos)
4849 #define CAN_ISR_BEI CAN_ISR_BEI_Msk
4850 #define CAN_ISR_TI_Pos (26U)
4851 #define CAN_ISR_TI_Msk (0x1UL << CAN_ISR_TI_Pos)
4852 #define CAN_ISR_TI CAN_ISR_TI_Msk
4853 #define CAN_ISR_RI_Pos (27U)
4854 #define CAN_ISR_RI_Msk (0x1UL << CAN_ISR_RI_Pos)
4855 #define CAN_ISR_RI CAN_ISR_RI_Msk
4856 #define CAN_ISR_EPI_Pos (28U)
4857 #define CAN_ISR_EPI_Msk (0x1UL << CAN_ISR_EPI_Pos)
4858 #define CAN_ISR_EPI CAN_ISR_EPI_Msk
4859 #define CAN_ISR_EWI_Pos (29U)
4860 #define CAN_ISR_EWI_Msk (0x1UL << CAN_ISR_EWI_Pos)
4861 #define CAN_ISR_EWI CAN_ISR_EWI_Msk
4862 #define CAN_ISR_ALI_Pos (30U)
4863 #define CAN_ISR_ALI_Msk (0x1UL << CAN_ISR_ALI_Pos)
4864 #define CAN_ISR_ALI CAN_ISR_ALI_Msk
4866 /*************** Bit definition for CAN_BT1_BT0_RMC_IMR **************/
4867 #define CAN_IMR_DOIM_Pos (0U)
4868 #define CAN_IMR_DOIM_Msk (0x1UL << CAN_IMR_DOIM_Pos)
4869 #define CAN_IMR_DOIM CAN_IMR_DOIM_Msk
4870 #define CAN_IMR_BEIM_Pos (1U)
4871 #define CAN_IMR_BEIM_Msk (0x1UL << CAN_IMR_BEIM_Pos)
4872 #define CAN_IMR_BEIM CAN_IMR_BEIM_Msk
4873 #define CAN_IMR_TIM_Pos (2U)
4874 #define CAN_IMR_TIM_Msk (0x1UL << CAN_IMR_TIM_Pos)
4875 #define CAN_IMR_TIM CAN_IMR_TIM_Msk
4876 #define CAN_IMR_RIM_Pos (3U)
4877 #define CAN_IMR_RIM_Msk (0x1UL << CAN_IMR_RIM_Pos)
4878 #define CAN_IMR_RIM CAN_IMR_RIM_Msk
4879 #define CAN_IMR_EPIM_Pos (4U)
4880 #define CAN_IMR_EPIM_Msk (0x1UL << CAN_IMR_EPIM_Pos)
4881 #define CAN_IMR_EPIM CAN_IMR_EPIM_Msk
4882 #define CAN_IMR_EWIM_Pos (5U)
4883 #define CAN_IMR_EWIM_Msk (0x1UL << CAN_IMR_EWIM_Pos)
4884 #define CAN_IMR_EWIM CAN_IMR_EWIM_Msk
4885 #define CAN_IMR_ALIM_Pos (6U)
4886 #define CAN_IMR_ALIM_Msk (0x1UL << CAN_IMR_ALIM_Pos)
4887 #define CAN_IMR_ALIM CAN_IMR_ALIM_Msk
4889 #define CAN_RMC_Pos (8U)
4890 #define CAN_RMC_Msk (0x1FUL << CAN_RMC_Pos)
4891 #define CAN_RMC CAN_RMC_Msk
4893 #define CAN_BTR_BRP_Pos (16U)
4894 #define CAN_BTR_BRP_Msk (0x3FUL << CAN_BTR_BRP_Pos)
4895 #define CAN_BTR_BRP CAN_BTR_BRP_Msk
4896 #define CAN_BTR_SJW_Pos (22U)
4897 #define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)
4898 #define CAN_BTR_SJW CAN_BTR_SJW_Msk
4899 #define CAN_BTR_TSEG1_Pos (24U)
4900 #define CAN_BTR_TSEG1_Msk (0xFUL << CAN_BTR_TSEG1_Pos)
4901 #define CAN_BTR_TSEG1 CAN_BTR_TSEG1_Msk
4902 #define CAN_BTR_TSEG2_Pos (28U)
4903 #define CAN_BTR_TSEG2_Msk (0x7UL << CAN_BTR_TSEG2_Pos)
4904 #define CAN_BTR_TSEG2 CAN_BTR_TSEG2_Msk
4905 #define CAN_BTR_SAM_Pos (31U)
4906 #define CAN_BTR_SAM_Msk (0x1UL << CAN_BTR_SAM_Pos)
4907 #define CAN_BTR_SAM CAN_BTR_SAM_Msk
4909 /************** Bit definition for CAN_ALC_TXERR_RXERR_ECC *************/
4910 #define CAN_ECC_BER_Pos (0U)
4911 #define CAN_ECC_BER_Msk (0x1UL << CAN_ECC_BER_Pos)
4912 #define CAN_ECC_BER CAN_ECC_BER_Msk
4913 #define CAN_ECC_STFER_Pos (1U)
4914 #define CAN_ECC_STFER_Msk (0x1UL << CAN_ECC_STFER_Pos)
4915 #define CAN_ECC_STFER CAN_ECC_STFER_Msk
4916 #define CAN_ECC_CRCER_Pos (2U)
4917 #define CAN_ECC_CRCER_Msk (0x1UL << CAN_ECC_CRCER_Pos)
4918 #define CAN_ECC_CRCER CAN_ECC_CRCER_Msk
4919 #define CAN_ECC_FRMER_Pos (3U)
4920 #define CAN_ECC_FRMER_Msk (0x1UL << CAN_ECC_FRMER_Pos)
4921 #define CAN_ECC_FRMER CAN_ECC_FRMER_Msk
4922 #define CAN_ECC_ACKER_Pos (4U)
4923 #define CAN_ECC_ACKER_Msk (0x1UL << CAN_ECC_ACKER_Pos)
4924 #define CAN_ECC_ACKER CAN_ECC_ACKER_Msk
4925 #define CAN_ECC_EDIR_Pos (5U)
4926 #define CAN_ECC_EDIR_Msk (0x1UL << CAN_ECC_EDIR_Pos)
4927 #define CAN_ECC_EDIR CAN_ECC_EDIR_Msk
4928 #define CAN_ECC_TXWRN_Pos (6U)
4929 #define CAN_ECC_TXWRN_Msk (0x1UL << CAN_ECC_TXWRN_Pos)
4930 #define CAN_ECC_TXWRN CAN_ECC_TXWRN_Msk
4931 #define CAN_ECC_RXERR_Pos (8U)
4932 #define CAN_ECC_RXERR_Msk (0xFFUL << CAN_ECC_RXERR_Pos)
4933 #define CAN_ECC_RXERR CAN_ECC_RXERR_Msk
4935 #define CAN_RXERR_Pos (8U)
4936 #define CAN_RXERR_Msk (0xFFUL << CAN_RXERR_Pos)
4937 #define CAN_RXERR CAN_RXERR_Msk
4939 #define CAN_TXERR_Pos (16U)
4940 #define CAN_TXERR_Msk (0xFFUL << CAN_TXERR_Pos)
4941 #define CAN_TXERR CAN_TXERR_Msk
4943 #define CAN_ALC_Pos (24U)
4944 #define CAN_ALC_Msk (0x1FUL << CAN_ALC_Pos)
4945 #define CAN_ALC CAN_ALC_Msk
4947 /*************** Bit definition for CAN_NBT **************/
4948 #define CAN_NBT_NBRP_Pos (0U)
4949 #define CAN_NBT_NBRP_Msk (0x3FFUL << CAN_NBT_NBRP_Pos)
4950 #define CAN_NBT_NBRP CAN_NBT_NBRP_Msk
4951 #define CAN_NBT_NSEG1_Pos (10U)
4952 #define CAN_NBT_NSEG1_Msk (0x3FUL << CAN_NBT_NSEG1_Pos)
4953 #define CAN_NBT_NSEG1 CAN_NBT_NSEG1_Msk
4954 #define CAN_NBT_NSEG2_Pos (16U)
4955 #define CAN_NBT_NSEG2_Msk (0xFUL << CAN_NBT_NSEG2_Pos)
4956 #define CAN_NBT_NSEG2 CAN_NBT_NSEG2_Msk
4957 #define CAN_NBT_NSJM_Pos (20U)
4958 #define CAN_NBT_NSJM_Msk (0xFUL << CAN_NBT_NSJM_Pos)
4959 #define CAN_NBT_NSJM CAN_NBT_NSJM_Msk
4961 /*************** Bit definition for CAN_SSPP_TDCR_DBT **************/
4962 #define CAN_DBT_DBRP_Pos (0U)
4963 #define CAN_DBT_DBRP_Msk (0x1FUL << CAN_DBT_DBRP_Pos)
4964 #define CAN_DBT_DBRP CAN_DBT_DBRP_Msk
4965 #define CAN_DBT_DSJW_Pos (5U)
4966 #define CAN_DBT_DSJW_Msk (0x7UL << CAN_DBT_DSJW_Pos)
4967 #define CAN_DBT_DSJW CAN_DBT_DSJW_Msk
4968 #define CAN_DBT_DSEG1_Pos (8U)
4969 #define CAN_DBT_DSEG1_Msk (0x1FUL << CAN_DBT_DSEG1_Pos)
4970 #define CAN_DBT_DSEG1 CAN_DBT_DSEG1_Msk
4971 #define CAN_DBT_DSEG2_Pos (13U)
4972 #define CAN_DBT_DSEG2_Msk (0x7UL << CAN_DBT_DSEG2_Pos)
4973 #define CAN_DBT_DSEG2 CAN_DBT_DSEG2_Msk
4975 #define CAN_TDCR_TDCO_Pos (16U)
4976 #define CAN_TDCR_TDCO_Msk (0x7FUL << CAN_TDCR_TDCO_Pos)
4977 #define CAN_TDCR_TDCO CAN_TDCR_TDCO_Msk
4978 #define CAN_TDCR_TDCEN_Pos (23U)
4979 #define CAN_TDCR_TDCEN_Msk (0x1UL << CAN_TDCR_TDCEN_Pos)
4980 #define CAN_TDCR_TDCEN CAN_TDCR_TDCEN_Msk
4982 #define CAN_SSPP_SSPP_Pos (24U)
4983 #define CAN_SSPP_SSPP_Msk (0x7FUL << CAN_SSPP_SSPP_Pos)
4984 #define CAN_SSPP_SSPP CAN_SSPP_SSPP_Msk
4986 /************* Bit definition for CAN_APERR_DPERR_FDSR_FDCFG ***********/
4987 #define CAN_FDCFG_FDEN_Pos (0U)
4988 #define CAN_FDCFG_FDEN_Msk (0x1UL << CAN_FDCFG_FDEN_Pos)
4989 #define CAN_FDCFG_FDEN CAN_FDCFG_FDEN_Msk
4990 #define CAN_FDCFG_BRSEN_Pos (1U)
4991 #define CAN_FDCFG_BRSEN_Msk (0x1UL << CAN_FDCFG_BRSEN_Pos)
4992 #define CAN_FDCFG_BRSEN CAN_FDCFG_BRSEN_Msk
4993 #define CAN_FDCFG_EXTBT_Pos (2U)
4994 #define CAN_FDCFG_EXTBT_Msk (0x1UL << CAN_FDCFG_EXTBT_Pos)
4995 #define CAN_FDCFG_EXTBT CAN_FDCFG_EXTBT_Msk
4996 #define CAN_FDCFG_ISO_Pos (3U)
4997 #define CAN_FDCFG_ISO_Msk (0x1UL << CAN_FDCFG_ISO_Pos)
4998 #define CAN_FDCFG_ISO CAN_FDCFG_ISO_Msk
4999 #define CAN_FDCFG_DAR_Pos (4U)
5000 #define CAN_FDCFG_DAR_Msk (0x1UL << CAN_FDCFG_DAR_Pos)
5001 #define CAN_FDCFG_DAR CAN_FDCFG_DAR_Msk
5002 #define CAN_FDCFG_REOM_Pos (5U)
5003 #define CAN_FDCFG_REOM_Msk (0x1UL << CAN_FDCFG_REOM_Pos)
5004 #define CAN_FDCFG_REOM CAN_FDCFG_REOM_Msk
5006 #define CAN_FDSTA_BITERR_Pos (8U)
5007 #define CAN_FDSTA_BITERR_Msk (0x1UL << CAN_FDSTA_BITERR_Pos)
5008 #define CAN_FDSTA_BITERR CAN_FDSTA_BITERR_Msk
5009 #define CAN_FDSTA_CRCERR_Pos (9U)
5010 #define CAN_FDSTA_CRCERR_Msk (0x1UL << CAN_FDSTA_CRCERR_Pos)
5011 #define CAN_FDSTA_CRCERR CAN_FDSTA_CRCERR_Msk
5012 #define CAN_FDSTA_FRMERR_Pos (10U)
5013 #define CAN_FDSTA_FRMERR_Msk (0x1UL << CAN_FDSTA_FRMERR_Pos)
5014 #define CAN_FDSTA_FRMERR CAN_FDSTA_FRMERR_Msk
5015 #define CAN_FDSTA_STFERR_Pos (11U)
5016 #define CAN_FDSTA_STFERR_Msk (0x1UL << CAN_FDSTA_STFERR_Pos)
5017 #define CAN_FDSTA_STFERR CAN_FDSTA_STFERR_Msk
5018 #define CAN_FDSTA_STATE_Pos (14U)
5019 #define CAN_FDSTA_STATE_Msk (0x3UL << CAN_FDSTA_STATE_Pos)
5020 #define CAN_FDSTA_STATE CAN_FDSTA_STATE_Msk
5022 #define CAN_DPERR_DPXERR_Pos (16U)
5023 #define CAN_DPERR_DPXERR_Msk (0xFFUL << CAN_DPERR_DPXERR_Pos)
5024 #define CAN_DPERR_DPXERR CAN_DPERR_DPXERR_Msk
5026 #define CAN_APERR_APERR_Pos (24U)
5027 #define CAN_APERR_APERR_Msk (0xFFUL << CAN_APERR_APERR_Pos)
5028 #define CAN_APERR_APERR CAN_APERR_APERR_Msk
5030 /*************** Bit definition for CAN_TEST **************/
5031 #define CAN_TEST_LBEN_Pos (0U)
5032 #define CAN_TEST_LBEN_Msk (0x1UL << CAN_TEST_LBEN_Pos)
5033 #define CAN_TEST_LBEN CAN_TEST_LBEN_Msk
5034 #define CAN_TEST_TXC_Pos (1U)
5035 #define CAN_TEST_TXC_Msk (0x1UL << CAN_TEST_TXC_Pos)
5036 #define CAN_TEST_TXC CAN_TEST_TXC_Msk
5038 /******************************************************************************/
5039 /* */
5040 /* Real-Time Clock (RTC) */
5041 /* */
5042 /******************************************************************************/
5043 
5044 /******************* Bit definition for RTC_CRH register ********************/
5045 #define RTC_CRH_SECIE_Pos (0U)
5046 #define RTC_CRH_SECIE_Msk (0x1UL << RTC_CRH_SECIE_Pos)
5047 #define RTC_CRH_SECIE RTC_CRH_SECIE_Msk
5048 #define RTC_CRH_ALRIE_Pos (1U)
5049 #define RTC_CRH_ALRIE_Msk (0x1UL << RTC_CRH_ALRIE_Pos)
5050 #define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk
5051 #define RTC_CRH_OWIE_Pos (2U)
5052 #define RTC_CRH_OWIE_Msk (0x1UL << RTC_CRH_OWIE_Pos)
5053 #define RTC_CRH_OWIE RTC_CRH_OWIE_Msk
5055 /******************* Bit definition for RTC_CRL register ********************/
5056 #define RTC_CRL_SECF_Pos (0U)
5057 #define RTC_CRL_SECF_Msk (0x1UL << RTC_CRL_SECF_Pos)
5058 #define RTC_CRL_SECF RTC_CRL_SECF_Msk
5059 #define RTC_CRL_ALRF_Pos (1U)
5060 #define RTC_CRL_ALRF_Msk (0x1UL << RTC_CRL_ALRF_Pos)
5061 #define RTC_CRL_ALRF RTC_CRL_ALRF_Msk
5062 #define RTC_CRL_OWF_Pos (2U)
5063 #define RTC_CRL_OWF_Msk (0x1UL << RTC_CRL_OWF_Pos)
5064 #define RTC_CRL_OWF RTC_CRL_OWF_Msk
5065 #define RTC_CRL_RSF_Pos (3U)
5066 #define RTC_CRL_RSF_Msk (0x1UL << RTC_CRL_RSF_Pos)
5067 #define RTC_CRL_RSF RTC_CRL_RSF_Msk
5068 #define RTC_CRL_CNF_Pos (4U)
5069 #define RTC_CRL_CNF_Msk (0x1UL << RTC_CRL_CNF_Pos)
5070 #define RTC_CRL_CNF RTC_CRL_CNF_Msk
5071 #define RTC_CRL_RTOFF_Pos (5U)
5072 #define RTC_CRL_RTOFF_Msk (0x1UL << RTC_CRL_RTOFF_Pos)
5073 #define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk
5075 /******************* Bit definition for RTC_PRLH register *******************/
5076 #define RTC_PRLH_PRL_Pos (0U)
5077 #define RTC_PRLH_PRL_Msk (0xFUL << RTC_PRLH_PRL_Pos)
5078 #define RTC_PRLH_PRL RTC_PRLH_PRL_Msk
5080 /******************* Bit definition for RTC_PRLL register *******************/
5081 #define RTC_PRLL_PRL_Pos (0U)
5082 #define RTC_PRLL_PRL_Msk (0xFFFFUL << RTC_PRLL_PRL_Pos)
5083 #define RTC_PRLL_PRL RTC_PRLL_PRL_Msk
5085 /******************* Bit definition for RTC_DIVH register *******************/
5086 #define RTC_DIVH_RTC_DIV_Pos (0U)
5087 #define RTC_DIVH_RTC_DIV_Msk (0xFUL << RTC_DIVH_RTC_DIV_Pos)
5088 #define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk
5090 /******************* Bit definition for RTC_DIVL register *******************/
5091 #define RTC_DIVL_RTC_DIV_Pos (0U)
5092 #define RTC_DIVL_RTC_DIV_Msk (0xFFFFUL << RTC_DIVL_RTC_DIV_Pos)
5093 #define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk
5095 /******************* Bit definition for RTC_CNTH register *******************/
5096 #define RTC_CNTH_RTC_CNT_Pos (0U)
5097 #define RTC_CNTH_RTC_CNT_Msk (0xFFFFUL << RTC_CNTH_RTC_CNT_Pos)
5098 #define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk
5100 /******************* Bit definition for RTC_CNTL register *******************/
5101 #define RTC_CNTL_RTC_CNT_Pos (0U)
5102 #define RTC_CNTL_RTC_CNT_Msk (0xFFFFUL << RTC_CNTL_RTC_CNT_Pos)
5103 #define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk
5105 /******************* Bit definition for RTC_ALRH register *******************/
5106 #define RTC_ALRH_RTC_ALR_Pos (0U)
5107 #define RTC_ALRH_RTC_ALR_Msk (0xFFFFUL << RTC_ALRH_RTC_ALR_Pos)
5108 #define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk
5110 /******************* Bit definition for RTC_ALRL register *******************/
5111 #define RTC_ALRL_RTC_ALR_Pos (0U)
5112 #define RTC_ALRL_RTC_ALR_Msk (0xFFFFUL << RTC_ALRL_RTC_ALR_Pos)
5113 #define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk
5115 /******************************************************************************/
5116 /* */
5117 /* Independent WATCHDOG (IWDG) */
5118 /* */
5119 /******************************************************************************/
5120 
5121 /******************* Bit definition for IWDG_KR register ********************/
5122 #define IWDG_KR_KEY_Pos (0U)
5123 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
5124 #define IWDG_KR_KEY IWDG_KR_KEY_Msk
5126 /******************* Bit definition for IWDG_PR register ********************/
5127 #define IWDG_PR_PR_Pos (0U)
5128 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
5129 #define IWDG_PR_PR IWDG_PR_PR_Msk
5130 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
5131 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
5132 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
5134 /******************* Bit definition for IWDG_RLR register *******************/
5135 #define IWDG_RLR_RL_Pos (0U)
5136 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
5137 #define IWDG_RLR_RL IWDG_RLR_RL_Msk
5139 /******************* Bit definition for IWDG_SR register ********************/
5140 #define IWDG_SR_PVU_Pos (0U)
5141 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
5142 #define IWDG_SR_PVU IWDG_SR_PVU_Msk
5143 #define IWDG_SR_RVU_Pos (1U)
5144 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
5145 #define IWDG_SR_RVU IWDG_SR_RVU_Msk
5147 /******************************************************************************/
5148 /* */
5149 /* Window WATCHDOG (WWDG) */
5150 /* */
5151 /******************************************************************************/
5152 
5153 /******************* Bit definition for WWDG_CR register ********************/
5154 #define WWDG_CR_T_Pos (0U)
5155 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
5156 #define WWDG_CR_T WWDG_CR_T_Msk
5157 #define WWDG_CR_T0 (0x01UL << WWDG_CR_T_Pos)
5158 #define WWDG_CR_T1 (0x02UL << WWDG_CR_T_Pos)
5159 #define WWDG_CR_T2 (0x04UL << WWDG_CR_T_Pos)
5160 #define WWDG_CR_T3 (0x08UL << WWDG_CR_T_Pos)
5161 #define WWDG_CR_T4 (0x10UL << WWDG_CR_T_Pos)
5162 #define WWDG_CR_T5 (0x20UL << WWDG_CR_T_Pos)
5163 #define WWDG_CR_T6 (0x40UL << WWDG_CR_T_Pos)
5165 #define WWDG_CR_WDGA_Pos (7U)
5166 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
5167 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
5169 /******************* Bit definition for WWDG_CFR register *******************/
5170 #define WWDG_CFR_W_Pos (0U)
5171 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
5172 #define WWDG_CFR_W WWDG_CFR_W_Msk
5173 #define WWDG_CFR_W0 (0x01UL << WWDG_CFR_W_Pos)
5174 #define WWDG_CFR_W1 (0x02UL << WWDG_CFR_W_Pos)
5175 #define WWDG_CFR_W2 (0x04UL << WWDG_CFR_W_Pos)
5176 #define WWDG_CFR_W3 (0x08UL << WWDG_CFR_W_Pos)
5177 #define WWDG_CFR_W4 (0x10UL << WWDG_CFR_W_Pos)
5178 #define WWDG_CFR_W5 (0x20UL << WWDG_CFR_W_Pos)
5179 #define WWDG_CFR_W6 (0x40UL << WWDG_CFR_W_Pos)
5181 #define WWDG_CFR_WDGTB_Pos (7U)
5182 #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
5183 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
5184 #define WWDG_CFR_WDGTB0 (0x1UL << WWDG_CFR_WDGTB_Pos)
5185 #define WWDG_CFR_WDGTB1 (0x2UL << WWDG_CFR_WDGTB_Pos)
5187 #define WWDG_CFR_EWI_Pos (9U)
5188 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
5189 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
5191 /******************* Bit definition for WWDG_SR register ********************/
5192 #define WWDG_SR_EWIF_Pos (0U)
5193 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
5194 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
5196 /******************************************************************************/
5197 /* */
5198 /* Quad-SPI Interface (QSPI) */
5199 /* */
5200 /******************************************************************************/
5201 
5202 /***************** Bit definition for QUADSPI_CR register *******************/
5203 #define QUADSPI_CR_EN_Pos (0U)
5204 #define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos)
5205 #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk
5206 #define QUADSPI_CR_ABORT_Pos (1U)
5207 #define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos)
5208 #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk
5209 #define QUADSPI_CR_DMAEN_Pos (2U)
5210 #define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos)
5211 #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk
5212 #define QUADSPI_CR_TCEN_Pos (3U)
5213 #define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos)
5214 #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk
5215 #define QUADSPI_CR_SSHIFT_Pos (4U)
5216 #define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos)
5217 #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk
5218 #define QUADSPI_CR_DFM_Pos (6U)
5219 #define QUADSPI_CR_DFM_Msk (0x1U << QUADSPI_CR_DFM_Pos)
5220 #define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk
5221 #define QUADSPI_CR_FSEL_Pos (7U)
5222 #define QUADSPI_CR_FSEL_Msk (0x1U << QUADSPI_CR_FSEL_Pos)
5223 #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk
5224 #define QUADSPI_CR_FTHRES_Pos (8U)
5225 #define QUADSPI_CR_FTHRES_Msk (0xFU << QUADSPI_CR_FTHRES_Pos)
5226 #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk
5227 #define QUADSPI_CR_FTHRES_0 (0x1U << QUADSPI_CR_FTHRES_Pos)
5228 #define QUADSPI_CR_FTHRES_1 (0x2U << QUADSPI_CR_FTHRES_Pos)
5229 #define QUADSPI_CR_FTHRES_2 (0x4U << QUADSPI_CR_FTHRES_Pos)
5230 #define QUADSPI_CR_FTHRES_3 (0x8U << QUADSPI_CR_FTHRES_Pos)
5231 #define QUADSPI_CR_TEIE_Pos (16U)
5232 #define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos)
5233 #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk
5234 #define QUADSPI_CR_TCIE_Pos (17U)
5235 #define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos)
5236 #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk
5237 #define QUADSPI_CR_FTIE_Pos (18U)
5238 #define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos)
5239 #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk
5240 #define QUADSPI_CR_SMIE_Pos (19U)
5241 #define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos)
5242 #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk
5243 #define QUADSPI_CR_TOIE_Pos (20U)
5244 #define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos)
5245 #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk
5246 #define QUADSPI_CR_APMS_Pos (22U)
5247 #define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos)
5248 #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk
5249 #define QUADSPI_CR_PMM_Pos (23U)
5250 #define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos)
5251 #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk
5252 #define QUADSPI_CR_PRESCALER_Pos (24U)
5253 #define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos)
5254 #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk
5255 #define QUADSPI_CR_PRESCALER_0 (0x01U << QUADSPI_CR_PRESCALER_Pos)
5256 #define QUADSPI_CR_PRESCALER_1 (0x02U << QUADSPI_CR_PRESCALER_Pos)
5257 #define QUADSPI_CR_PRESCALER_2 (0x04U << QUADSPI_CR_PRESCALER_Pos)
5258 #define QUADSPI_CR_PRESCALER_3 (0x08U << QUADSPI_CR_PRESCALER_Pos)
5259 #define QUADSPI_CR_PRESCALER_4 (0x10U << QUADSPI_CR_PRESCALER_Pos)
5260 #define QUADSPI_CR_PRESCALER_5 (0x20U << QUADSPI_CR_PRESCALER_Pos)
5261 #define QUADSPI_CR_PRESCALER_6 (0x40U << QUADSPI_CR_PRESCALER_Pos)
5262 #define QUADSPI_CR_PRESCALER_7 (0x80U << QUADSPI_CR_PRESCALER_Pos)
5264 /***************** Bit definition for QUADSPI_DCR register ******************/
5265 #define QUADSPI_DCR_CKMODE_Pos (0U)
5266 #define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos)
5267 #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk
5268 #define QUADSPI_DCR_CSHT_Pos (8U)
5269 #define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos)
5270 #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk
5271 #define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos)
5272 #define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos)
5273 #define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos)
5274 #define QUADSPI_DCR_FSIZE_Pos (16U)
5275 #define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos)
5276 #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk
5277 #define QUADSPI_DCR_FSIZE_0 (0x01U << QUADSPI_DCR_FSIZE_Pos)
5278 #define QUADSPI_DCR_FSIZE_1 (0x02U << QUADSPI_DCR_FSIZE_Pos)
5279 #define QUADSPI_DCR_FSIZE_2 (0x04U << QUADSPI_DCR_FSIZE_Pos)
5280 #define QUADSPI_DCR_FSIZE_3 (0x08U << QUADSPI_DCR_FSIZE_Pos)
5281 #define QUADSPI_DCR_FSIZE_4 (0x10U << QUADSPI_DCR_FSIZE_Pos)
5283 /****************** Bit definition for QUADSPI_SR register *******************/
5284 #define QUADSPI_SR_TEF_Pos (0U)
5285 #define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos)
5286 #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk
5287 #define QUADSPI_SR_TCF_Pos (1U)
5288 #define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos)
5289 #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk
5290 #define QUADSPI_SR_FTF_Pos (2U)
5291 #define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos)
5292 #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk
5293 #define QUADSPI_SR_SMF_Pos (3U)
5294 #define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos)
5295 #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk
5296 #define QUADSPI_SR_TOF_Pos (4U)
5297 #define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos)
5298 #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk
5299 #define QUADSPI_SR_BUSY_Pos (5U)
5300 #define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos)
5301 #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk
5302 #define QUADSPI_SR_FLEVEL_Pos (8U)
5303 #define QUADSPI_SR_FLEVEL_Msk (0x1FU << QUADSPI_SR_FLEVEL_Pos)
5304 #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk
5305 #define QUADSPI_SR_FLEVEL_0 (0x01U << QUADSPI_SR_FLEVEL_Pos)
5306 #define QUADSPI_SR_FLEVEL_1 (0x02U << QUADSPI_SR_FLEVEL_Pos)
5307 #define QUADSPI_SR_FLEVEL_2 (0x04U << QUADSPI_SR_FLEVEL_Pos)
5308 #define QUADSPI_SR_FLEVEL_3 (0x08U << QUADSPI_SR_FLEVEL_Pos)
5309 #define QUADSPI_SR_FLEVEL_4 (0x10U << QUADSPI_SR_FLEVEL_Pos)
5310 #define QUADSPI_SR_FLEVEL_5 (0x20U << QUADSPI_SR_FLEVEL_Pos)
5311 #define QUADSPI_SR_FLEVEL_6 (0x30U << QUADSPI_SR_FLEVEL_Pos)
5313 /****************** Bit definition for QUADSPI_FCR register ******************/
5314 #define QUADSPI_FCR_CTEF_Pos (0U)
5315 #define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos)
5316 #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk
5317 #define QUADSPI_FCR_CTCF_Pos (1U)
5318 #define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos)
5319 #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk
5320 #define QUADSPI_FCR_CSMF_Pos (3U)
5321 #define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos)
5322 #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk
5323 #define QUADSPI_FCR_CTOF_Pos (4U)
5324 #define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos)
5325 #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk
5327 /****************** Bit definition for QUADSPI_DLR register ******************/
5328 #define QUADSPI_DLR_DL_Pos (0U)
5329 #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos)
5330 #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk
5332 /****************** Bit definition for QUADSPI_CCR register ******************/
5333 #define QUADSPI_CCR_INSTRUCTION_Pos (0U)
5334 #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos)
5335 #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk
5336 #define QUADSPI_CCR_INSTRUCTION_0 (0x01U << QUADSPI_CCR_INSTRUCTION_Pos)
5337 #define QUADSPI_CCR_INSTRUCTION_1 (0x02U << QUADSPI_CCR_INSTRUCTION_Pos)
5338 #define QUADSPI_CCR_INSTRUCTION_2 (0x04U << QUADSPI_CCR_INSTRUCTION_Pos)
5339 #define QUADSPI_CCR_INSTRUCTION_3 (0x08U << QUADSPI_CCR_INSTRUCTION_Pos)
5340 #define QUADSPI_CCR_INSTRUCTION_4 (0x10U << QUADSPI_CCR_INSTRUCTION_Pos)
5341 #define QUADSPI_CCR_INSTRUCTION_5 (0x20U << QUADSPI_CCR_INSTRUCTION_Pos)
5342 #define QUADSPI_CCR_INSTRUCTION_6 (0x40U << QUADSPI_CCR_INSTRUCTION_Pos)
5343 #define QUADSPI_CCR_INSTRUCTION_7 (0x80U << QUADSPI_CCR_INSTRUCTION_Pos)
5344 #define QUADSPI_CCR_IMODE_Pos (8U)
5345 #define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos)
5346 #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk
5347 #define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos)
5348 #define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos)
5349 #define QUADSPI_CCR_ADMODE_Pos (10U)
5350 #define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos)
5351 #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk
5352 #define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos)
5353 #define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos)
5354 #define QUADSPI_CCR_ADSIZE_Pos (12U)
5355 #define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos)
5356 #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk
5357 #define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos)
5358 #define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos)
5359 #define QUADSPI_CCR_ABMODE_Pos (14U)
5360 #define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos)
5361 #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk
5362 #define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos)
5363 #define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos)
5364 #define QUADSPI_CCR_ABSIZE_Pos (16U)
5365 #define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos)
5366 #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk
5367 #define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos)
5368 #define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos)
5369 #define QUADSPI_CCR_DCYC_Pos (18U)
5370 #define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos)
5371 #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk
5372 #define QUADSPI_CCR_DCYC_0 (0x01U << QUADSPI_CCR_DCYC_Pos)
5373 #define QUADSPI_CCR_DCYC_1 (0x02U << QUADSPI_CCR_DCYC_Pos)
5374 #define QUADSPI_CCR_DCYC_2 (0x04U << QUADSPI_CCR_DCYC_Pos)
5375 #define QUADSPI_CCR_DCYC_3 (0x08U << QUADSPI_CCR_DCYC_Pos)
5376 #define QUADSPI_CCR_DCYC_4 (0x10U << QUADSPI_CCR_DCYC_Pos)
5377 #define QUADSPI_CCR_DMODE_Pos (24U)
5378 #define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos)
5379 #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk
5380 #define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos)
5381 #define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos)
5382 #define QUADSPI_CCR_FMODE_Pos (26U)
5383 #define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos)
5384 #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk
5385 #define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos)
5386 #define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos)
5387 #define QUADSPI_CCR_SIOO_Pos (28U)
5388 #define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos)
5389 #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk
5390 #define QUADSPI_CCR_DHHC_Pos (30U)
5391 #define QUADSPI_CCR_DHHC_Msk (0x1U << QUADSPI_CCR_DHHC_Pos)
5392 #define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk
5393 #define QUADSPI_CCR_DDRM_Pos (31U)
5394 #define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos)
5395 #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk
5397 /****************** Bit definition for QUADSPI_AR register *******************/
5398 #define QUADSPI_AR_ADDRESS_Pos (0U)
5399 #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos)
5400 #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk
5402 /****************** Bit definition for QUADSPI_ABR register ******************/
5403 #define QUADSPI_ABR_ALTERNATE_Pos (0U)
5404 #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos)
5405 #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk
5407 /****************** Bit definition for QUADSPI_DR register *******************/
5408 #define QUADSPI_DR_DATA_Pos (0U)
5409 #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos)
5410 #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk
5412 /****************** Bit definition for QUADSPI_PSMKR register ****************/
5413 #define QUADSPI_PSMKR_MASK_Pos (0U)
5414 #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos)
5415 #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk
5417 /****************** Bit definition for QUADSPI_PSMAR register ****************/
5418 #define QUADSPI_PSMAR_MATCH_Pos (0U)
5419 #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos)
5420 #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk
5422 /****************** Bit definition for QUADSPI_PIR register *****************/
5423 #define QUADSPI_PIR_INTERVAL_Pos (0U)
5424 #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos)
5425 #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk
5427 /****************** Bit definition for QUADSPI_LPTR register *****************/
5428 #define QUADSPI_LPTR_TIMEOUT_Pos (0U)
5429 #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos)
5430 #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk
5432 /******************************************************************************/
5433 /* */
5434 /* SD host Interface (SDIO) */
5435 /* */
5436 /******************************************************************************/
5437 
5438 /****************** Bit definition for SDIO_CTRL register ******************/
5439 #define SDIO_CTRL_CTRL_RST_Pos (0U)
5440 #define SDIO_CTRL_CTRL_RST_Msk (0x1U << SDIO_CTRL_CTRL_RST_Pos)
5441 #define SDIO_CTRL_CTRL_RST SDIO_CTRL_CTRL_RST_Msk
5442 #define SDIO_CTRL_FIFO_RST_Pos (1U)
5443 #define SDIO_CTRL_FIFO_RST_Msk (0x1U << SDIO_CTRL_FIFO_RST_Pos)
5444 #define SDIO_CTRL_FIFO_RST SDIO_CTRL_FIFO_RST_Msk
5445 #define SDIO_CTRL_DMA_RST_Pos (2U)
5446 #define SDIO_CTRL_DMA_RST_Msk (0x1U << SDIO_CTRL_DMA_RST_Pos)
5447 #define SDIO_CTRL_DMA_RST SDIO_CTRL_DMA_RST_Msk
5448 #define SDIO_CTRL_INT_ENABLE_Pos (4U)
5449 #define SDIO_CTRL_INT_ENABLE_Msk (0x1U << SDIO_CTRL_INT_ENABLE_Pos)
5450 #define SDIO_CTRL_INT_ENABLE SDIO_CTRL_INT_ENABLE_Msk
5451 #define SDIO_CTRL_DMA_ENABLE_Pos (5U)
5452 #define SDIO_CTRL_DMA_ENABLE_Msk (0x1U << SDIO_CTRL_DMA_ENABLE_Pos)
5453 #define SDIO_CTRL_DMA_ENABLE SDIO_CTRL_DMA_ENABLE_Msk
5454 #define SDIO_CTRL_READ_WAIT_Pos (6U)
5455 #define SDIO_CTRL_READ_WAIT_Msk (0x1U << SDIO_CTRL_READ_WAIT_Pos)
5456 #define SDIO_CTRL_READ_WAIT SDIO_CTRL_READ_WAIT_Msk
5457 #define SDIO_CTRL_SEND_IRQ_RESP_Pos (7U)
5458 #define SDIO_CTRL_SEND_IRQ_RESP_Msk (0x1U << SDIO_CTRL_SEND_IRQ_RESP_Pos)
5459 #define SDIO_CTRL_SEND_IRQ_RESP SDIO_CTRL_SEND_IRQ_RESP_Msk
5460 #define SDIO_CTRL_ABORT_READ_DATA_Pos (8U)
5461 #define SDIO_CTRL_ABORT_READ_DATA_Msk (0x1U << SDIO_CTRL_ABORT_READ_DATA_Pos)
5462 #define SDIO_CTRL_ABORT_READ_DATA SDIO_CTRL_ABORT_READ_DATA_Msk
5463 #define SDIO_CTRL_CEATA_INT_STAT_Pos (11U)
5464 #define SDIO_CTRL_CEATA_INT_STAT_Msk (0x1U << SDIO_CTRL_CEATA_INT_STAT_Pos)
5465 #define SDIO_CTRL_CEATA_INT_STAT SDIO_CTRL_CEATA_INT_STAT_Msk
5466 #define SDIO_CTRL_CARD_VLTG_A_Pos (16U)
5467 #define SDIO_CTRL_CARD_VLTG_A_Msk (0xFU << SDIO_CTRL_CARD_VLTG_A_Pos)
5468 #define SDIO_CTRL_CARD_VLTG_A SDIO_CTRL_CARD_VLTG_A_Msk
5469 #define SDIO_CTRL_CARD_VLTG_B_Pos (20U)
5470 #define SDIO_CTRL_CARD_VLTG_B_Msk (0xFU << SDIO_CTRL_CARD_VLTG_B_Pos)
5471 #define SDIO_CTRL_CARD_VLTG_B SDIO_CTRL_CARD_VLTG_B_Msk
5472 #define SDIO_CTRL_EN_OD_Pos (24U)
5473 #define SDIO_CTRL_EN_OD_Msk (0x1U << SDIO_CTRL_EN_OD_Pos)
5474 #define SDIO_CTRL_EN_OD SDIO_CTRL_EN_OD_Msk
5475 #define SDIO_CTRL_INTERNAL_DMAC_Pos (25U)
5476 #define SDIO_CTRL_INTERNAL_DMAC_Msk (0x1U << SDIO_CTRL_INTERNAL_DMAC_Pos)
5477 #define SDIO_CTRL_INTERNAL_DMAC SDIO_CTRL_INTERNAL_DMAC_Msk
5478 
5479 /******************* Bit definition for SDIO_CLKDIV register *******************/
5480 #define SDIO_CLKDIV_DIVIDER_Pos (0U)
5481 #define SDIO_CLKDIV_DIVIDER_Msk (0xFFU << SDIO_CLKDIV_DIVIDER_Pos)
5482 #define SDIO_CLKDIV_DIVIDER SDIO_CLKDIV_DIVIDER_Msk
5483 
5484 /******************* Bit definition for SDIO_CLKENA register *******************/
5485 #define SDIO_CLKENA_CLK_ENABLE_Pos (0U)
5486 #define SDIO_CLKENA_CLK_ENABLE_Msk (0x1U << SDIO_CLKENA_CLK_ENABLE_Pos)
5487 #define SDIO_CLKENA_CLK_ENABLE SDIO_CLKENA_CLK_ENABLE_Msk
5488 
5489 #define SDIO_CLKENA_LOW_POWER_Pos (16U)
5490 #define SDIO_CLKENA_LOW_POWER_Msk (0x1U << SDIO_CLKENA_LOW_POWER_Pos)
5491 #define SDIO_CLKENA_LOW_POWER SDIO_CLKENA_LOW_POWER_Msk
5492 
5493 /******************* Bit definition for SDIO_TIMOUT register *******************/
5494 #define SDIO_TIMOUT_DATA_TIMOUT_Pos (0U)
5495 #define SDIO_TIMOUT_DATA_TIMOUT_Msk (0xFFU << SDIO_TIMOUT_DATA_TIMOUT_Pos)
5496 #define SDIO_TIMOUT_DATA_TIMOUT SDIO_TIMOUT_DATA_TIMOUT_Msk
5497 
5498 #define SDIO_TIMOUT_RESPONSE_TIMOUT_Pos (8U)
5499 #define SDIO_TIMOUT_RESPONSE_TIMOUT_Msk (0xFFFFFFU << SDIO_TIMOUT_RESPONSE_TIMOUT_Pos)
5500 #define SDIO_TIMOUT_RESPONSE_TIMOUT SDIO_TIMOUT_RESPONSE_TIMOUT_Msk
5501 
5502 /******************* Bit definition for SDIO_WIDTH register *******************/
5503 #define SDIO_CTYPE_WIDTH0_Pos (0U)
5504 #define SDIO_CTYPE_WIDTH0_Msk (0x1U << SDIO_CTYPE_WIDTH0_Pos)
5505 #define SDIO_CTYPE_WIDTH0 SDIO_CTYPE_WIDTH0_Msk
5506 
5507 #define SDIO_CTYPE_WIDTH1_Pos (16U)
5508 #define SDIO_CTYPE_WIDTH1_Msk (0x1U << SDIO_CTYPE_WIDTH1_Pos)
5509 #define SDIO_CTYPE_WIDTH1 SDIO_CTYPE_WIDTH1_Msk
5510 
5511 /******************* Bit definition for SDIO_BLKSIZE register *******************/
5512 #define SDIO_BLKSIZE_BLOCKSIZE_Pos (0U)
5513 #define SDIO_BLKSIZE_BLOCKSIZE_Msk (0xFFFFU << SDIO_BLKSIZE_BLOCKSIZE_Pos)
5514 #define SDIO_BLKSIZE_BLOCKSIZE SDIO_BLKSIZE_BLOCKSIZE_Msk
5515 
5516 /******************* Bit definition for SDIO_BYTCNT register *******************/
5517 #define SDIO_BYTCNT_BYTECOUNT_Pos (0U)
5518 #define SDIO_BYTCNT_BYTECOUNT_Msk (0xFFFFFFFFU << SDIO_BYTCNT_BYTECOUNT_Pos)
5519 #define SDIO_BYTCNT_BYTECOUNT SDIO_BYTCNT_BYTECOUNT_Msk
5520 
5521 /******************* Bit definition for SDIO_INTMASK register *******************/
5522 #define SDIO_INTMASK_CARDDETECT_Pos (0U)
5523 #define SDIO_INTMASK_CARDDETECT_Msk (0x1U << SDIO_INTMASK_CARDDETECT_Pos)
5524 #define SDIO_INTMASK_CARDDETECT SDIO_INTMASK_CARDDETECT_Msk
5525 #define SDIO_INTMASK_RESPERR_Pos (1U)
5526 #define SDIO_INTMASK_RESPERR_Msk (0x1U << SDIO_INTMASK_RESPERR_Pos)
5527 #define SDIO_INTMASK_RESPERR SDIO_INTMASK_RESPERR_Msk
5528 #define SDIO_INTMASK_CMDDONE_Pos (2U)
5529 #define SDIO_INTMASK_CMDDONE_Msk (0x1U << SDIO_INTMASK_CMDDONE_Pos)
5530 #define SDIO_INTMASK_CMDDONE SDIO_INTMASK_CMDDONE_Msk
5531 #define SDIO_INTMASK_DTRANSFEROVER_Pos (3U)
5532 #define SDIO_INTMASK_DTRANSFEROVER_Msk (0x1U << SDIO_INTMASK_DTRANSFEROVER_Pos)
5533 #define SDIO_INTMASK_DTRANSFEROVER SDIO_INTMASK_DTRANSFEROVER_Msk
5534 #define SDIO_INTMASK_TXDATAREQ_Pos (4U)
5535 #define SDIO_INTMASK_TXDATAREQ_Msk (0x1U << SDIO_INTMASK_TXDATAREQ_Pos)
5536 #define SDIO_INTMASK_TXDATAREQ SDIO_INTMASK_TXDATAREQ_Msk
5537 #define SDIO_INTMASK_RXDATAREQ_Pos (5U)
5538 #define SDIO_INTMASK_RXDATAREQ_Msk (0x1U << SDIO_INTMASK_RXDATAREQ_Pos)
5539 #define SDIO_INTMASK_RXDATAREQ SDIO_INTMASK_RXDATAREQ_Msk
5540 #define SDIO_INTMASK_RESPCRCERR_Pos (6U)
5541 #define SDIO_INTMASK_RESPCRCERR_Msk (0x1U << SDIO_INTMASK_RESPCRCERR_Pos)
5542 #define SDIO_INTMASK_RESPCRCERR SDIO_INTMASK_RESPCRCERR_Msk
5543 #define SDIO_INTMASK_DATACRCERR_Pos (7U)
5544 #define SDIO_INTMASK_DATACRCERR_Msk (0x1U << SDIO_INTMASK_DATACRCERR_Pos)
5545 #define SDIO_INTMASK_DATACRCERR SDIO_INTMASK_DATACRCERR_Msk
5546 #define SDIO_INTMASK_RESPTIMEOUT_Pos (8U)
5547 #define SDIO_INTMASK_RESPTIMEOUT_Msk (0x1U << SDIO_INTMASK_RESPTIMEOUT_Pos)
5548 #define SDIO_INTMASK_RESPTIMEOUT SDIO_INTMASK_RESPTIMEOUT_Msk
5549 #define SDIO_INTMASK_DATATIMEOUT_Pos (9U)
5550 #define SDIO_INTMASK_DATATIMEOUT_Msk (0x1U << SDIO_INTMASK_DATATIMEOUT_Pos)
5551 #define SDIO_INTMASK_DATATIMEOUT SDIO_INTMASK_DATATIMEOUT_Msk
5552 #define SDIO_INTMASK_DATASTARV_Pos (10U)
5553 #define SDIO_INTMASK_DATASTARV_Msk (0x1U << SDIO_INTMASK_DATASTARV_Pos)
5554 #define SDIO_INTMASK_DATASTARV SDIO_INTMASK_DATASTARV_Msk
5555 #define SDIO_INTMASK_UNDER_OVER_RUN_Pos (11U)
5556 #define SDIO_INTMASK_UNDER_OVER_RUN_Msk (0x1U << SDIO_INTMASK_UNDER_OVER_RUN_Pos)
5557 #define SDIO_INTMASK_UNDER_OVER_RUN SDIO_INTMASK_UNDER_OVER_RUN_Msk
5558 #define SDIO_INTMASK_HLE_Pos (12U)
5559 #define SDIO_INTMASK_HLE_Msk (0x1U << SDIO_INTMASK_HLE_Pos)
5560 #define SDIO_INTMASK_HLE SDIO_INTMASK_HLE_Msk
5561 #define SDIO_INTMASK_STARTERROR_Pos (13U)
5562 #define SDIO_INTMASK_STARTERROR_Msk (0x1U << SDIO_INTMASK_STARTERROR_Pos)
5563 #define SDIO_INTMASK_STARTERROR SDIO_INTMASK_STARTERROR_Msk
5564 #define SDIO_INTMASK_BUSYCLEAR_Pos (13U)
5565 #define SDIO_INTMASK_BUSYCLEAR_Msk (0x1U << SDIO_INTMASK_BUSYCLEAR_Pos)
5566 #define SDIO_INTMASK_BUSYCLEAR SDIO_INTMASK_BUSYCLEAR_Msk
5567 #define SDIO_INTMASK_AUTOCMDDONE_Pos (14U)
5568 #define SDIO_INTMASK_AUTOCMDDONE_Msk (0x1U << SDIO_INTMASK_AUTOCMDDONE_Pos)
5569 #define SDIO_INTMASK_AUTOCMDDONE SDIO_INTMASK_AUTOCMDDONE_Msk
5570 #define SDIO_INTMASK_ENDERROR_Pos (15U)
5571 #define SDIO_INTMASK_ENDERROR_Msk (0x1U << SDIO_INTMASK_ENDERROR_Pos)
5572 #define SDIO_INTMASK_ENDERROR SDIO_INTMASK_ENDERROR_Msk
5573 #define SDIO_INTMASK_SDIOIT_Pos (16U)
5574 #define SDIO_INTMASK_SDIOIT_Msk (0xFFFFU << SDIO_INTMASK_SDIOIT_Pos)
5575 #define SDIO_INTMASK_SDIOIT SDIO_INTMASK_SDIOIT_Msk
5576 
5577 /******************* Bit definition for SDIO_CMDARG register *******************/
5578 #define SDIO_CMD_CMDARG_Pos (0U)
5579 #define SDIO_CMD_CMDARG_Msk (0xFFFFFFFFU << SDIO_CMD_CMDARG_Pos)
5580 #define SDIO_CMD_CMDARG SDIO_CMD_CMDARG_Msk
5581 
5582 /******************* Bit definition for SDIO_CMD register *******************/
5583 #define SDIO_CMD_CMDINDEX_Pos (0U)
5584 #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos)
5585 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk
5586 #define SDIO_CMD_RESP_EXPECT_Pos (6U)
5587 #define SDIO_CMD_RESP_EXPECT_Msk (0x1U << SDIO_CMD_RESP_EXPECT_Pos)
5588 #define SDIO_CMD_RESP_EXPECT SDIO_CMD_RESP_EXPECT_Msk
5589 #define SDIO_CMD_RESP_LENGTH_Pos (7U)
5590 #define SDIO_CMD_RESP_LENGTH_Msk (0x1U << SDIO_CMD_RESP_LENGTH_Pos)
5591 #define SDIO_CMD_RESP_LENGTH SDIO_CMD_RESP_LENGTH_Msk
5592 #define SDIO_CMD_CHECK_RESP_CRC_Pos (8U)
5593 #define SDIO_CMD_CHECK_RESP_CRC_Msk (0x1U << SDIO_CMD_CHECK_RESP_CRC_Pos)
5594 #define SDIO_CMD_CHECK_RESP_CRC SDIO_CMD_CHECK_RESP_CRC_Msk
5595 #define SDIO_CMD_DATA_EXPECT_Pos (9U)
5596 #define SDIO_CMD_DATA_EXPECT_Msk (0x1U << SDIO_CMD_DATA_EXPECT_Pos)
5597 #define SDIO_CMD_DATA_EXPECT SDIO_CMD_DATA_EXPECT_Msk
5598 #define SDIO_CMD_READ_WRITE_Pos (10U)
5599 #define SDIO_CMD_READ_WRITE_Msk (0x1U << SDIO_CMD_READ_WRITE_Pos)
5600 #define SDIO_CMD_READ_WRITE SDIO_CMD_READ_WRITE_Msk
5601 #define SDIO_CMD_TRANSFER_MODE_Pos (11U)
5602 #define SDIO_CMD_TRANSFER_MODE_Msk (0x1U << SDIO_CMD_TRANSFER_MODE_Pos)
5603 #define SDIO_CMD_TRANSFER_MODE SDIO_CMD_TRANSFER_MODE_Msk
5604 #define SDIO_CMD_SEND_AUTO_STOP_Pos (12U)
5605 #define SDIO_CMD_SEND_AUTO_STOP_Msk (0x1U << SDIO_CMD_SEND_AUTO_STOP_Pos)
5606 #define SDIO_CMD_SEND_AUTO_STOP SDIO_CMD_SEND_AUTO_STOP_Msk
5607 #define SDIO_CMD_WAIT_PRV_COMPLT_Pos (13U)
5608 #define SDIO_CMD_WAIT_PRV_COMPLT_Msk (0x1U << SDIO_CMD_WAIT_PRV_COMPLT_Pos)
5609 #define SDIO_CMD_WAIT_PRV_COMPLT SDIO_CMD_WAIT_PRV_COMPLT_Msk
5610 #define SDIO_CMD_STOP_ABORT_CMD_Pos (14U)
5611 #define SDIO_CMD_STOP_ABORT_CMD_Msk (0x1U << SDIO_CMD_STOP_ABORT_CMD_Pos)
5612 #define SDIO_CMD_STOP_ABORT_CMD SDIO_CMD_STOP_ABORT_CMD_Msk
5613 #define SDIO_CMD_SEND_INITIALIZATION_Pos (15U)
5614 #define SDIO_CMD_SEND_INITIALIZATION_Msk (0x1U << SDIO_CMD_SEND_INITIALIZATION_Pos)
5615 #define SDIO_CMD_SEND_INITIALIZATION SDIO_CMD_SEND_INITIALIZATION_Msk
5616 
5617 /****************** Bit definition for SDIO_MINISTS register ********************/
5618 #define SDIO_MINISTS_CARDDETECT_Pos (0U)
5619 #define SDIO_MINISTS_CARDDETECT_Msk (0x1U << SDIO_MINISTS_CARDDETECT_Pos)
5620 #define SDIO_MINISTS_CARDDETECT SDIO_MINISTS_CARDDETECT_Msk
5621 #define SDIO_MINISTS_RESPERR_Pos (1U)
5622 #define SDIO_MINISTS_RESPERR_Msk (0x1U << SDIO_MINISTS_RESPERR_Pos)
5623 #define SDIO_MINISTS_RESPERR SDIO_MINISTS_RESPERR_Msk
5624 #define SDIO_MINISTS_CMDDONE_Pos (2U)
5625 #define SDIO_MINISTS_CMDDONE_Msk (0x1U << SDIO_MINISTS_CMDDONE_Pos)
5626 #define SDIO_MINISTS_CMDDONE SDIO_MINISTS_CMDDONE_Msk
5627 #define SDIO_MINISTS_DTRANSFEROVER_Pos (3U)
5628 #define SDIO_MINISTS_DTRANSFEROVER_Msk (0x1U << SDIO_MINISTS_DTRANSFEROVER_Pos)
5629 #define SDIO_MINISTS_DTRANSFEROVER SDIO_MINISTS_DTRANSFEROVER_Msk
5630 #define SDIO_MINISTS_TXDATAREQ_Pos (4U)
5631 #define SDIO_MINISTS_TXDATAREQ_Msk (0x1U << SDIO_MINISTS_TXDATAREQ_Pos)
5632 #define SDIO_MINISTS_TXDATAREQ SDIO_MINISTS_TXDATAREQ_Msk
5633 #define SDIO_MINISTS_RXDATAREQ_Pos (5U)
5634 #define SDIO_MINISTS_RXDATAREQ_Msk (0x1U << SDIO_MINISTS_RXDATAREQ_Pos)
5635 #define SDIO_MINISTS_RXDATAREQ SDIO_MINISTS_RXDATAREQ_Msk
5636 #define SDIO_MINISTS_RESPCRCERR_Pos (6U)
5637 #define SDIO_MINISTS_RESPCRCERR_Msk (0x1U << SDIO_MINISTS_RESPCRCERR_Pos)
5638 #define SDIO_MINISTS_RESPCRCERR SDIO_MINISTS_RESPCRCERR_Msk
5639 #define SDIO_MINISTS_DATACRCERR_Pos (7U)
5640 #define SDIO_MINISTS_DATACRCERR_Msk (0x1U << SDIO_MINISTS_DATACRCERR_Pos)
5641 #define SDIO_MINISTS_DATACRCERR SDIO_MINISTS_DATACRCERR_Msk
5642 #define SDIO_MINISTS_RESPTIMEOUT_Pos (8U)
5643 #define SDIO_MINISTS_RESPTIMEOUT_Msk (0x1U << SDIO_MINISTS_RESPTIMEOUT_Pos)
5644 #define SDIO_MINISTS_RESPTIMEOUT SDIO_MINISTS_RESPTIMEOUT_Msk
5645 #define SDIO_MINISTS_DATATIMEOUT_Pos (9U)
5646 #define SDIO_MINISTS_DATATIMEOUT_Msk (0x1U << SDIO_MINISTS_DATATIMEOUT_Pos)
5647 #define SDIO_MINISTS_DATATIMEOUT SDIO_MINISTS_DATATIMEOUT_Msk
5648 #define SDIO_MINISTS_DATASTARV_Pos (10U)
5649 #define SDIO_MINISTS_DATASTARV_Msk (0x1U << SDIO_MINISTS_DATASTARV_Pos)
5650 #define SDIO_MINISTS_DATASTARV SDIO_MINISTS_DATASTARV_Msk
5651 #define SDIO_MINISTS_UNDER_OVER_RUN_Pos (11U)
5652 #define SDIO_MINISTS_UNDER_OVER_RUN_Msk (0x1U << SDIO_MINISTS_UNDER_OVER_RUN_Pos)
5653 #define SDIO_MINISTS_UNDER_OVER_RUN SDIO_MINISTS_UNDER_OVER_RUN_Msk
5654 #define SDIO_MINISTS_HLE_Pos (12U)
5655 #define SDIO_MINISTS_HLE_Msk (0x1U << SDIO_MINISTS_HLE_Pos)
5656 #define SDIO_MINISTS_HLE SDIO_MINISTS_HLE_Msk
5657 #define SDIO_MINISTS_STARTERROR_Pos (13U)
5658 #define SDIO_MINISTS_STARTERROR_Msk (0x1U << SDIO_MINISTS_STARTERROR_Pos)
5659 #define SDIO_MINISTS_STARTERROR SDIO_MINISTS_STARTERROR_Msk
5660 #define SDIO_MINISTS_BUSYCLEAR_Pos (13U)
5661 #define SDIO_MINISTS_BUSYCLEAR_Msk (0x1U << SDIO_MINISTS_BUSYCLEAR_Pos)
5662 #define SDIO_MINISTS_BUSYCLEAR SDIO_MINISTS_BUSYCLEAR_Msk
5663 #define SDIO_MINISTS_AUTOCMDDONE_Pos (14U)
5664 #define SDIO_MINISTS_AUTOCMDDONE_Msk (0x1U << SDIO_MINISTS_AUTOCMDDONE_Pos)
5665 #define SDIO_MINISTS_AUTOCMDDONE SDIO_MINISTS_AUTOCMDDONE_Msk
5666 #define SDIO_MINISTS_ENDERROR_Pos (15U)
5667 #define SDIO_MINISTS_ENDERROR_Msk (0x1U << SDIO_MINISTS_ENDERROR_Pos)
5668 #define SDIO_MINISTS_ENDERROR SDIO_MINISTS_ENDERROR_Msk
5669 #define SDIO_MINISTS_SDIOIT_Pos (16U)
5670 #define SDIO_MINISTS_SDIOIT_Msk (0xFFFFU << SDIO_MINISTS_SDIOIT_Pos)
5671 #define SDIO_MINISTS_SDIOIT SDIO_MINISTS_SDIOIT_Msk
5672 
5673 /****************** Bit definition for SDIO_RINTSTS register ********************/
5674 #define SDIO_RINTSTS_CARDDETECT_Pos (0U)
5675 #define SDIO_RINTSTS_CARDDETECT_Msk (0x1U << SDIO_RINTSTS_CARDDETECT_Pos)
5676 #define SDIO_RINTSTS_CARDDETECT SDIO_RINTSTS_CARDDETECT_Msk
5677 #define SDIO_RINTSTS_RESPERR_Pos (1U)
5678 #define SDIO_RINTSTS_RESPERR_Msk (0x1U << SDIO_RINTSTS_RESPERR_Pos)
5679 #define SDIO_RINTSTS_RESPERR SDIO_RINTSTS_RESPERR_Msk
5680 #define SDIO_RINTSTS_CMDDONE_Pos (2U)
5681 #define SDIO_RINTSTS_CMDDONE_Msk (0x1U << SDIO_RINTSTS_CMDDONE_Pos)
5682 #define SDIO_RINTSTS_CMDDONE SDIO_RINTSTS_CMDDONE_Msk
5683 #define SDIO_RINTSTS_DTRANSFEROVER_Pos (3U)
5684 #define SDIO_RINTSTS_DTRANSFEROVER_Msk (0x1U << SDIO_RINTSTS_DTRANSFEROVER_Pos)
5685 #define SDIO_RINTSTS_DTRANSFEROVER SDIO_RINTSTS_DTRANSFEROVER_Msk
5686 #define SDIO_RINTSTS_TXDATAREQ_Pos (4U)
5687 #define SDIO_RINTSTS_TXDATAREQ_Msk (0x1U << SDIO_RINTSTS_TXDATAREQ_Pos)
5688 #define SDIO_RINTSTS_TXDATAREQ SDIO_RINTSTS_TXDATAREQ_Msk
5689 #define SDIO_RINTSTS_RXDATAREQ_Pos (5U)
5690 #define SDIO_RINTSTS_RXDATAREQ_Msk (0x1U << SDIO_RINTSTS_RXDATAREQ_Pos)
5691 #define SDIO_RINTSTS_RXDATAREQ SDIO_RINTSTS_RXDATAREQ_Msk
5692 #define SDIO_RINTSTS_RESPCRCERR_Pos (6U)
5693 #define SDIO_RINTSTS_RESPCRCERR_Msk (0x1U << SDIO_RINTSTS_RESPCRCERR_Pos)
5694 #define SDIO_RINTSTS_RESPCRCERR SDIO_RINTSTS_RESPCRCERR_Msk
5695 #define SDIO_RINTSTS_DATACRCERR_Pos (7U)
5696 #define SDIO_RINTSTS_DATACRCERR_Msk (0x1U << SDIO_RINTSTS_DATACRCERR_Pos)
5697 #define SDIO_RINTSTS_DATACRCERR SDIO_RINTSTS_DATACRCERR_Msk
5698 #define SDIO_RINTSTS_RESPTIMEOUT_Pos (8U)
5699 #define SDIO_RINTSTS_RESPTIMEOUT_Msk (0x1U << SDIO_RINTSTS_RESPTIMEOUT_Pos)
5700 #define SDIO_RINTSTS_RESPTIMEOUT SDIO_RINTSTS_RESPTIMEOUT_Msk
5701 #define SDIO_RINTSTS_DATATIMEOUT_Pos (9U)
5702 #define SDIO_RINTSTS_DATATIMEOUT_Msk (0x1U << SDIO_RINTSTS_DATATIMEOUT_Pos)
5703 #define SDIO_RINTSTS_DATATIMEOUT SDIO_RINTSTS_DATATIMEOUT_Msk
5704 #define SDIO_RINTSTS_DATASTARV_Pos (10U)
5705 #define SDIO_RINTSTS_DATASTARV_Msk (0x1U << SDIO_RINTSTS_DATASTARV_Pos)
5706 #define SDIO_RINTSTS_DATASTARV SDIO_RINTSTS_DATASTARV_Msk
5707 #define SDIO_RINTSTS_UNDER_OVER_RUN_Pos (11U)
5708 #define SDIO_RINTSTS_UNDER_OVER_RUN_Msk (0x1U << SDIO_RINTSTS_UNDER_OVER_RUN_Pos)
5709 #define SDIO_RINTSTS_UNDER_OVER_RUN SDIO_RINTSTS_UNDER_OVER_RUN_Msk
5710 #define SDIO_RINTSTS_HLE_Pos (12U)
5711 #define SDIO_RINTSTS_HLE_Msk (0x1U << SDIO_RINTSTS_HLE_Pos)
5712 #define SDIO_RINTSTS_HLE SDIO_RINTSTS_HLE_Msk
5713 #define SDIO_RINTSTS_STARTERROR_Pos (13U)
5714 #define SDIO_RINTSTS_STARTERROR_Msk (0x1U << SDIO_RINTSTS_STARTERROR_Pos)
5715 #define SDIO_RINTSTS_STARTERROR SDIO_RINTSTS_STARTERROR_Msk
5716 #define SDIO_RINTSTS_BUSYCLEAR_Pos (13U)
5717 #define SDIO_RINTSTS_BUSYCLEAR_Msk (0x1U << SDIO_RINTSTS_BUSYCLEAR_Pos)
5718 #define SDIO_RINTSTS_BUSYCLEAR SDIO_RINTSTS_BUSYCLEAR_Msk
5719 #define SDIO_RINTSTS_AUTOCMDDONE_Pos (14U)
5720 #define SDIO_RINTSTS_AUTOCMDDONE_Msk (0x1U << SDIO_RINTSTS_AUTOCMDDONE_Pos)
5721 #define SDIO_RINTSTS_AUTOCMDDONE SDIO_RINTSTS_AUTOCMDDONE_Msk
5722 #define SDIO_RINTSTS_ENDERROR_Pos (15U)
5723 #define SDIO_RINTSTS_ENDERROR_Msk (0x1U << SDIO_RINTSTS_ENDERROR_Pos)
5724 #define SDIO_RINTSTS_ENDERROR SDIO_RINTSTS_ENDERROR_Msk
5725 #define SDIO_RINTSTS_SDIOIT_Pos (16U)
5726 #define SDIO_RINTSTS_SDIOIT_Msk (0xFFFFU << SDIO_RINTSTS_SDIOIT_Pos)
5727 #define SDIO_RINTSTS_SDIOIT SDIO_RINTSTS_SDIOIT_Msk
5728 
5729 /******************* Bit definition for SDIO_STATUS register *******************/
5730 #define SDIO_STATUS_RX_WMARK_Pos (0U)
5731 #define SDIO_STATUS_RX_WMARK_Msk (0x1U << SDIO_STATUS_RX_WMARK_Pos)
5732 #define SDIO_STATUS_RX_WMARK SDIO_STATUS_RX_WMARK_Msk
5733 #define SDIO_STATUS_TX_WMARK_Pos (1U)
5734 #define SDIO_STATUS_TX_WMARK_Msk (0x1U << SDIO_STATUS_TX_WMARK_Pos)
5735 #define SDIO_STATUS_TX_WMARK SDIO_STATUS_TX_WMARK_Msk
5736 #define SDIO_STATUS_FIFO_EMPTY_Pos (2U)
5737 #define SDIO_STATUS_FIFO_EMPTY_Msk (0x1U << SDIO_STATUS_FIFO_EMPTY_Pos)
5738 #define SDIO_STATUS_FIFO_EMPTY SDIO_STATUS_FIFO_EMPTY_Msk
5739 #define SDIO_STATUS_FIFO_FULL_Pos (3U)
5740 #define SDIO_STATUS_FIFO_FULL_Msk (0x1U << SDIO_STATUS_FIFO_FULL_Pos)
5741 #define SDIO_STATUS_FIFO_FULL SDIO_STATUS_FIFO_FULL_Msk
5742 #define SDIO_STATUS_FSM_STATE_Pos (4U)
5743 #define SDIO_STATUS_FSM_STATE_Msk (0xFU << SDIO_STATUS_FSM_STATE_Pos)
5744 #define SDIO_STATUS_FSM_STATE SDIO_STATUS_FSM_STATE_Msk
5745 #define SDIO_STATUS_DATA3_STATUS_Pos (8U)
5746 #define SDIO_STATUS_DATA3_STATUS_Msk (0x1U << SDIO_STATUS_DATA3_STATUS_Pos)
5747 #define SDIO_STATUS_DATA3_STATUS SDIO_STATUS_DATA3_STATUS_Msk
5748 #define SDIO_STATUS_CARD_BUSY_Pos (9U)
5749 #define SDIO_STATUS_CARD_BUSY_Msk (0x1U << SDIO_STATUS_CARD_BUSY_Pos)
5750 #define SDIO_STATUS_CARD_BUSY SDIO_STATUS_CARD_BUSY_Msk
5751 #define SDIO_STATUS_DATA_BUSY_Pos (10U)
5752 #define SDIO_STATUS_DATA_BUSY_Msk (0x1U << SDIO_STATUS_DATA_BUSY_Pos)
5753 #define SDIO_STATUS_DATA_BUSY SDIO_STATUS_DATA_BUSY_Msk
5754 #define SDIO_STATUS_RESPONSE_INDEX_Pos (11U)
5755 #define SDIO_STATUS_RESPONSE_INDEX_Msk (0x3FU << SDIO_STATUS_RESPONSE_INDEX_Pos)
5756 #define SDIO_STATUS_RESPONSE_INDEX SDIO_STATUS_RESPONSE_INDEX_Msk
5757 #define SDIO_STATUS_FIFO_COUNT_Pos (17U)
5758 #define SDIO_STATUS_FIFO_COUNT_Msk (0x1FFFU << SDIO_STATUS_FIFO_COUNT_Pos)
5759 #define SDIO_STATUS_FIFO_COUNT SDIO_STATUS_FIFO_COUNT_Msk
5760 #define SDIO_STATUS_DMA_ACK_Pos (30U)
5761 #define SDIO_STATUS_DMA_ACK_Msk (0x1U << SDIO_STATUS_DMA_ACK_Pos)
5762 #define SDIO_STATUS_DMA_ACK SDIO_STATUS_DMA_ACK_Msk
5763 #define SDIO_STATUS_DMA_REQ_Pos (31U)
5764 #define SDIO_STATUS_DMA_REQ_Msk (0x1U << SDIO_STATUS_DMA_REQ_Pos)
5765 #define SDIO_STATUS_DMA_REQ SDIO_STATUS_DMA_REQ_Msk
5766 
5767 
5768 /******************* Bit definition for SDIO_FIFOTH register *******************/
5769 #define SDIO_FIFOTH_TX_WMARK_Pos (0U)
5770 #define SDIO_FIFOTH_TX_WMARK_Msk (0xFFFU << SDIO_FIFOTH_TX_WMARK_Pos)
5771 #define SDIO_FIFOTH_TX_WMARK SDIO_FIFOTH_TX_WMARK_Msk
5772 #define SDIO_FIFOTH_RX_WMARK_Pos (16U)
5773 #define SDIO_FIFOTH_RX_WMARK_Msk (0xFFFU << SDIO_FIFOTH_RX_WMARK_Pos)
5774 #define SDIO_FIFOTH_RX_WMARK SDIO_FIFOTH_RX_WMARK_Msk
5775 #define SDIO_FIFOTH_MSIZE_Pos (28U)
5776 #define SDIO_FIFOTH_MSIZE_Msk (0x3U << SDIO_FIFOTH_MSIZE_Pos)
5777 #define SDIO_FIFOTH_MSIZE SDIO_FIFOTH_MSIZE_Msk
5778 
5779 /******************* Bit definition for SDIO_WRIPRT register *******************/
5780 #define SDIO_WRIPRT_WRITE_PROTECT_Pos (0U)
5781 #define SDIO_WRIPRT_WRITE_PROTECT_Msk (0x1U << SDIO_WRIPRT_WRITE_PROTECT_Pos)
5782 #define SDIO_WRIPRT_WRITE_PROTECT SDIO_WRIPRT_WRITE_PROTECT_Msk
5783 
5784 /******************* Bit definition for SDIO_TCBCNT register *******************/
5785 #define SDIO_TCBCNT_COUNT_Pos (0U)
5786 #define SDIO_TCBCNT_COUNT_Msk (0xFFFFFFFFU << SDIO_TCBCNT_COUNT_Pos)
5787 #define SDIO_TCBCNT_COUNT SDIO_TCBCNT_COUNT_Msk
5788 
5789 /******************* Bit definition for SDIO_TBBCNT register *******************/
5790 #define SDIO_TBBCNT_COUNT_Pos (0U)
5791 #define SDIO_TBBCNT_COUNT_Msk (0xFFFFFFFFU << SDIO_TBBCNT_COUNT_Pos)
5792 #define SDIO_TBBCNT_COUNT SDIO_TBBCNT_COUNT_Msk
5793 
5794 /******************* Bit definition for SDIO_BMOD register *******************/
5795 #define SDIO_BMOD_SWR_Pos (0U)
5796 #define SDIO_BMOD_SWR_Msk (0x1U << SDIO_BMOD_SWR_Pos)
5797 #define SDIO_BMOD_SWR SDIO_BMOD_SERE_Msk
5798 #define SDIO_BMOD_FB_Pos (1U)
5799 #define SDIO_BMOD_FB_Msk (0x1U << SDIO_BMOD_FB_Pos)
5800 #define SDIO_BMOD_FB SDIO_BMOD_FB_Msk
5801 #define SDIO_BMOD_DSL_Pos (2U)
5802 #define SDIO_BMOD_DSL_Msk (0x1FU << SDIO_BMOD_DSL_Pos)
5803 #define SDIO_BMOD_DSL SDIO_BMOD_DSL_Msk
5804 #define SDIO_BMOD_DE_Pos (7U)
5805 #define SDIO_BMOD_DE_Msk (0x1U << SDIO_BMOD_DE_Pos)
5806 #define SDIO_BMOD_DE SDIO_BMOD_DE_Msk
5807 #define SDIO_BMOD_PBL_Pos (8U)
5808 #define SDIO_BMOD_PBL_Msk (0x7U << SDIO_BMOD_PBL_Pos)
5809 #define SDIO_BMOD_PBL SDIO_BMOD_PBL_Msk
5810 
5811 /******************* Bit definition for SDIO_PLDMND register *******************/
5812 #define SDIO_PLDMND_PD_Pos (0U)
5813 #define SDIO_PLDMND_PD_Msk (0xFFFFFFFFU << SDIO_PLDMND_PD_Pos)
5814 #define SDIO_PLDMND_PD SDIO_PLDMND_PD_Msk
5815 
5816 /******************* Bit definition for SDIO_DBADDR register *******************/
5817 #define SDIO_DBADDR_SDL_Pos (0U)
5818 #define SDIO_DBADDR_SDL_Msk (0xFFFFFFFFU << SDIO_DBADDR_SDL_Pos)
5819 #define SDIO_DBADDR_SDL SDIO_DBADDR_SDL_Msk
5820 
5821 /******************* Bit definition for SDIO_IDSTS register *******************/
5822 #define SDIO_IDSTS_TI_Pos (0U)
5823 #define SDIO_IDSTS_TI_Msk (0x1U << SDIO_IDSTS_TI_Pos)
5824 #define SDIO_IDSTS_TI SDIO_IDSTS_TI_Msk
5825 #define SDIO_IDSTS_RI_Pos (1U)
5826 #define SDIO_IDSTS_RI_Msk (0x1U << SDIO_IDSTS_RI_Pos)
5827 #define SDIO_IDSTS_RI SDIO_IDSTS_RI_Msk
5828 #define SDIO_IDSTS_FBE_Pos (2U)
5829 #define SDIO_IDSTS_FBE_Msk (0x1U << SDIO_IDSTS_FBE_Pos)
5830 #define SDIO_IDSTS_FBE SDIO_IDSTS_FBE_Msk
5831 #define SDIO_IDSTS_DU_Pos (4U)
5832 #define SDIO_IDSTS_DU_Msk (0x1U << SDIO_IDSTS_DU_Pos)
5833 #define SDIO_IDSTS_DU SDIO_IDSTS_DU_Msk
5834 #define SDIO_IDSTS_CES_Pos (5U)
5835 #define SDIO_IDSTS_CES_Msk (0x1U << SDIO_IDSTS_CES_Pos)
5836 #define SDIO_IDSTS_CES SDIO_IDSTS_CES_Msk
5837 #define SDIO_IDSTS_NIS_Pos (8U)
5838 #define SDIO_IDSTS_NIS_Msk (0x1U << SDIO_IDSTS_NIS_Pos)
5839 #define SDIO_IDSTS_NIS SDIO_IDSTS_NIS_Msk
5840 #define SDIO_IDSTS_AIS_Pos (9U)
5841 #define SDIO_IDSTS_AIS_Msk (0x1U << SDIO_IDSTS_AIS_Pos)
5842 #define SDIO_IDSTS_AIS SDIO_IDSTS_AIS_Msk
5843 #define SDIO_IDSTS_FBE_CODE_Pos (10U)
5844 #define SDIO_IDSTS_FBE_CODE_Msk (0x7U << SDIO_IDSTS_FBE_CODE_Pos)
5845 #define SDIO_IDSTS_FBE_CODE SDIO_IDSTS_FBE_CODE_Msk
5846 #define SDIO_IDSTS_FSM_Pos (13U)
5847 #define SDIO_IDSTS_FSM_Msk (0xFU << SDIO_IDSTS_FSM_Pos)
5848 #define SDIO_IDSTS_FSM SDIO_IDSTS_FSM_Msk
5849 
5850 /******************* Bit definition for SDIO_IDINTEN register *******************/
5851 #define SDIO_IDINTEN_TI_Pos (0U)
5852 #define SDIO_IDINTEN_TI_Msk (0x1U << SDIO_DBADDR_SDL_Pos)
5853 #define SDIO_IDINTEN_TI SDIO_DBADDR_SDL_Msk
5854 #define SDIO_IDINTEN_RI_Pos (1U)
5855 #define SDIO_IDINTEN_RI_Msk (0x1U << SDIO_IDINTEN_RI_Pos)
5856 #define SDIO_IDINTEN_RI SDIO_IDINTEN_RI_Msk
5857 #define SDIO_IDINTEN_FBE_Pos (2U)
5858 #define SDIO_IDINTEN_FBE_Msk (0x1U << SDIO_IDINTEN_FBE_Pos)
5859 #define SDIO_IDINTEN_FBE SDIO_IDINTEN_FBE_Msk
5860 #define SDIO_IDINTEN_DU_Pos (4U)
5861 #define SDIO_IDINTEN_DU_Msk (0x1U << SDIO_IDINTEN_DU_Pos)
5862 #define SDIO_IDINTEN_DU SDIO_IDINTEN_DU_Msk
5863 #define SDIO_IDINTEN_CES_Pos (5U)
5864 #define SDIO_IDINTEN_CES_Msk (0x1U << SDIO_IDINTEN_CES_Pos)
5865 #define SDIO_IDINTEN_CES SDIO_IDINTEN_CES_Msk
5866 #define SDIO_IDINTEN_NI_Pos (8U)
5867 #define SDIO_IDINTEN_NI_Msk (0x1U << SDIO_IDINTEN_NI_Pos)
5868 #define SDIO_IDINTEN_NI SDIO_IDINTEN_NI_Msk
5869 #define SDIO_IDINTEN_AI_Pos (9U)
5870 #define SDIO_IDINTEN_AI_Msk (0x1U << SDIO_IDINTEN_AI_Pos)
5871 #define SDIO_IDINTEN_AI SDIO_IDINTEN_AI_Msk
5872 
5873 /******************* Bit definition for SDIO_DSCADDR register *******************/
5874 #define SDIO_DSCADDR_HDA_Pos (0U)
5875 #define SDIO_DSCADDR_HDA_Msk (0xFFFFFFFFU << SDIO_DSCADDR_HDA_Pos)
5876 #define SDIO_DSCADDR_HDA SDIO_DSCADDR_HDA_Msk
5877 
5878 /******************* Bit definition for SDIO_BUFADDR register *******************/
5879 #define SDIO_BUFADDR_HBA_Pos (0U)
5880 #define SDIO_BUFADDR_HBA_Msk (0xFFFFFFFFU << SDIO_BUFADDR_HBA_Pos)
5881 #define SDIO_BUFADDR_HBA SDIO_BUFADDR_HBA_Msk
5882 
5883 /******************* Bit definition for SDIO_CARDTHRCTL register *******************/
5884 #define SDIO_CARDTHRCTL_CARDRDTHREN_Pos (0U)
5885 #define SDIO_CARDTHRCTL_CARDRDTHREN_Msk (0x1 << SDIO_CARDTHRCTL_CARDRDTHREN_Pos)
5886 #define SDIO_CARDTHRCTL_CARDRDTHREN SDIO_CARDTHRCTL_CARDRDTHREN_Msk
5887 #define SDIO_CARDTHRCTL_BSYCLRINTEN_Pos (1U)
5888 #define SDIO_CARDTHRCTL_BSYCLRINTEN_Msk (0x1 << SDIO_CARDTHRCTL_BSYCLRINTEN_Pos)
5889 #define SDIO_CARDTHRCTL_BSYCLRINTEN SDIO_CARDTHRCTL_BSYCLRINTEN_Msk
5890 #define SDIO_CARDTHRCTL_CARDWRTHREN_Pos (2U)
5891 #define SDIO_CARDTHRCTL_CARDWRTHREN_Msk (0x1 << SDIO_CARDTHRCTL_CARDWRTHREN_Pos)
5892 #define SDIO_CARDTHRCTL_CARDWRTHREN SDIO_CARDTHRCTL_CARDWRTHREN_Msk
5893 #define SDIO_CARDTHRCTL_CARDTHRESHOLD_Pos (16U)
5894 #define SDIO_CARDTHRCTL_CARDTHRESHOLD_Msk (0x3FF << SDIO_CARDTHRCTL_CARDTHRESHOLD_Pos)
5895 #define SDIO_CARDTHRCTL_CARDTHRESHOLD SDIO_CARDTHRCTL_CARDTHRESHOLD_Msk
5896 
5897 /******************************************************************************/
5898 /* */
5899 /* Universal Serial Bus (USB) */
5900 /* */
5901 /******************************************************************************/
5902 
5903 /******************************** Bit definition for USB_FADDR register ********************************/
5904 #define USB_FADDR_FADDR_Msk (0x7FU)
5906 /******************************** Bit definition for USB_POWER register ********************************/
5907 #define USB_POWER_SUSEN (0x1U << 0)
5908 #define USB_POWER_SUSMD (0x1U << 1)
5909 #define USB_POWER_RESUME (0x1U << 2)
5910 #define USB_POWER_USBRST (0x1U << 3)
5911 #define USB_POWER_SOFTCONN (0x1U << 6)
5912 #define USB_POWER_ISOUD (0x1U << 7)
5914 /******************************** Bit definition for USB_INTRTX register ********************************/
5915 #define USB_INTRTX_EP0 (0x1U << 0)
5916 #define USB_INTRTX_EP1TX (0x1U << 1)
5917 #define USB_INTRTX_EP2TX (0x1U << 2)
5918 #define USB_INTRTX_EP3TX (0x1U << 3)
5919 #define USB_INTRTX_EP4TX (0x1U << 4)
5920 #define USB_INTRTX_EP5TX (0x1U << 5)
5922 /******************************** Bit definition for USB_INTRRX register ********************************/
5923 #define USB_INTRRX_EP1RX (0x1U << 1)
5924 #define USB_INTRRX_EP2RX (0x1U << 2)
5925 #define USB_INTRRX_EP3RX (0x1U << 3)
5926 #define USB_INTRRX_EP4RX (0x1U << 4)
5927 #define USB_INTRRX_EP5RX (0x1U << 5)
5929 /******************************** Bit definition for USB_INTRTXE register ********************************/
5930 #define USB_INTRTXE_EP0E (0x1U << 0)
5931 #define USB_INTRTXE_EP1TXE (0x1U << 1)
5932 #define USB_INTRTXE_EP2TXE (0x1U << 2)
5933 #define USB_INTRTXE_EP3TXE (0x1U << 3)
5934 #define USB_INTRTXE_EP4TXE (0x1U << 4)
5935 #define USB_INTRTXE_EP5TXE (0x1U << 5)
5937 /******************************** Bit definition for USB_INTRRXE register ********************************/
5938 #define USB_INTRRXE_EP1RXE (0x1U << 1)
5939 #define USB_INTRRXE_EP2RXE (0x1U << 2)
5940 #define USB_INTRRXE_EP3RXE (0x1U << 3)
5941 #define USB_INTRRXE_EP4RXE (0x1U << 4)
5942 #define USB_INTRRXE_EP5RXE (0x1U << 5)
5944 /******************************** Bit definition for USB_INTRUSB register ********************************/
5945 #define USB_INTRUSB_SUSIS (0x1U << 0)
5946 #define USB_INTRUSB_RSUIS (0x1U << 1)
5947 #define USB_INTRUSB_RSTIS (0x1U << 2)
5948 #define USB_INTRUSB_SOFIS (0x1U << 3)
5950 /******************************** Bit definition for USB_INTRUSBE register ********************************/
5951 #define USB_INTRUSBE_SUSIE (0x1U << 0)
5952 #define USB_INTRUSBE_RSUIE (0x1U << 1)
5953 #define USB_INTRUSBE_RSTIE (0x1U << 2)
5954 #define USB_INTRUSBE_SOFIE (0x1U << 3)
5956 /******************************** Bit definition for USB_CSR0L register ********************************/
5957 #define USB_CSR0L_RXPKTRDY (0x1U << 0)
5958 #define USB_CSR0L_TXPKTRDY (0x1U << 1)
5959 #define USB_CSR0L_SENTSTALL (0x1U << 2)
5960 #define USB_CSR0L_DATAEND (0x1U << 3)
5961 #define USB_CSR0L_SETUPEND (0x1U << 4)
5962 #define USB_CSR0L_SENDSTALL (0x1U << 5)
5963 #define USB_CSR0L_SVDRXPKTRDY (0x1U << 6)
5964 #define USB_CSR0L_SVDSETUPEND (0x1U << 7)
5966 /******************************** Bit definition for USB_CSR0H register ********************************/
5967 #define USB_CSR0H_FLUSHFIFO (0x1U << 0)
5969 /******************************** Bit definition for USB_TXCSRL register ********************************/
5970 #define USB_TXCSRL_TXPKTRDY (0x1U << 0)
5971 #define USB_TXCSRL_FIFONE (0x1U << 1)
5972 #define USB_TXCSRL_UNDERRUN (0x1U << 2)
5973 #define USB_TXCSRL_FLUSHFIFO (0x1U << 3)
5974 #define USB_TXCSRL_SENDSTALL (0x1U << 4)
5975 #define USB_TXCSRL_SENTSTALL (0x1U << 5)
5976 #define USB_TXCSRL_CLRDATATOG (0x1U << 6)
5978 /******************************** Bit definition for USB_TXCSRH register ********************************/
5979 #define USB_TXCSRH_FRCDATATOG (0x1U << 3)
5980 #define USB_TXCSRH_DMAEN (0x1U << 4)
5981 #define USB_TXCSRH_ISO (0x1U << 6)
5982 #define USB_TXCSRH_AUTOSET (0x1U << 7)
5984 /******************************** Bit definition for USB_RXCSRL register ********************************/
5985 #define USB_RXCSRL_RXPKTRDY (0x1U << 0)
5986 #define USB_RXCSRL_FIFOFULL (0x1U << 1)
5987 #define USB_RXCSRL_OVERRUN (0x1U << 2)
5988 #define USB_RXCSRL_DATAERROR (0x1U << 3)
5989 #define USB_RXCSRL_FLUSHFIFO (0x1U << 4)
5990 #define USB_RXCSRL_SENDSTALL (0x1U << 5)
5991 #define USB_RXCSRL_SENTSTALL (0x1U << 6)
5992 #define USB_RXCSRL_CLRDATATOG (0x1U << 7)
5994 /******************************** Bit definition for USB_OUTCSR2 register ********************************/
5995 #define USB_RXCSRH_DMAEN (0x1U << 5)
5996 #define USB_RXCSRH_ISO (0x1U << 6)
5997 #define USB_RXCSRH_AUTOCLR (0x1U << 7)
5999 /******************************************************************************/
6000 /* */
6001 /* Serial Peripheral Interface (SPI) */
6002 /* */
6003 /******************************************************************************/
6004 
6005 /*
6006  * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
6007  */
6008 #define SPI_I2S_SUPPORT
6009 #define SPI_CRC_ERROR_WORKAROUND_FEATURE
6010 
6011 /******************* Bit definition for SPI_CR1 register ********************/
6012 #define SPI_CR1_CPHA_Pos (0U)
6013 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
6014 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
6015 #define SPI_CR1_CPOL_Pos (1U)
6016 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
6017 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
6018 #define SPI_CR1_MSTR_Pos (2U)
6019 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
6020 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
6022 #define SPI_CR1_BR_Pos (3U)
6023 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
6024 #define SPI_CR1_BR SPI_CR1_BR_Msk
6025 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
6026 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
6027 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
6029 #define SPI_CR1_SPE_Pos (6U)
6030 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
6031 #define SPI_CR1_SPE SPI_CR1_SPE_Msk
6032 #define SPI_CR1_LSBFIRST_Pos (7U)
6033 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
6034 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
6035 #define SPI_CR1_SSI_Pos (8U)
6036 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
6037 #define SPI_CR1_SSI SPI_CR1_SSI_Msk
6038 #define SPI_CR1_SSM_Pos (9U)
6039 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
6040 #define SPI_CR1_SSM SPI_CR1_SSM_Msk
6041 #define SPI_CR1_RXONLY_Pos (10U)
6042 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
6043 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
6044 #define SPI_CR1_DFF_Pos (11U)
6045 #define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos)
6046 #define SPI_CR1_DFF SPI_CR1_DFF_Msk
6047 #define SPI_CR1_CRCNEXT_Pos (12U)
6048 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
6049 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
6050 #define SPI_CR1_CRCEN_Pos (13U)
6051 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
6052 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
6053 #define SPI_CR1_BIDIOE_Pos (14U)
6054 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
6055 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
6056 #define SPI_CR1_BIDIMODE_Pos (15U)
6057 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
6058 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
6060 /******************* Bit definition for SPI_CR2 register ********************/
6061 #define SPI_CR2_RXDMAEN_Pos (0U)
6062 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
6063 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
6064 #define SPI_CR2_TXDMAEN_Pos (1U)
6065 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
6066 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
6067 #define SPI_CR2_SSOE_Pos (2U)
6068 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
6069 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
6070 #define SPI_CR2_ERRIE_Pos (5U)
6071 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
6072 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
6073 #define SPI_CR2_RXNEIE_Pos (6U)
6074 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
6075 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
6076 #define SPI_CR2_TXEIE_Pos (7U)
6077 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
6078 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
6080 /******************** Bit definition for SPI_SR register ********************/
6081 #define SPI_SR_RXNE_Pos (0U)
6082 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
6083 #define SPI_SR_RXNE SPI_SR_RXNE_Msk
6084 #define SPI_SR_TXE_Pos (1U)
6085 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
6086 #define SPI_SR_TXE SPI_SR_TXE_Msk
6087 #define SPI_SR_CHSIDE_Pos (2U)
6088 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
6089 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
6090 #define SPI_SR_UDR_Pos (3U)
6091 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
6092 #define SPI_SR_UDR SPI_SR_UDR_Msk
6093 #define SPI_SR_CRCERR_Pos (4U)
6094 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
6095 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
6096 #define SPI_SR_MODF_Pos (5U)
6097 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
6098 #define SPI_SR_MODF SPI_SR_MODF_Msk
6099 #define SPI_SR_OVR_Pos (6U)
6100 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
6101 #define SPI_SR_OVR SPI_SR_OVR_Msk
6102 #define SPI_SR_BSY_Pos (7U)
6103 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
6104 #define SPI_SR_BSY SPI_SR_BSY_Msk
6106 /******************** Bit definition for SPI_DR register ********************/
6107 #define SPI_DR_DR_Pos (0U)
6108 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
6109 #define SPI_DR_DR SPI_DR_DR_Msk
6111 /******************* Bit definition for SPI_CRCPR register ******************/
6112 #define SPI_CRCPR_CRCPOLY_Pos (0U)
6113 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
6114 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
6116 /****************** Bit definition for SPI_RXCRCR register ******************/
6117 #define SPI_RXCRCR_RXCRC_Pos (0U)
6118 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
6119 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
6121 /****************** Bit definition for SPI_TXCRCR register ******************/
6122 #define SPI_TXCRCR_TXCRC_Pos (0U)
6123 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
6124 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
6126 /****************** Bit definition for SPI_I2SCFGR register *****************/
6127 #define SPI_I2SCFGR_CHLEN_Pos (0U)
6128 #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
6129 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
6131 #define SPI_I2SCFGR_DATLEN_Pos (1U)
6132 #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
6133 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
6134 #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
6135 #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
6137 #define SPI_I2SCFGR_CKPOL_Pos (3U)
6138 #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
6139 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
6141 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
6142 #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
6143 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
6144 #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
6145 #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
6147 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
6148 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
6149 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
6151 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
6152 #define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)
6153 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
6154 #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
6155 #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
6157 #define SPI_I2SCFGR_I2SE_Pos (10U)
6158 #define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)
6159 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk
6160 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
6161 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
6162 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
6163 /****************** Bit definition for SPI_I2SPR register *******************/
6164 #define SPI_I2SPR_I2SDIV_Pos (0U)
6165 #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)
6166 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk
6167 #define SPI_I2SPR_ODD_Pos (8U)
6168 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)
6169 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk
6170 #define SPI_I2SPR_MCKOE_Pos (9U)
6171 #define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)
6172 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk
6174 /******************************************************************************/
6175 /* */
6176 /* Inter-integrated Circuit Interface (I2C) */
6177 /* */
6178 /******************************************************************************/
6179 
6180 /****************************** Bit definition for I2C_CON register *******************************/
6181 #define I2C_CON_MASTER_MODE (0x1UL << 0)
6183 #define I2C_CON_SPEED_Msk (0x3UL << 1)
6184 #define I2C_CON_SPEED_STANDARD (0x1UL << 1)
6185 #define I2C_CON_SPEED_FAST (0x2UL << 1)
6187 #define I2C_CON_10BITADDR_SLAVE (0x1UL << 3)
6188 #define I2C_CON_10BITADDR_MASTER (0x1UL << 4)
6189 #define I2C_CON_RESTART_EN (0x1UL << 5)
6190 #define I2C_CON_SLAVE_DISABLE (0x1UL << 6)
6191 #define I2C_CON_STOP_DET_IFADDRESSED (0x1UL << 7)
6192 #define I2C_CON_TX_EMPTY_CTRL (0x1UL << 8)
6193 #define I2C_CON_RX_FIFO_FULL_HLD_CTRL (0x1UL << 9)
6194 #define I2C_CON_STOP_DET_IF_MASTER_ACTIVE (0x1UL << 10)
6195 #define I2C_CON_BUS_CLEAR_FEATURE_CTRL (0x1UL << 11)
6196 #define I2C_CON_OPTIONAL_SAR_CTRL (0x1UL << 16)
6197 #define I2C_CON_SMBUS_SLAVE_QUICK_EN (0x1UL << 17)
6198 #define I2C_CON_SMBUS_ARP_EN (0x1UL << 18)
6199 #define I2C_CON_SMBUS_PERSISTANT_SLV_ADDR_EN (0x1UL << 19)
6201 /****************************** Bit definition for I2C_TAR register *******************************/
6202 #define I2C_TAR_TAR_Msk (0x3FFUL)
6203 #define I2C_TAR_GC_OR_START (0x1UL << 10)
6204 #define I2C_TAR_SPECIAL (0x1UL << 11)
6205 #define I2C_TAR_10BITADDR_MASTER (0x1UL << 12)
6206 #define I2C_TAR_DEVICE_ID (0x1UL << 13)
6207 #define I2C_TAR_SMBUS_QUICK_CMD (0x1UL << 16)
6209 /****************************** Bit definition for I2C_SAR register *******************************/
6210 /****************************** Bit definition for I2C_HS_MADDR register *******************************/
6211 
6212 /****************************** Bit definition for I2C_DATA_CMD register *******************************/
6213 #define I2C_DATA_CMD_DAT_Msk (0xFFUL)
6215 #define I2C_DATA_CMD_READ (0x1UL << 8)
6216 #define I2C_DATA_CMD_STOP (0x1UL << 9)
6217 #define I2C_DATA_CMD_RESTART (0x1UL << 10)
6218 #define I2C_DATA_CMD_FIRST_DATA_BYTE (0x1UL << 11)
6220 /****************************** Bit definition for I2C_SS_SCL_HCNT register *******************************/
6221 /****************************** Bit definition for I2C_SS_SCL_LCNT register *******************************/
6222 /****************************** Bit definition for I2C_FS_SCL_HCNT register *******************************/
6223 /****************************** Bit definition for I2C_FS_SCL_LCNT register *******************************/
6224 /****************************** Bit definition for I2C_HS_SCL_HCNT register *******************************/
6225 /****************************** Bit definition for I2C_HS_SCL_LCNT register *******************************/
6226 
6227 /****************************** Bit definition for I2C_INTR_STAT register *******************************/
6228 /****************************** Bit definition for I2C_INTR_MASK register *******************************/
6229 /****************************** Bit definition for I2C_RAW_INTR_STAT register *******************************/
6230 #define I2C_INTR_RX_UNDER (0x1UL << 0)
6231 #define I2C_INTR_RX_OVER (0x1UL << 1)
6232 #define I2C_INTR_RX_FULL (0x1UL << 2)
6233 #define I2C_INTR_TX_OVER (0x1UL << 3)
6234 #define I2C_INTR_TX_EMPTY (0x1UL << 4)
6235 #define I2C_INTR_RD_REQ (0x1UL << 5)
6236 #define I2C_INTR_TX_ABRT (0x1UL << 6)
6237 #define I2C_INTR_RX_DONE (0x1UL << 7)
6238 #define I2C_INTR_ACTIVITY (0x1UL << 8)
6239 #define I2C_INTR_STOP_DET (0x1UL << 9)
6240 #define I2C_INTR_START_DET (0x1UL << 10)
6241 #define I2C_INTR_GEN_CALL (0x1UL << 11)
6242 #define I2C_INTR_SCL_STUCK_AT_LOW (0x1UL << 14)
6245 /****************************** Bit definition for I2C_RX_TL register *******************************/
6246 /****************************** Bit definition for I2C_TX_TL register *******************************/
6247 /****************************** Bit definition for I2C_CLR_INTR register *******************************/
6248 /****************************** Bit definition for I2C_CLR_RX_UNDERT register *******************************/
6249 /****************************** Bit definition for I2C_CLR_RX_OVER register *******************************/
6250 /****************************** Bit definition for I2C_CLR_TX_OVER register *******************************/
6251 /****************************** Bit definition for I2C_CLR_RD_REQ register *******************************/
6252 /****************************** Bit definition for I2C_CLR_TX_ABRT register *******************************/
6253 /****************************** Bit definition for I2C_CLR_RX_DONE register *******************************/
6254 /****************************** Bit definition for I2C_CLR_ACTIVITY register *******************************/
6255 /****************************** Bit definition for I2C_CLR_STOP_DET register *******************************/
6256 /****************************** Bit definition for I2C_CLR_START_DET register *******************************/
6257 /****************************** Bit definition for I2C_CLR_GEN_CALL register *******************************/
6258 
6259 /****************************** Bit definition for I2C_ENABLE register *******************************/
6260 #define I2C_ENABLE_ENABLE (0x1UL << 0)
6261 #define I2C_ENABLE_ABORT (0x1UL << 1)
6262 #define I2C_ENABLE_TX_CMD_BLOCK (0x1UL << 2)
6263 #define I2C_ENABLE_SDA_STUCK_RECOVERY_ENA (0x1UL << 3)
6264 #define I2C_ENABLE_SMBUS_CLK_RESET (0x1UL << 16)
6265 #define I2C_ENABLE_SMBUS_SUSPEND_EN (0x1UL << 17)
6266 #define I2C_ENABLE_SMBUS_ALERT_EN (0x1UL << 18)
6268 /****************************** Bit definition for I2C_STATUS register *******************************/
6269 #define I2C_STATUS_ACTIVITY (0x1UL << 0)
6270 #define I2C_STATUS_TFNF (0x1UL << 1)
6271 #define I2C_STATUS_TFE (0x1UL << 2)
6272 #define I2C_STATUS_RFNE (0x1UL << 3)
6273 #define I2C_STATUS_RFF (0x1UL << 4)
6274 #define I2C_STATUS_MST_ACTIVITY (0x1UL << 5)
6275 #define I2C_STATUS_SLV_ACTIVITY (0x1UL << 6)
6276 #define I2C_STATUS_MST_HOLD_TX_FIFO_EMPTY (0x1UL << 7)
6277 #define I2C_STATUS_MST_HOLD_RX_FIFO_FULL (0x1UL << 8)
6278 #define I2C_STATUS_SLV_HOLD_TX_FIFO_EMPTY (0x1UL << 9)
6279 #define I2C_STATUS_SLV_HOLD_RX_FIFO_FULL (0x1UL << 10)
6280 #define I2C_STATUS_SDA_STUCK_NOT_RECOVERED (0x1UL << 11)
6281 #define I2C_STATUS_SMBUS_QUICK_CMD_BIT (0x1UL << 16)
6282 #define I2C_STATUS_SMBUS_SLAVE_ADDR_VALID (0x1UL << 17)
6283 #define I2C_STATUS_SMBUS_SLAVE_ADDR_RESOLVED (0x1UL << 18)
6284 #define I2C_STATUS_SMBUS_SUSPEND_STATUS (0x1UL << 19)
6285 #define I2C_STATUS_SMBUS_ALERT_STATUS (0x1UL << 20)
6287 /****************************** Bit definition for I2C_TXFLR register *******************************/
6288 /****************************** Bit definition for I2C_RXFLR register *******************************/
6289 /****************************** Bit definition for I2C_SDA_HOLD register *******************************/
6290 
6291 /****************************** Bit definition for I2C_TX_ABRT_SOURCE *******************************/
6292 #define I2C_TX_ABRT_SOURCE_7B_ADDR_NOACK (0x1UL << 0)
6293 #define I2C_TX_ABRT_SOURCE_10ADDR1_NOACK (0x1UL << 1)
6294 #define I2C_TX_ABRT_SOURCE_10ADDR2_NOACK (0x1UL << 2)
6295 #define I2C_TX_ABRT_SOURCE_TXDATA_NOACK (0x1UL << 3)
6296 #define I2C_TX_ABRT_SOURCE_GCALL_NOACK (0x1UL << 4)
6297 #define I2C_TX_ABRT_SOURCE_GCALL_READ (0x1UL << 5)
6298 #define I2C_TX_ABRT_SOURCE_HS_ACKDET (0x1UL << 6)
6299 #define I2C_TX_ABRT_SOURCE_SBYTE_ACKDET (0x1UL << 7)
6300 #define I2C_TX_ABRT_SOURCE_HS_NORSTRT (0x1UL << 8)
6301 #define I2C_TX_ABRT_SOURCE_SBYTE_NORSTRT (0x1UL << 9)
6302 #define I2C_TX_ABRT_SOURCE_10B_RD_NORSTRT (0x1UL << 10)
6303 #define I2C_TX_ABRT_SOURCE_MASTER_DIS (0x1UL << 11)
6304 #define I2C_TX_ABRT_SOURCE_LOST (0x1UL << 12)
6305 #define I2C_TX_ABRT_SOURCE_SLVFLUSH_TXFIFO (0x1UL << 13)
6306 #define I2C_TX_ABRT_SOURCE_SLV_ARBLOST (0x1UL << 14)
6307 #define I2C_TX_ABRT_SOURCE_SLVRD_INTX (0x1UL << 15)
6308 #define I2C_TX_ABRT_SOURCE_USER_ABRT (0x1UL << 16)
6309 #define I2C_TX_ABRT_SOURCE_SDA_STUCK_AT_LOW (0x1UL << 17)
6310 #define I2C_TX_ABRT_SOURCE_DEVICE_NOACK (0x1UL << 18)
6311 #define I2C_TX_ABRT_SOURCE_DEVICE_SLVADDR_NOACK (0x1UL << 19)
6312 #define I2C_TX_ABRT_SOURCE_DEVICE_WRITE (0x1UL << 20)
6314 #define I2C_TX_ABRT_SOURCE_TX_FLUSH_CNT_Msk (0xFF800000UL)
6316 /****************************** Bit definition for I2C_SLV_DATA_NACK_ONLY register *******************************/
6317 #define I2C_SLV_DATA_NACK_ONLY_NACK (0x1UL << 0)
6319 /****************************** Bit definition for I2C_DMA_CR register *******************************/
6320 #define I2C_DMA_CR_RDMAE (0x1UL << 0)
6321 #define I2C_DMA_CR_TDMAE (0x1UL << 1)
6323 /****************************** Bit definition for I2C_DMA_TDLR register *******************************/
6324 /****************************** Bit definition for I2C_DMA_RDLR register *******************************/
6325 /****************************** Bit definition for I2C_SDA_SETUP register *******************************/
6326 /****************************** Bit definition for I2C_ACK_GENERAL_CALL register *******************************/
6327 
6328 /****************************** Bit definition for I2C_ENABLE_STATUS register *******************************/
6329 #define I2C_ENABLE_STATUS_IC_EN (0x1UL << 0)
6330 #define I2C_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY (0x1UL << 1)
6331 #define I2C_ENABLE_STATUS_SLV_RX_DATA_LOST (0x1UL << 2)
6333 /****************************** Bit definition for FS_SPKLEN register *******************************/
6334 /****************************** Bit definition for HS_SPKLEN register *******************************/
6335 /****************************** Bit definition for CLR_RESTART_DET register *******************************/
6336 /****************************** Bit definition for SCL_STUCK_AT_LOW_TIMEOUT register *******************************/
6337 /****************************** Bit definition for SDA_STUCK_AT_LOW_TIMEOUT register *******************************/
6338 /****************************** Bit definition for CLR_SCL_STUCK_DET register *******************************/
6339 /****************************** Bit definition for SMBUS_CLK_LOW_SEXT register *******************************/
6340 /****************************** Bit definition for SMBUS_CLK_LOW_MEXT register *******************************/
6341 /****************************** Bit definition for SMBUS_THIGH_MAX_IDLE_COUNT register *******************************/
6342 /****************************** Bit definition for SMBUS_INTR_STAT register *******************************/
6343 /****************************** Bit definition for SMBUS_INTR_MASK register *******************************/
6344 /****************************** Bit definition for SMBUS_RAW_INTR_STAT register *******************************/
6345 #define I2C_SMBUS_INTR_SLV_CLOCK_EXTND_TIMEOUT (0x1UL << 0)
6346 #define I2C_SMBUS_INTR_MST_CLOCK_EXTND_TIMEOUT (0x1UL << 1)
6347 #define I2C_SMBUS_INTR_QUICK_CMD_DET (0x1UL << 2)
6348 #define I2C_SMBUS_INTR_HOST_NTFY_MST_DET (0x1UL << 3)
6349 #define I2C_SMBUS_INTR_ARP_PREPARE_CMD_DET (0x1UL << 4)
6350 #define I2C_SMBUS_INTR_ARP_RST_CMD_DET (0x1UL << 5)
6351 #define I2C_SMBUS_INTR_ARP_GET_UDID_CMD_DET (0x1UL << 6)
6352 #define I2C_SMBUS_INTR_ARP_ASSGN_ADDR_CMD_DET (0x1UL << 7)
6353 #define I2C_SMBUS_INTR_SLV_RX_PEC_NACK (0x1UL << 8)
6354 #define I2C_SMBUS_INTR_SMBUS_SUSPEND_DET (0x1UL << 9)
6355 #define I2C_SMBUS_INTR_SMBUS_ALERT_DET (0x1UL << 10)
6357 /****************************** Bit definition for CLR_SMBUS_INTR register *******************************/
6358 /****************************** Bit definition for OPTIONAL_SAR register *******************************/
6359 /****************************** Bit definition for SMBUS_UDID_LSB register *******************************/
6360 
6361 /******************************************************************************/
6362 /* */
6363 /* Universal Synchronous Asynchronous Receiver Transmitter */
6364 /* */
6365 /******************************************************************************/
6366 
6367 /******************* Bit definition for USART_SR register *******************/
6368 #define USART_SR_PE_Pos (0U)
6369 #define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos)
6370 #define USART_SR_PE USART_SR_PE_Msk
6371 #define USART_SR_FE_Pos (1U)
6372 #define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos)
6373 #define USART_SR_FE USART_SR_FE_Msk
6374 #define USART_SR_NE_Pos (2U)
6375 #define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos)
6376 #define USART_SR_NE USART_SR_NE_Msk
6377 #define USART_SR_ORE_Pos (3U)
6378 #define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos)
6379 #define USART_SR_ORE USART_SR_ORE_Msk
6380 #define USART_SR_IDLE_Pos (4U)
6381 #define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos)
6382 #define USART_SR_IDLE USART_SR_IDLE_Msk
6383 #define USART_SR_RXNE_Pos (5U)
6384 #define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos)
6385 #define USART_SR_RXNE USART_SR_RXNE_Msk
6386 #define USART_SR_TC_Pos (6U)
6387 #define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos)
6388 #define USART_SR_TC USART_SR_TC_Msk
6389 #define USART_SR_TXE_Pos (7U)
6390 #define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos)
6391 #define USART_SR_TXE USART_SR_TXE_Msk
6392 #define USART_SR_LBD_Pos (8U)
6393 #define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos)
6394 #define USART_SR_LBD USART_SR_LBD_Msk
6395 #define USART_SR_CTS_Pos (9U)
6396 #define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos)
6397 #define USART_SR_CTS USART_SR_CTS_Msk
6399 /******************* Bit definition for USART_DR register *******************/
6400 #define USART_DR_DR_Pos (0U)
6401 #define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos)
6402 #define USART_DR_DR USART_DR_DR_Msk
6404 /****************** Bit definition for USART_BRR register *******************/
6405 #define USART_BRR_DIV_Fraction_Pos (0U)
6406 #define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos)
6407 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk
6408 #define USART_BRR_DIV_Mantissa_Pos (4U)
6409 #define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)
6410 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk
6412 /****************** Bit definition for USART_CR1 register *******************/
6413 #define USART_CR1_SBK_Pos (0U)
6414 #define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos)
6415 #define USART_CR1_SBK USART_CR1_SBK_Msk
6416 #define USART_CR1_RWU_Pos (1U)
6417 #define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos)
6418 #define USART_CR1_RWU USART_CR1_RWU_Msk
6419 #define USART_CR1_RE_Pos (2U)
6420 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
6421 #define USART_CR1_RE USART_CR1_RE_Msk
6422 #define USART_CR1_TE_Pos (3U)
6423 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
6424 #define USART_CR1_TE USART_CR1_TE_Msk
6425 #define USART_CR1_IDLEIE_Pos (4U)
6426 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
6427 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
6428 #define USART_CR1_RXNEIE_Pos (5U)
6429 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
6430 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
6431 #define USART_CR1_TCIE_Pos (6U)
6432 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
6433 #define USART_CR1_TCIE USART_CR1_TCIE_Msk
6434 #define USART_CR1_TXEIE_Pos (7U)
6435 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
6436 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
6437 #define USART_CR1_PEIE_Pos (8U)
6438 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
6439 #define USART_CR1_PEIE USART_CR1_PEIE_Msk
6440 #define USART_CR1_PS_Pos (9U)
6441 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
6442 #define USART_CR1_PS USART_CR1_PS_Msk
6443 #define USART_CR1_PCE_Pos (10U)
6444 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
6445 #define USART_CR1_PCE USART_CR1_PCE_Msk
6446 #define USART_CR1_WAKE_Pos (11U)
6447 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
6448 #define USART_CR1_WAKE USART_CR1_WAKE_Msk
6449 #define USART_CR1_M_Pos (12U)
6450 #define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos)
6451 #define USART_CR1_M USART_CR1_M_Msk
6452 #define USART_CR1_UE_Pos (13U)
6453 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
6454 #define USART_CR1_UE USART_CR1_UE_Msk
6456 /****************** Bit definition for USART_CR2 register *******************/
6457 #define USART_CR2_ADD_Pos (0U)
6458 #define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos)
6459 #define USART_CR2_ADD USART_CR2_ADD_Msk
6460 #define USART_CR2_LBDL_Pos (5U)
6461 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
6462 #define USART_CR2_LBDL USART_CR2_LBDL_Msk
6463 #define USART_CR2_LBDIE_Pos (6U)
6464 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
6465 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
6466 #define USART_CR2_LBCL_Pos (8U)
6467 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
6468 #define USART_CR2_LBCL USART_CR2_LBCL_Msk
6469 #define USART_CR2_CPHA_Pos (9U)
6470 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
6471 #define USART_CR2_CPHA USART_CR2_CPHA_Msk
6472 #define USART_CR2_CPOL_Pos (10U)
6473 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
6474 #define USART_CR2_CPOL USART_CR2_CPOL_Msk
6475 #define USART_CR2_CLKEN_Pos (11U)
6476 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
6477 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
6479 #define USART_CR2_STOP_Pos (12U)
6480 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
6481 #define USART_CR2_STOP USART_CR2_STOP_Msk
6482 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
6483 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
6485 #define USART_CR2_LINEN_Pos (14U)
6486 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
6487 #define USART_CR2_LINEN USART_CR2_LINEN_Msk
6489 /****************** Bit definition for USART_CR3 register *******************/
6490 #define USART_CR3_EIE_Pos (0U)
6491 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
6492 #define USART_CR3_EIE USART_CR3_EIE_Msk
6493 #define USART_CR3_IREN_Pos (1U)
6494 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
6495 #define USART_CR3_IREN USART_CR3_IREN_Msk
6496 #define USART_CR3_IRLP_Pos (2U)
6497 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
6498 #define USART_CR3_IRLP USART_CR3_IRLP_Msk
6499 #define USART_CR3_HDSEL_Pos (3U)
6500 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
6501 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
6502 #define USART_CR3_NACK_Pos (4U)
6503 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
6504 #define USART_CR3_NACK USART_CR3_NACK_Msk
6505 #define USART_CR3_SCEN_Pos (5U)
6506 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
6507 #define USART_CR3_SCEN USART_CR3_SCEN_Msk
6508 #define USART_CR3_DMAR_Pos (6U)
6509 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
6510 #define USART_CR3_DMAR USART_CR3_DMAR_Msk
6511 #define USART_CR3_DMAT_Pos (7U)
6512 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
6513 #define USART_CR3_DMAT USART_CR3_DMAT_Msk
6514 #define USART_CR3_RTSE_Pos (8U)
6515 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
6516 #define USART_CR3_RTSE USART_CR3_RTSE_Msk
6517 #define USART_CR3_CTSE_Pos (9U)
6518 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
6519 #define USART_CR3_CTSE USART_CR3_CTSE_Msk
6520 #define USART_CR3_CTSIE_Pos (10U)
6521 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
6522 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
6524 /****************** Bit definition for USART_GTPR register ******************/
6525 #define USART_GTPR_PSC_Pos (0U)
6526 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
6527 #define USART_GTPR_PSC USART_GTPR_PSC_Msk
6528 #define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos)
6529 #define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos)
6530 #define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos)
6531 #define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos)
6532 #define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos)
6533 #define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos)
6534 #define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos)
6535 #define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos)
6537 #define USART_GTPR_GT_Pos (8U)
6538 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
6539 #define USART_GTPR_GT USART_GTPR_GT_Msk
6541 /******************************************************************************/
6542 /* */
6543 /* Debug MCU (DBGMCU) */
6544 /* */
6545 /******************************************************************************/
6546 
6547 /**************** Bit definition for DBGMCU_IDCODE register *****************/
6548 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
6549 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
6550 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
6552 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
6553 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
6554 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
6555 #define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos)
6556 #define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos)
6557 #define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos)
6558 #define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos)
6559 #define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos)
6560 #define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos)
6561 #define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos)
6562 #define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos)
6563 #define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos)
6564 #define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos)
6565 #define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos)
6566 #define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos)
6567 #define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos)
6568 #define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos)
6569 #define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos)
6570 #define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos)
6572 /****************** Bit definition for DBGMCU_CR register *******************/
6573 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
6574 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
6575 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
6576 #define DBGMCU_CR_DBG_STOP_Pos (1U)
6577 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
6578 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
6579 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
6580 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
6581 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
6582 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
6583 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
6584 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
6586 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
6587 #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
6588 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
6589 #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
6590 #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
6592 #define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
6593 #define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_IWDG_STOP_Pos)
6594 #define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk
6595 #define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
6596 #define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_WWDG_STOP_Pos)
6597 #define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk
6598 #define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U)
6599 #define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM1_STOP_Pos)
6600 #define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk
6601 #define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
6602 #define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM2_STOP_Pos)
6603 #define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk
6604 #define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
6605 #define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM3_STOP_Pos)
6606 #define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk
6607 #define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)
6608 #define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM4_STOP_Pos)
6609 #define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk
6610 #define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U)
6611 #define DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_CR_DBG_CAN1_STOP_Pos)
6612 #define DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk
6613 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
6614 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos)
6615 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk
6616 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
6617 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos)
6618 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk
6619 #define DBGMCU_CR_DBG_TIM8_STOP_Pos (17U)
6620 #define DBGMCU_CR_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM8_STOP_Pos)
6621 #define DBGMCU_CR_DBG_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP_Msk
6622 #define DBGMCU_CR_DBG_TIM5_STOP_Pos (18U)
6623 #define DBGMCU_CR_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM5_STOP_Pos)
6624 #define DBGMCU_CR_DBG_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP_Msk
6625 #define DBGMCU_CR_DBG_TIM6_STOP_Pos (19U)
6626 #define DBGMCU_CR_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM6_STOP_Pos)
6627 #define DBGMCU_CR_DBG_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP_Msk
6628 #define DBGMCU_CR_DBG_TIM7_STOP_Pos (20U)
6629 #define DBGMCU_CR_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM7_STOP_Pos)
6630 #define DBGMCU_CR_DBG_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP_Msk
6632 /******************************************************************************/
6633 /* */
6634 /* FLASH and Option Bytes Registers (FLASH) */
6635 /* */
6636 /******************************************************************************/
6637 
6638 /******************* Bit definition for FLASH_ACR register ******************/
6639 #define FLASH_ACR_LATENCY_Pos (0U)
6640 #define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos)
6641 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
6642 #define FLASH_ACR_LATENCY_0 (0x0UL << FLASH_ACR_LATENCY_Pos)
6643 #define FLASH_ACR_LATENCY_1 (0x1UL << FLASH_ACR_LATENCY_Pos)
6645 #define FLASH_ACR_HLFCYA_Pos (3U)
6646 #define FLASH_ACR_HLFCYA_Msk (0x1UL << FLASH_ACR_HLFCYA_Pos)
6647 #define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk
6648 #define FLASH_ACR_PRFTBE_Pos (4U)
6649 #define FLASH_ACR_PRFTBE_Msk (0x1UL << FLASH_ACR_PRFTBE_Pos)
6650 #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk
6651 #define FLASH_ACR_PRFTBS_Pos (5U)
6652 #define FLASH_ACR_PRFTBS_Msk (0x1UL << FLASH_ACR_PRFTBS_Pos)
6653 #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk
6655 /****************** Bit definition for FLASH_KEYR register ******************/
6656 #define FLASH_KEYR_FKEYR_Pos (0U)
6657 #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos)
6658 #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk
6660 #define RDP_KEY_Pos (0U)
6661 #define RDP_KEY_Msk (0xA5UL << RDP_KEY_Pos)
6662 #define RDP_KEY RDP_KEY_Msk
6663 #define FLASH_KEY1_Pos (0U)
6664 #define FLASH_KEY1_Msk (0x45670123UL << FLASH_KEY1_Pos)
6665 #define FLASH_KEY1 FLASH_KEY1_Msk
6666 #define FLASH_KEY2_Pos (0U)
6667 #define FLASH_KEY2_Msk (0xCDEF89ABUL << FLASH_KEY2_Pos)
6668 #define FLASH_KEY2 FLASH_KEY2_Msk
6670 /***************** Bit definition for FLASH_OPTKEYR register ****************/
6671 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
6672 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos)
6673 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk
6675 #define FLASH_OPTKEY1 FLASH_KEY1
6676 #define FLASH_OPTKEY2 FLASH_KEY2
6678 /****************** Bit definition for FLASH_SR register ********************/
6679 #define FLASH_SR_BSY_Pos (0U)
6680 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
6681 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
6682 #define FLASH_SR_PGERR_Pos (2U)
6683 #define FLASH_SR_PGERR_Msk (0x1UL << FLASH_SR_PGERR_Pos)
6684 #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk
6685 #define FLASH_SR_WRPRTERR_Pos (4U)
6686 #define FLASH_SR_WRPRTERR_Msk (0x1UL << FLASH_SR_WRPRTERR_Pos)
6687 #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk
6688 #define FLASH_SR_EOP_Pos (5U)
6689 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
6690 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
6692 /******************* Bit definition for FLASH_CR register *******************/
6693 #define FLASH_CR_PG_Pos (0U)
6694 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
6695 #define FLASH_CR_PG FLASH_CR_PG_Msk
6696 #define FLASH_CR_PER_Pos (1U)
6697 #define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos)
6698 #define FLASH_CR_PER FLASH_CR_PER_Msk
6699 #define FLASH_CR_MER_Pos (2U)
6700 #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)
6701 #define FLASH_CR_MER FLASH_CR_MER_Msk
6702 #define FLASH_CR_OPTPG_Pos (4U)
6703 #define FLASH_CR_OPTPG_Msk (0x1UL << FLASH_CR_OPTPG_Pos)
6704 #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk
6705 #define FLASH_CR_OPTER_Pos (5U)
6706 #define FLASH_CR_OPTER_Msk (0x1UL << FLASH_CR_OPTER_Pos)
6707 #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk
6708 #define FLASH_CR_STRT_Pos (6U)
6709 #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
6710 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
6711 #define FLASH_CR_LOCK_Pos (7U)
6712 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
6713 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
6714 #define FLASH_CR_OPTWRE_Pos (9U)
6715 #define FLASH_CR_OPTWRE_Msk (0x1UL << FLASH_CR_OPTWRE_Pos)
6716 #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk
6717 #define FLASH_CR_ERRIE_Pos (10U)
6718 #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)
6719 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
6720 #define FLASH_CR_EOPIE_Pos (12U)
6721 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
6722 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
6724 /******************* Bit definition for FLASH_AR register *******************/
6725 #define FLASH_AR_FAR_Pos (0U)
6726 #define FLASH_AR_FAR_Msk (0xFFFFFFFFUL << FLASH_AR_FAR_Pos)
6727 #define FLASH_AR_FAR FLASH_AR_FAR_Msk
6729 /****************** Bit definition for FLASH_OBR register *******************/
6730 #define FLASH_OBR_OPTERR_Pos (0U)
6731 #define FLASH_OBR_OPTERR_Msk (0x1UL << FLASH_OBR_OPTERR_Pos)
6732 #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk
6733 #define FLASH_OBR_RDPRT_Pos (1U)
6734 #define FLASH_OBR_RDPRT_Msk (0x1UL << FLASH_OBR_RDPRT_Pos)
6735 #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk
6737 #define FLASH_OBR_IWDG_SW_Pos (2U)
6738 #define FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos)
6739 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk
6740 #define FLASH_OBR_nRST_STOP_Pos (3U)
6741 #define FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos)
6742 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk
6743 #define FLASH_OBR_nRST_STDBY_Pos (4U)
6744 #define FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos)
6745 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk
6746 #define FLASH_OBR_USER_Pos (2U)
6747 #define FLASH_OBR_USER_Msk (0x7UL << FLASH_OBR_USER_Pos)
6748 #define FLASH_OBR_USER FLASH_OBR_USER_Msk
6749 #define FLASH_OBR_DATA0_Pos (10U)
6750 #define FLASH_OBR_DATA0_Msk (0xFFUL << FLASH_OBR_DATA0_Pos)
6751 #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk
6752 #define FLASH_OBR_DATA1_Pos (18U)
6753 #define FLASH_OBR_DATA1_Msk (0xFFUL << FLASH_OBR_DATA1_Pos)
6754 #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk
6756 /****************** Bit definition for FLASH_WRPR register ******************/
6757 #define FLASH_WRPR_WRP_Pos (0U)
6758 #define FLASH_WRPR_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR_WRP_Pos)
6759 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk
6761 /*----------------------------------------------------------------------------*/
6762 
6763 /****************** Bit definition for FLASH_RDP register *******************/
6764 #define FLASH_RDP_RDP_Pos (0U)
6765 #define FLASH_RDP_RDP_Msk (0xFFUL << FLASH_RDP_RDP_Pos)
6766 #define FLASH_RDP_RDP FLASH_RDP_RDP_Msk
6767 #define FLASH_RDP_nRDP_Pos (8U)
6768 #define FLASH_RDP_nRDP_Msk (0xFFUL << FLASH_RDP_nRDP_Pos)
6769 #define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk
6771 /****************** Bit definition for FLASH_USER register ******************/
6772 #define FLASH_USER_USER_Pos (16U)
6773 #define FLASH_USER_USER_Msk (0xFFUL << FLASH_USER_USER_Pos)
6774 #define FLASH_USER_USER FLASH_USER_USER_Msk
6775 #define FLASH_USER_nUSER_Pos (24U)
6776 #define FLASH_USER_nUSER_Msk (0xFFUL << FLASH_USER_nUSER_Pos)
6777 #define FLASH_USER_nUSER FLASH_USER_nUSER_Msk
6779 /****************** Bit definition for FLASH_Data0 register *****************/
6780 #define FLASH_DATA0_DATA0_Pos (0U)
6781 #define FLASH_DATA0_DATA0_Msk (0xFFUL << FLASH_DATA0_DATA0_Pos)
6782 #define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk
6783 #define FLASH_DATA0_nDATA0_Pos (8U)
6784 #define FLASH_DATA0_nDATA0_Msk (0xFFUL << FLASH_DATA0_nDATA0_Pos)
6785 #define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk
6787 /****************** Bit definition for FLASH_Data1 register *****************/
6788 #define FLASH_DATA1_DATA1_Pos (16U)
6789 #define FLASH_DATA1_DATA1_Msk (0xFFUL << FLASH_DATA1_DATA1_Pos)
6790 #define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk
6791 #define FLASH_DATA1_nDATA1_Pos (24U)
6792 #define FLASH_DATA1_nDATA1_Msk (0xFFUL << FLASH_DATA1_nDATA1_Pos)
6793 #define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk
6795 /****************** Bit definition for FLASH_WRP0 register ******************/
6796 #define FLASH_WRP0_WRP0_Pos (0U)
6797 #define FLASH_WRP0_WRP0_Msk (0xFFUL << FLASH_WRP0_WRP0_Pos)
6798 #define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk
6799 #define FLASH_WRP0_nWRP0_Pos (8U)
6800 #define FLASH_WRP0_nWRP0_Msk (0xFFUL << FLASH_WRP0_nWRP0_Pos)
6801 #define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk
6803 /****************** Bit definition for FLASH_WRP1 register ******************/
6804 #define FLASH_WRP1_WRP1_Pos (16U)
6805 #define FLASH_WRP1_WRP1_Msk (0xFFUL << FLASH_WRP1_WRP1_Pos)
6806 #define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk
6807 #define FLASH_WRP1_nWRP1_Pos (24U)
6808 #define FLASH_WRP1_nWRP1_Msk (0xFFUL << FLASH_WRP1_nWRP1_Pos)
6809 #define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk
6811 /****************** Bit definition for FLASH_WRP2 register ******************/
6812 #define FLASH_WRP2_WRP2_Pos (0U)
6813 #define FLASH_WRP2_WRP2_Msk (0xFFUL << FLASH_WRP2_WRP2_Pos)
6814 #define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk
6815 #define FLASH_WRP2_nWRP2_Pos (8U)
6816 #define FLASH_WRP2_nWRP2_Msk (0xFFUL << FLASH_WRP2_nWRP2_Pos)
6817 #define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk
6819 /****************** Bit definition for FLASH_WRP3 register ******************/
6820 #define FLASH_WRP3_WRP3_Pos (16U)
6821 #define FLASH_WRP3_WRP3_Msk (0xFFUL << FLASH_WRP3_WRP3_Pos)
6822 #define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk
6823 #define FLASH_WRP3_nWRP3_Pos (24U)
6824 #define FLASH_WRP3_nWRP3_Msk (0xFFUL << FLASH_WRP3_nWRP3_Pos)
6825 #define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk
6836 #define M8(adr) (*((volatile uint8_t *) (adr)))
6837 #define M16(adr) (*((volatile uint16_t *) (adr)))
6838 #define M32(adr) (*((volatile uint32_t *) (adr)))
6839 
6840 
6841 #define BIT_BAND_ADDR(addr, bitnum) ((((uint32_t)(addr)) & 0xF0000000) + 0x2000000 + ((((uint32_t)(addr)) & 0xFFFFF) << 5) + ((bitnum) << 2))
6842 
6843 
6844 #ifdef USE_STDPERIPH_DRIVER
6845  #include "mg32f157_conf.h"
6846 #endif
6847 
6848 
6853 #define SET_BIT(REG, BIT) ((REG) |= (BIT))
6854 
6855 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
6856 
6857 #define READ_BIT(REG, BIT) ((REG) & (BIT))
6858 
6859 #define CLEAR_REG(REG) ((REG) = (0x0))
6860 
6861 #define WRITE_REG(REG, VAL) ((REG) = (VAL))
6862 
6863 #define READ_REG(REG) ((REG))
6864 
6865 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
6866 
6867 #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
6868 
6873 #ifdef __cplusplus
6874 }
6875 #endif
6876 
6877 #endif /* __MG32F157_H__ */
6878 
__IO uint16_t DR42
Definition: mg32f157.h:347
__IO uint32_t KEYR1
Definition: mg32f157.h:447
__IO uint16_t DR15
Definition: mg32f157.h:293
uint16_t RESERVED4
Definition: mg32f157.h:776
__IO uint32_t CCR
Definition: mg32f157.h:875
Definition: mg32f157.h:115
__IO uint32_t ENABLE_SHIFT
Definition: mg32f157.h:833
__IO uint16_t DR3
Definition: mg32f157.h:263
__IO uint32_t IDR
Definition: mg32f157.h:638
__IO uint32_t JOFR3
Definition: mg32f157.h:237
Definition: mg32f157.h:842
__IO uint32_t DHR8R2
Definition: mg32f157.h:418
__IO uint16_t CNTL
Definition: mg32f157.h:781
__IO uint16_t DR1
Definition: mg32f157.h:259
__IO uint32_t CTYPE
Definition: mg32f157.h:801
__IO uint16_t DR22
Definition: mg32f157.h:307
__IO uint32_t CSR
Definition: mg32f157.h:758
__IO uint16_t DR16
Definition: mg32f157.h:295
__IO uint16_t DR20
Definition: mg32f157.h:303
__IO uint16_t DR6
Definition: mg32f157.h:269
__IO uint32_t DLR
Definition: mg32f157.h:874
__IO uint32_t JSQR
Definition: mg32f157.h:244
__IO uint32_t DHR12LD
Definition: mg32f157.h:420
__IO uint32_t DHR12L2
Definition: mg32f157.h:417
__IO uint32_t MAPR2
Definition: mg32f157.h:655
__IO uint32_t SR
Definition: mg32f157.h:390
__IO uint16_t DR
Definition: mg32f157.h:850
uint16_t RESERVED29
Definition: mg32f157.h:316
__IO uint32_t SQR2
Definition: mg32f157.h:242
__IO uint16_t DR9
Definition: mg32f157.h:275
__IO uint16_t DR14
Definition: mg32f157.h:291
Definition: mg32f157.h:141
uint16_t RESERVED1
Definition: mg32f157.h:260
uint16_t RESERVED17
Definition: mg32f157.h:292
__IO uint32_t RLR
Definition: mg32f157.h:729
__IO uint16_t I2SPR
Definition: mg32f157.h:860
__IO uint32_t JOFR4
Definition: mg32f157.h:238
__IO uint16_t DIVL
Definition: mg32f157.h:777
__IO uint32_t DHR12RD
Definition: mg32f157.h:419
__IO uint32_t PSMKR
Definition: mg32f157.h:879
__IO uint16_t WRP2
Definition: mg32f157.h:626
__IO uint16_t DR37
Definition: mg32f157.h:337
__IO uint32_t WRPR
Definition: mg32f157.h:610
uint16_t RESERVED42
Definition: mg32f157.h:342
Definition: mg32f157.h:138
uint16_t RESERVED27
Definition: mg32f157.h:312
__IO uint32_t OTR
Definition: mg32f157.h:401
Definition: mg32f157.h:160
__IO uint32_t CSR
Definition: mg32f157.h:400
__IO uint16_t DR41
Definition: mg32f157.h:345
uint16_t RESERVED6
Definition: mg32f157.h:932
__IO uint32_t SR
Definition: mg32f157.h:943
__IO uint16_t DR40
Definition: mg32f157.h:343
__IO uint32_t IDSTS
Definition: mg32f157.h:824
uint16_t RESERVED34
Definition: mg32f157.h:326
__IO uint32_t BYTCNT
Definition: mg32f157.h:803
Definition: mg32f157.h:586
uint16_t RESERVED7
Definition: mg32f157.h:859
uint16_t RESERVED5
Definition: mg32f157.h:268
__IO uint32_t LPOTR
Definition: mg32f157.h:402
uint16_t RESERVED1
Definition: mg32f157.h:379
Definition: mg32f157.h:161
uint16_t RESERVED4
Definition: mg32f157.h:853
Definition: mg32f157.h:118
uint16_t RESERVED5
Definition: mg32f157.h:930
__IO uint32_t ABR
Definition: mg32f157.h:877
__IO uint16_t DR31
Definition: mg32f157.h:325
Definition: mg32f157.h:512
uint16_t RESERVED35
Definition: mg32f157.h:328
__IO uint32_t AR
Definition: mg32f157.h:876
uint16_t RESERVED23
Definition: mg32f157.h:304
Definition: mg32f157.h:618
__IO uint32_t CR
Definition: mg32f157.h:411
Definition: mg32f157.h:163
Definition: mg32f157.h:109
Definition: mg32f157.h:374
__IO uint32_t DR
Definition: mg32f157.h:878
uint16_t RESERVED32
Definition: mg32f157.h:322
__IO uint32_t TXBUF
Definition: mg32f157.h:359
Definition: mg32f157.h:122
__IO uint32_t DOUTR
Definition: mg32f157.h:445
Definition: mg32f157.h:387
uint16_t RESERVED21
Definition: mg32f157.h:300
__IO uint16_t DR2
Definition: mg32f157.h:261
__IO uint16_t DR21
Definition: mg32f157.h:305
__IO uint32_t CLKENA
Definition: mg32f157.h:799
__IO uint32_t FTSR
Definition: mg32f157.h:591
__IO uint32_t KEYR
Definition: mg32f157.h:603
uint16_t RESERVED5
Definition: mg32f157.h:855
uint16_t RESERVED8
Definition: mg32f157.h:784
__IO uint16_t CRL
Definition: mg32f157.h:769
__IO uint32_t BDCR
Definition: mg32f157.h:757
__IO uint16_t RTCCR
Definition: mg32f157.h:279
__IO uint16_t DR33
Definition: mg32f157.h:329
__IO uint32_t IMR
Definition: mg32f157.h:588
Definition: mg32f157.h:107
__IO uint32_t RESERVED0
Definition: mg32f157.h:798
__IO uint16_t DR18
Definition: mg32f157.h:299
uint16_t RESERVED0
Definition: mg32f157.h:768
Definition: mg32f157.h:154
__IO uint32_t CR
Definition: mg32f157.h:749
__IO uint32_t APB1ENR
Definition: mg32f157.h:756
__IO uint16_t DR27
Definition: mg32f157.h:317
__IO uint16_t DR4
Definition: mg32f157.h:265
Definition: mg32f157.h:440
uint16_t RESERVED6
Definition: mg32f157.h:780
uint16_t RESERVED12
Definition: mg32f157.h:282
__IO uint32_t JDR2
Definition: mg32f157.h:246
__IO uint32_t CLKDIV
Definition: mg32f157.h:797
__IO uint16_t DR38
Definition: mg32f157.h:339
__IO uint32_t AHBENR
Definition: mg32f157.h:754
Definition: mg32f157.h:939
__IO uint32_t PSMAR
Definition: mg32f157.h:880
__IO uint32_t CR
Definition: mg32f157.h:433
uint16_t RESERVED18
Definition: mg32f157.h:294
__IO uint16_t DR7
Definition: mg32f157.h:271
Definition: mg32f157.h:114
Definition: mg32f157.h:106
__IO uint32_t DINR
Definition: mg32f157.h:444
__IO uint32_t RESP2
Definition: mg32f157.h:809
__IO uint32_t JDR1
Definition: mg32f157.h:245
__IO uint32_t DHR12R2
Definition: mg32f157.h:416
__IO uint32_t DR
Definition: mg32f157.h:376
Definition: mg32f157.h:120
__IO uint32_t PR
Definition: mg32f157.h:593
uint16_t RESERVED9
Definition: mg32f157.h:786
uint16_t RESERVED0
Definition: mg32f157.h:845
uint16_t RESERVED22
Definition: mg32f157.h:302
__IO uint32_t FIFO
Definition: mg32f157.h:835
__IO uint32_t DHR12R1
Definition: mg32f157.h:413
uint16_t RESERVED9
Definition: mg32f157.h:276
__IO uint32_t PWREN
Definition: mg32f157.h:796
__IO uint32_t KEYR2
Definition: mg32f157.h:448
__IO uint16_t CRCPR
Definition: mg32f157.h:852
__IO uint32_t DR
Definition: mg32f157.h:391
__IO uint32_t OBR
Definition: mg32f157.h:609
Definition: mg32f157.h:134
Definition: mg32f157.h:147
uint8_t RESERVED0
Definition: mg32f157.h:378
Definition: mg32f157.h:132
__IO uint32_t RESERVED1
Definition: mg32f157.h:817
__IO uint32_t WRTPRT
Definition: mg32f157.h:816
CMSIS Cortex-M3 Core Peripheral Access Layer Header File.
uint16_t RESERVED3
Definition: mg32f157.h:264
__IO uint16_t Data0
Definition: mg32f157.h:622
__IO uint32_t SSPP_TDCR_DBT
Definition: mg32f157.h:365
uint16_t RESERVED39
Definition: mg32f157.h:336
__IO uint32_t LCKR
Definition: mg32f157.h:642
uint16_t RESERVED19
Definition: mg32f157.h:296
__IO uint32_t CFGR
Definition: mg32f157.h:750
uint16_t RESERVED7
Definition: mg32f157.h:272
__IO uint32_t APB2RSTR
Definition: mg32f157.h:752
uint16_t RESERVED1
Definition: mg32f157.h:770
uint16_t RESERVED41
Definition: mg32f157.h:340
__IO uint16_t CR3
Definition: mg32f157.h:929
__IO uint32_t BLKSIZ
Definition: mg32f157.h:802
__IO uint16_t CR2
Definition: mg32f157.h:846
Definition: mg32f157.h:117
__IO uint32_t CR
Definition: mg32f157.h:941
Definition: mg32f157.h:113
__IO uint32_t TCBCNT
Definition: mg32f157.h:818
uint16_t RESERVED16
Definition: mg32f157.h:290
Definition: mg32f157.h:150
uint16_t RESERVED26
Definition: mg32f157.h:310
Definition: mg32f157.h:634
__IO uint32_t CMD
Definition: mg32f157.h:806
Definition: mg32f157.h:111
__IO uint32_t CR2
Definition: mg32f157.h:232
Definition: mg32f157.h:119
Definition: mg32f157.h:151
__IO uint16_t DR5
Definition: mg32f157.h:267
uint16_t RESERVED0
Definition: mg32f157.h:920
Definition: mg32f157.h:128
Definition: mg32f157.h:868
__IO uint16_t WRP1
Definition: mg32f157.h:625
Definition: mg32f157.h:110
__IO uint32_t TEST
Definition: mg32f157.h:367
__IO uint32_t FCR
Definition: mg32f157.h:873
__IO uint32_t IDCODE
Definition: mg32f157.h:432
uint32_t RESERVED3
Definition: mg32f157.h:697
uint32_t RESERVED0
Definition: mg32f157.h:258
Definition: mg32f157.h:355
uint16_t RESERVED4
Definition: mg32f157.h:928
__IO uint16_t DR10
Definition: mg32f157.h:277
__IO uint16_t SR
Definition: mg32f157.h:919
__IO uint16_t RDP
Definition: mg32f157.h:620
uint16_t RESERVED5
Definition: mg32f157.h:778
Definition: mg32f157.h:148
uint16_t RESERVED3
Definition: mg32f157.h:774
Definition: mg32f157.h:228
uint16_t RESERVED43
Definition: mg32f157.h:344
__IO uint32_t SR
Definition: mg32f157.h:605
uint16_t RESERVED2
Definition: mg32f157.h:849
__IO uint16_t Data1
Definition: mg32f157.h:623
__IO uint32_t DOR2
Definition: mg32f157.h:423
uint16_t RESERVED2
Definition: mg32f157.h:772
Definition: mg32f157.h:153
uint16_t RESERVED2
Definition: mg32f157.h:262
__IO uint32_t CTRL
Definition: mg32f157.h:795
Definition: mg32f157.h:649
Definition: mg32f157.h:126
uint16_t RESERVED11
Definition: mg32f157.h:280
__IO uint32_t INTMASK
Definition: mg32f157.h:804
__IO uint32_t CDETECT
Definition: mg32f157.h:815
__IO uint32_t RXBUF
Definition: mg32f157.h:360
Definition: mg32f157.h:125
Definition: mg32f157.h:460
__IO uint32_t CRH
Definition: mg32f157.h:637
uint16_t RESERVED3
Definition: mg32f157.h:851
uint8_t RESERVED1
Definition: mg32f157.h:552
__IO uint32_t CR
Definition: mg32f157.h:606
uint16_t RESERVED44
Definition: mg32f157.h:346
__IO uint32_t MAPR
Definition: mg32f157.h:652
Definition: mg32f157.h:116
uint16_t RESERVED8
Definition: mg32f157.h:274
__IO uint32_t JDR4
Definition: mg32f157.h:248
Definition: mg32f157.h:146
__IO uint32_t APB2ENR
Definition: mg32f157.h:755
Definition: mg32f157.h:137
__IO uint16_t DR12
Definition: mg32f157.h:287
__IO uint32_t SR
Definition: mg32f157.h:872
__IO uint32_t DHR8R1
Definition: mg32f157.h:415
Definition: mg32f157.h:917
__IO uint16_t WRP0
Definition: mg32f157.h:624
Definition: mg32f157.h:889
__IO uint16_t DR24
Definition: mg32f157.h:311
__IO uint16_t DR28
Definition: mg32f157.h:319
__IO uint16_t TXCRCR
Definition: mg32f157.h:856
__IO uint32_t UHS_REG_EXT
Definition: mg32f157.h:831
__IO uint16_t CR2
Definition: mg32f157.h:927
__IO uint16_t I2SCFGR
Definition: mg32f157.h:858
__IO uint16_t DR35
Definition: mg32f157.h:333
__IO uint32_t BSRR
Definition: mg32f157.h:640
uint16_t RESERVED31
Definition: mg32f157.h:320
Definition: mg32f157.h:124
__IO uint16_t BRR
Definition: mg32f157.h:923
Definition: mg32f157.h:409
uint16_t RESERVED8
Definition: mg32f157.h:861
uint16_t RESERVED28
Definition: mg32f157.h:314
Definition: mg32f157.h:158
Definition: mg32f157.h:600
__IO uint32_t KEYR3
Definition: mg32f157.h:449
__IO uint32_t IVR2
Definition: mg32f157.h:452
Definition: mg32f157.h:737
__IO uint32_t RESERVED
Definition: mg32f157.h:608
__IO uint32_t ALC_TXERR_RXERR_ECC
Definition: mg32f157.h:363
Definition: mg32f157.h:725
__IO uint32_t APB1RSTR
Definition: mg32f157.h:753
__IO uint32_t CFR
Definition: mg32f157.h:942
__IO uint32_t JOFR1
Definition: mg32f157.h:235
IRQn
Definition: mg32f157.h:90
__IO uint32_t RESP3
Definition: mg32f157.h:810
#define __IO
Definition: core_cm3.h:170
__IO uint32_t CR
Definition: mg32f157.h:389
uint16_t RESERVED1
Definition: mg32f157.h:922
Definition: mg32f157.h:140
__IO uint32_t CARDTHRCTL
Definition: mg32f157.h:829
__IO uint32_t CR
Definition: mg32f157.h:739
__IO uint16_t PRLH
Definition: mg32f157.h:771
uint16_t RESERVED24
Definition: mg32f157.h:306
__IO uint32_t CR
Definition: mg32f157.h:380
Definition: mg32f157.h:747
__IO uint32_t LTR
Definition: mg32f157.h:240
Definition: mg32f157.h:105
Definition: mg32f157.h:139
__IO uint32_t DCR
Definition: mg32f157.h:871
Definition: mg32f157.h:130
__IO uint32_t SR
Definition: mg32f157.h:730
__IO uint32_t AMR
Definition: mg32f157.h:362
__IO uint32_t STATUS
Definition: mg32f157.h:813
__IO uint32_t BT1_BT0_RMC_IMR
Definition: mg32f157.h:358
__IO uint32_t TMOUT
Definition: mg32f157.h:800
__IO uint32_t JOFR2
Definition: mg32f157.h:236
__IO uint32_t CSR
Definition: mg32f157.h:740
__IO uint32_t HTR
Definition: mg32f157.h:239
Definition: mg32f157.h:104
__IO uint32_t ISR_SR_CMR_MR
Definition: mg32f157.h:357
Definition: mg32f157.h:398
Definition: mg32f157.h:144
uint16_t RESERVED10
Definition: mg32f157.h:278
__IO uint32_t AR
Definition: mg32f157.h:607
__IO uint32_t BACK_END_POWER
Definition: mg32f157.h:830
__IO uint16_t ALRL
Definition: mg32f157.h:785
Definition: mg32f157.h:135
Definition: mg32f157.h:136
__IO uint16_t DR23
Definition: mg32f157.h:309
__IO uint16_t CSR
Definition: mg32f157.h:283
Definition: mg32f157.h:765
Definition: mg32f157.h:127
Definition: mg32f157.h:108
__IO uint32_t EVCR
Definition: mg32f157.h:651
__IO uint16_t USER
Definition: mg32f157.h:621
__IO uint32_t DSCADDR
Definition: mg32f157.h:826
Definition: mg32f157.h:121
__IO uint32_t DHR12L1
Definition: mg32f157.h:414
uint16_t RESERVED37
Definition: mg32f157.h:332
uint16_t RESERVED25
Definition: mg32f157.h:308
__IO uint32_t RESP1
Definition: mg32f157.h:808
Definition: mg32f157.h:145
__IO uint32_t CIR
Definition: mg32f157.h:751
__IO uint32_t KEYR0
Definition: mg32f157.h:446
Definition: mg32f157.h:256
__IO uint32_t RTSR
Definition: mg32f157.h:590
__IO uint16_t WRP3
Definition: mg32f157.h:627
uint16_t RESERVED40
Definition: mg32f157.h:338
__IO uint32_t CR
Definition: mg32f157.h:870
uint32_t RESERVED1
Definition: mg32f157.h:673
__IO uint16_t CRH
Definition: mg32f157.h:767
uint16_t RESERVED4
Definition: mg32f157.h:266
__IO uint32_t NBT
Definition: mg32f157.h:364
__IO uint16_t DR29
Definition: mg32f157.h:321
Definition: mg32f157.h:662
__IO uint16_t CR1
Definition: mg32f157.h:844
uint16_t RESERVED6
Definition: mg32f157.h:857
__IO uint32_t SR
Definition: mg32f157.h:443
__IO uint16_t PRLL
Definition: mg32f157.h:773
__IO uint32_t CR1
Definition: mg32f157.h:231
__IO uint16_t DR39
Definition: mg32f157.h:341
__IO uint32_t SMPR1
Definition: mg32f157.h:233
__IO uint16_t DR19
Definition: mg32f157.h:301
__IO uint16_t DR30
Definition: mg32f157.h:323
__IO uint32_t SQR3
Definition: mg32f157.h:243
__IO uint32_t DBADDR
Definition: mg32f157.h:823
__IO uint16_t DR32
Definition: mg32f157.h:327
Definition: mg32f157.h:123
Definition: mg32f157.h:143
__IO uint32_t MINTSTS
Definition: mg32f157.h:811
__IO uint32_t IVR3
Definition: mg32f157.h:453
__IO uint32_t BUFADDR
Definition: mg32f157.h:827
__IO uint16_t DR
Definition: mg32f157.h:921
__IO uint32_t CR
Definition: mg32f157.h:442
__IO uint16_t DR26
Definition: mg32f157.h:315
__IO uint32_t BRR
Definition: mg32f157.h:641
__IO uint32_t PIR
Definition: mg32f157.h:881
__IO uint32_t ODR
Definition: mg32f157.h:639
__IO uint32_t OP_MODE
Definition: mg32f157.h:611
uint16_t RESERVED7
Definition: mg32f157.h:782
__IO uint16_t CR1
Definition: mg32f157.h:925
__IO uint32_t ACR
Definition: mg32f157.h:602
Definition: mg32f157.h:152
__IO uint32_t PLDMND
Definition: mg32f157.h:822
__IO uint32_t SMPR2
Definition: mg32f157.h:234
Definition: mg32f157.h:112
__IO uint32_t CMDARG
Definition: mg32f157.h:805
__IO uint16_t CNTH
Definition: mg32f157.h:779
__IO uint32_t SWIER
Definition: mg32f157.h:592
Definition: mg32f157.h:430
uint16_t RESERVED1
Definition: mg32f157.h:847
Definition: mg32f157.h:157
__IO uint16_t DR25
Definition: mg32f157.h:313
uint16_t RESERVED20
Definition: mg32f157.h:298
uint32_t RESERVED5
Definition: mg32f157.h:709
__IO uint16_t DR34
Definition: mg32f157.h:331
Definition: mg32f157.h:142
__IO uint16_t RXCRCR
Definition: mg32f157.h:854
__IO uint16_t GTPR
Definition: mg32f157.h:931
__IO uint32_t SWTRIGR
Definition: mg32f157.h:412
uint16_t RESERVED3
Definition: mg32f157.h:926
__IO uint16_t DR17
Definition: mg32f157.h:297
Definition: mg32f157.h:162
__IO uint32_t DOR1
Definition: mg32f157.h:422
Definition: mg32f157.h:155
uint32_t RESERVED0
Definition: mg32f157.h:654
__IO uint32_t IDINTEN
Definition: mg32f157.h:825
Definition: mg32f157.h:156
__IO uint32_t IVR1
Definition: mg32f157.h:451
Definition: mg32f157.h:129
Definition: mg32f157.h:159
__IO uint32_t BMOD
Definition: mg32f157.h:821
__IO uint32_t CRL
Definition: mg32f157.h:636
__IO uint32_t DHR8RD
Definition: mg32f157.h:421
__IO uint32_t EMMC_DDR_REG
Definition: mg32f157.h:832
__IO uint32_t LPTR
Definition: mg32f157.h:882
__IO uint32_t SQR1
Definition: mg32f157.h:241
__IO uint32_t APERR_DPERR_FDSR_FDCFG
Definition: mg32f157.h:366
__IO uint32_t RINTSTS
Definition: mg32f157.h:812
__IO uint32_t KR
Definition: mg32f157.h:727
__IO uint16_t CR
Definition: mg32f157.h:281
__IO uint32_t FIFOTH
Definition: mg32f157.h:814
__IO uint32_t SR
Definition: mg32f157.h:230
__IO uint32_t EMR
Definition: mg32f157.h:589
__IO uint32_t OPTKEYR
Definition: mg32f157.h:604
uint32_t RESERVED0
Definition: mg32f157.h:667
__IO uint32_t TBBCNT
Definition: mg32f157.h:819
uint16_t RESERVED30
Definition: mg32f157.h:318
__IO uint16_t DR11
Definition: mg32f157.h:285
uint16_t RESERVED38
Definition: mg32f157.h:334
Definition: mg32f157.h:793
__IO uint16_t DR8
Definition: mg32f157.h:273
Definition: mg32f157.h:149
__IO uint16_t SR
Definition: mg32f157.h:848
uint16_t RESERVED15
Definition: mg32f157.h:288
__IO uint32_t JDR3
Definition: mg32f157.h:247
__IO uint16_t DR13
Definition: mg32f157.h:289
uint16_t RESERVED36
Definition: mg32f157.h:330
uint32_t RESERVED2
Definition: mg32f157.h:674
uint16_t RESERVED2
Definition: mg32f157.h:924
__IO uint32_t ACR
Definition: mg32f157.h:361
uint16_t RESERVED14
Definition: mg32f157.h:286
uint16_t RESERVED33
Definition: mg32f157.h:324
__IO uint16_t ALRH
Definition: mg32f157.h:783
Definition: mg32f157.h:133
__IO uint32_t IVR0
Definition: mg32f157.h:450
__IO uint32_t DR
Definition: mg32f157.h:249
Definition: mg32f157.h:131
uint16_t RESERVED6
Definition: mg32f157.h:270
__IO uint16_t DIVH
Definition: mg32f157.h:775
__IO uint32_t RESP0
Definition: mg32f157.h:807
__IO uint16_t DR36
Definition: mg32f157.h:335
__IO uint32_t PR
Definition: mg32f157.h:728
__IO uint8_t IDR
Definition: mg32f157.h:377
uint16_t RESERVED45
Definition: mg32f157.h:348