◆ ABR
QUADSPI alternate bytes registers, Address offset: 0x01C
◆ AR
QUADSPI address register, Address offset: 0x018
◆ CCR
QUADSPI communication configuration register, Address offset: 0x014
◆ CR
QUADSPI control register, Address offset: 0x000
◆ DCR
QUADSPI device configuration register, Address offset: 0x004
◆ DLR
QUADSPI data length register, Address offset: 0x010
◆ DR
QUADSPI data register, Address offset: 0x020
◆ FCR
QUADSPI flag clear register, Address offset: 0x00C
◆ LPTR
QUADSPI low-power timeout register, Address offset: 0x030
◆ PIR
QUADSPI polling interval register, Address offset: 0x02C
◆ PSMAR
QUADSPI polling status match register, Address offset: 0x028
◆ PSMKR
QUADSPI polling status mask register, Address offset: 0x024
◆ SR
QUADSPI status register, Address offset: 0x008
The documentation for this struct was generated from the following file: