Next: Adapteva Epiphany Options, Up: Submodel Options [Contents][Index]

#### 3.18.1 AArch64 Options

These options are defined for AArch64 implementations:

`-mabi=name`

  Generate code for the specified data model. Permissible values are ‘`ilp32`’ for SysV-like data model where int, long int and pointers are 32 bits, and ‘`lp64`’ for SysV-like data model where int is 32 bits, but long int and pointers are 64 bits.

  The default depends on the specific target configuration. Note that the LP64 and ILP32 ABIs are not link-compatible; you must compile your entire program with the same ABI, and link with a compatible set of libraries.

`-mbig-endian`

  Generate big-endian code. This is the default when GCC is configured for an ‘`aarch64_be-*-*`’ target.

`-mgeneral-regs-only`

  Generate code which uses only the general-purpose registers. This will prevent the compiler from using floating-point and Advanced SIMD registers but will not impose any restrictions on the assembler.

`-mlittle-endian`

  Generate little-endian code. This is the default when GCC is configured for an ‘`aarch64-*-*`’ but not an ‘`aarch64_be-*-*`’ target.

`-mcmodel=tiny`

  Generate code for the tiny code model. The program and its statically defined symbols must be within 1MB of each other. Programs can be statically or dynamically linked.

`-mcmodel=small`

  Generate code for the small code model. The program and its statically defined symbols must be within 4GB of each other. Programs can be statically or dynamically linked. This is the default code model.

`-mcmodel=large`

  Generate code for the large code model. This makes no assumptions about addresses and sizes of sections. Programs can be statically linked only.

`-mstrict-align`

  Avoid generating memory accesses that may not be aligned on a natural object boundary as described in the architecture specification.

`-momit-leaf-frame-pointer`
`-mno-omit-leaf-frame-pointer`

  Omit or keep the frame pointer in leaf functions. The former behavior is the default.

`-mtls-dialect=desc`

  Use TLS descriptors as the thread-local storage mechanism for dynamic accesses of TLS variables. This is the default.

`-mtls-dialect=traditional`

  Use traditional TLS as the thread-local storage mechanism for dynamic accesses of TLS variables.

`-mtls-size=size`

  Specify bit size of immediate TLS offsets. Valid values are 12, 24, 32, 48. This option requires binutils 2.26 or newer.

`-mfix-cortex-a53-835769`
`-mno-fix-cortex-a53-835769`

  Enable or disable the workaround for the ARM Cortex-A53 erratum number 835769. This involves inserting a NOP instruction between memory instructions and 64-bit integer multiply-accumulate instructions.

`-mfix-cortex-a53-843419`
`-mno-fix-cortex-a53-843419`

  Enable or disable the workaround for the ARM Cortex-A53 erratum number 843419. This erratum workaround is made at link time and this will only pass the corresponding flag to the linker.

`-mlow-precision-recip-sqrt`
`-mno-low-precision-recip-sqrt`

  Enable or disable the reciprocal square root approximation. This option only has an effect if `-ffast-math` or `-funsafe-math-optimizations` is used as well. Enabling this reduces precision of reciprocal square root results to about 16 bits for single precision and to 32 bits for double precision.

`-mlow-precision-sqrt`
`-mno-low-precision-sqrt`

  Enable or disable the square root approximation. This option only has an effect if `-ffast-math` or `-funsafe-math-optimizations` is used as well. Enabling this reduces precision of square root results to about 16 bits for single precision and to 32 bits for double precision. If enabled, it implies `-mlow-precision-recip-sqrt`.

`-mlow-precision-div`
`-mno-low-precision-div`

  Enable or disable the division approximation. This option only has an effect if `-ffast-math` or `-funsafe-math-optimizations` is used as well. Enabling this reduces precision of division results to about 16 bits for single precision and to 32 bits for double precision.

`-march=name`

  Specify the name of the target architecture and, optionally, one or more feature modifiers. This option has the form `-march=arch{+[no]feature}*`.

  The permissible values for arch are ‘`armv8-a`’, ‘`armv8.1-a`’, ‘`armv8.2-a`’, ‘`armv8.3-a`’ or native.

  The value ‘`armv8.3-a`’ implies ‘`armv8.2-a`’ and enables compiler support for the ARMv8.3-A architecture extensions.

  The value ‘`armv8.2-a`’ implies ‘`armv8.1-a`’ and enables compiler support for the ARMv8.2-A architecture extensions.

  The value ‘`armv8.1-a`’ implies ‘`armv8-a`’ and enables compiler support for the ARMv8.1-A architecture extension. In particular, it enables the ‘`+crc`’ and ‘`+lse`’ features.

  The value ‘`native`’ is available on native AArch64 GNU/Linux and causes the compiler to pick the architecture of the host system. This option has no effect if the compiler is unable to recognize the architecture of the host system,

  The permissible values for feature are listed in the sub-section on `-march` and `-mcpu` Feature Modifiers. Where conflicting feature modifiers are specified, the right-most feature is used.

  GCC uses name to determine what kind of instructions it can emit when generating assembly code. If `-march` is specified without either of `-mtune` or `-mcpu` also being specified, the code is tuned to perform well across a range of target processors implementing the target architecture.

`-mtune=name`

  Specify the name of the target processor for which GCC should tune the performance of the code. Permissible values for this option are: ‘`generic`’, ‘`cortex-a35`’, ‘`cortex-a53`’, ‘`cortex-a57`’, ‘`cortex-a72`’, ‘`cortex-a73`’, ‘`exynos-m1`’, ‘`falkor`’, ‘`qdf24xx`’, ‘`xgene1`’, ‘`vulcan`’, ‘`thunderx`’, ‘`thunderxt88`’, ‘`thunderxt88p1`’, ‘`thunderxt81`’, ‘`thunderxt83`’, ‘`thunderx2t99`’, ‘`cortex-a57.cortex-a53`’, ‘`cortex-a72.cortex-a53`’, ‘`cortex-a73.cortex-a35`’, ‘`cortex-a73.cortex-a53`’, ‘`native`’.

  The values ‘`cortex-a57.cortex-a53`’, ‘`cortex-a72.cortex-a53`’, ‘`cortex-a73.cortex-a35`’, ‘`cortex-a73.cortex-a53`’ specify that GCC should tune for a big.LITTLE system.

  Additionally on native AArch64 GNU/Linux systems the value ‘`native`’ tunes performance to the host system. This option has no effect if the compiler is unable to recognize the processor of the host system.

  Where none of `-mtune=`, `-mcpu=` or `-march=` are specified, the code is tuned to perform well across a range of target processors.

  This option cannot be suffixed by feature modifiers.

`-mcpu=name`

  Specify the name of the target processor, optionally suffixed by one or more feature modifiers. This option has the form `-mcpu=cpu{+[no]feature}*`, where the permissible values for cpu are the same as those available for `-mtune`. The permissible values for feature are documented in the sub-section on `-march` and `-mcpu` Feature Modifiers. Where conflicting feature modifiers are specified, the right-most feature is used.

  GCC uses name to determine what kind of instructions it can emit when generating assembly code (as if by `-march`) and to determine the target processor for which to tune for performance (as if by `-mtune`). Where this option is used in conjunction with `-march` or `-mtune`, those options take precedence over the appropriate part of this option.

`-moverride=string`

  Override tuning decisions made by the back-end in response to a `-mtune=` switch. The syntax, semantics, and accepted values for string in this option are not guaranteed to be consistent across releases.

  This option is only intended to be useful when developing GCC.

`-mpc-relative-literal-loads`

  Enable PC-relative literal loads. With this option literal pools are accessed using a single instruction and emitted after each function. This limits the maximum size of functions to 1MB. This is enabled by default for `-mcmodel=tiny`.

`-msign-return-address=scope`

  Select the function scope on which return address signing will be applied. Permissible values are ‘`none`’, which disables return address signing, ‘`non-leaf`’, which enables pointer signing for functions which are not leaf functions, and ‘`all`’, which enables pointer signing for all functions. The default value is ‘`none`’.

#### 3.18.1.1 `-march` and `-mcpu` Feature Modifiers

Feature modifiers used with `-march` and `-mcpu` can be any of the following and their inverses `nofeature`:

‘`crc`’

  Enable CRC extension. This is on by default for `-march=armv8.1-a`.

‘`crypto`’

  Enable Crypto extension. This also enables Advanced SIMD and floating-point instructions.

‘`fp`’

  Enable floating-point instructions. This is on by default for all possible values for options `-march` and `-mcpu`.

‘`simd`’

  Enable Advanced SIMD instructions. This also enables floating-point instructions. This is on by default for all possible values for options `-march` and `-mcpu`.

‘`lse`’

  Enable Large System Extension instructions. This is on by default for `-march=armv8.1-a`.

‘`fp16`’

  Enable FP16 extension. This also enables floating-point instructions.

Feature `crypto` implies `simd`, which implies `fp`. Conversely, `nofp` implies `nosimd`, which implies `nocrypto`.

Next: Adapteva Epiphany Options, Up: Submodel Options [Contents][Index]