MG32L003 Standard Peripherals Firmware Library

core_cm0plus.h
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1 /**************************************************************************/
7 /*
8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29 #endif
30
31 #ifndef __CORE_CM0PLUS_H_GENERIC
32 #define __CORE_CM0PLUS_H_GENERIC
33
34 #include <stdint.h>
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
55 /*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
63 #include "cmsis_version.h"
64
65 /* CMSIS CM0+ definitions */
66 #define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
67 #define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
68 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
69 __CM0PLUS_CMSIS_VERSION_SUB )
71 #define __CORTEX_M (0U)
76 #define __FPU_USED 0U
77
78 #if defined ( __CC_ARM )
79 #if defined __TARGET_FPU_VFP
80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
81 #endif
82
83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84 #if defined __ARM_PCS_VFP
85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
86 #endif
87
88 #elif defined ( __GNUC__ )
89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
91 #endif
92
93 #elif defined ( __ICCARM__ )
94 #if defined __ARMVFP__
95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
96 #endif
97
98 #elif defined ( __TI_ARM__ )
99 #if defined __TI_VFP_SUPPORT__
100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
101 #endif
102
103 #elif defined ( __TASKING__ )
104 #if defined __FPU_VFP__
105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106 #endif
107
108 #elif defined ( __CSMC__ )
109 #if ( __CSMC__ & 0x400U)
110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
111 #endif
112
113 #endif
114
115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
116
117
118 #ifdef __cplusplus
119 }
120 #endif
121
122 #endif /* __CORE_CM0PLUS_H_GENERIC */
123
124 #ifndef __CMSIS_GENERIC
125
126 #ifndef __CORE_CM0PLUS_H_DEPENDANT
127 #define __CORE_CM0PLUS_H_DEPENDANT
128
129 #ifdef __cplusplus
130 extern "C" {
131 #endif
132
133 /* check device defines and use defaults */
134 #if defined __CHECK_DEVICE_DEFINES
135 #ifndef __CM0PLUS_REV
136 #define __CM0PLUS_REV 0x0000U
137 #warning "__CM0PLUS_REV not defined in device header file; using default!"
138 #endif
139
140 #ifndef __MPU_PRESENT
141 #define __MPU_PRESENT 0U
142 #warning "__MPU_PRESENT not defined in device header file; using default!"
143 #endif
144
145 #ifndef __VTOR_PRESENT
146 #define __VTOR_PRESENT 0U
147 #warning "__VTOR_PRESENT not defined in device header file; using default!"
148 #endif
149
150 #ifndef __NVIC_PRIO_BITS
151 #define __NVIC_PRIO_BITS 2U
152 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
153 #endif
154
155 #ifndef __Vendor_SysTickConfig
156 #define __Vendor_SysTickConfig 0U
157 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
158 #endif
159 #endif
160
161 /* IO definitions (access restrictions to peripheral registers) */
169 #ifdef __cplusplus
170 #define __I volatile
171 #else
172 #define __I volatile const
173 #endif
174 #define __O volatile
175 #define __IO volatile
177 /* following defines should be used for structure members */
178 #define __IM volatile const
179 #define __OM volatile
180 #define __IOM volatile
182
186 /*******************************************************************************
187 * Register Abstraction
188 Core Register contain:
189 - Core Register
190 - Core NVIC Register
191 - Core SCB Register
192 - Core SysTick Register
193 - Core MPU Register
194 ******************************************************************************/
195
210 typedef union
211 {
212 struct
213 {
214 uint32_t _reserved0:28;
215 uint32_t V:1;
216 uint32_t C:1;
217 uint32_t Z:1;
218 uint32_t N:1;
219 } b;
220 uint32_t w;
221 } APSR_Type;
222
223 /* APSR Register Definitions */
224 #define APSR_N_Pos 31U
225 #define APSR_N_Msk (1UL << APSR_N_Pos)
227 #define APSR_Z_Pos 30U
228 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
230 #define APSR_C_Pos 29U
231 #define APSR_C_Msk (1UL << APSR_C_Pos)
233 #define APSR_V_Pos 28U
234 #define APSR_V_Msk (1UL << APSR_V_Pos)
240 typedef union
241 {
242 struct
243 {
244 uint32_t ISR:9;
245 uint32_t _reserved0:23;
246 } b;
247 uint32_t w;
248 } IPSR_Type;
249
250 /* IPSR Register Definitions */
251 #define IPSR_ISR_Pos 0U
252 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
258 typedef union
259 {
260 struct
261 {
262 uint32_t ISR:9;
263 uint32_t _reserved0:15;
264 uint32_t T:1;
265 uint32_t _reserved1:3;
266 uint32_t V:1;
267 uint32_t C:1;
268 uint32_t Z:1;
269 uint32_t N:1;
270 } b;
271 uint32_t w;
272 } xPSR_Type;
273
274 /* xPSR Register Definitions */
275 #define xPSR_N_Pos 31U
276 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
278 #define xPSR_Z_Pos 30U
279 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
281 #define xPSR_C_Pos 29U
282 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
284 #define xPSR_V_Pos 28U
285 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
287 #define xPSR_T_Pos 24U
288 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
290 #define xPSR_ISR_Pos 0U
291 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
297 typedef union
298 {
299 struct
300 {
301 uint32_t nPRIV:1;
302 uint32_t SPSEL:1;
303 uint32_t _reserved1:30;
304 } b;
305 uint32_t w;
306 } CONTROL_Type;
307
308 /* CONTROL Register Definitions */
309 #define CONTROL_SPSEL_Pos 1U
310 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
312 #define CONTROL_nPRIV_Pos 0U
313 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
315
328 typedef struct
329 {
330 __IOM uint32_t ISER[1U];
331 uint32_t RESERVED0[31U];
332 __IOM uint32_t ICER[1U];
333 uint32_t RSERVED1[31U];
334 __IOM uint32_t ISPR[1U];
335 uint32_t RESERVED2[31U];
336 __IOM uint32_t ICPR[1U];
337 uint32_t RESERVED3[31U];
338 uint32_t RESERVED4[64U];
339 __IOM uint32_t IP[8U];
340 } NVIC_Type;
341
355 typedef struct
356 {
357 __IM uint32_t CPUID;
358 __IOM uint32_t ICSR;
359 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
360 __IOM uint32_t VTOR;
361 #else
362 uint32_t RESERVED0;
363 #endif
364 __IOM uint32_t AIRCR;
365 __IOM uint32_t SCR;
366 __IOM uint32_t CCR;
367 uint32_t RESERVED1;
368 __IOM uint32_t SHP[2U];
369 __IOM uint32_t SHCSR;
370 } SCB_Type;
371
372 /* SCB CPUID Register Definitions */
373 #define SCB_CPUID_IMPLEMENTER_Pos 24U
374 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
376 #define SCB_CPUID_VARIANT_Pos 20U
377 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
379 #define SCB_CPUID_ARCHITECTURE_Pos 16U
380 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
382 #define SCB_CPUID_PARTNO_Pos 4U
383 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
385 #define SCB_CPUID_REVISION_Pos 0U
386 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
388 /* SCB Interrupt Control State Register Definitions */
389 #define SCB_ICSR_NMIPENDSET_Pos 31U
390 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
392 #define SCB_ICSR_PENDSVSET_Pos 28U
393 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
395 #define SCB_ICSR_PENDSVCLR_Pos 27U
396 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
398 #define SCB_ICSR_PENDSTSET_Pos 26U
399 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
401 #define SCB_ICSR_PENDSTCLR_Pos 25U
402 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
404 #define SCB_ICSR_ISRPREEMPT_Pos 23U
405 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
407 #define SCB_ICSR_ISRPENDING_Pos 22U
408 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
410 #define SCB_ICSR_VECTPENDING_Pos 12U
411 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
413 #define SCB_ICSR_VECTACTIVE_Pos 0U
414 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
416 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
417 /* SCB Interrupt Control State Register Definitions */
418 #define SCB_VTOR_TBLOFF_Pos 8U
419 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)
420 #endif
421
422 /* SCB Application Interrupt and Reset Control Register Definitions */
423 #define SCB_AIRCR_VECTKEY_Pos 16U
424 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
426 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
427 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
429 #define SCB_AIRCR_ENDIANESS_Pos 15U
430 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
432 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
433 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
435 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
436 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
438 /* SCB System Control Register Definitions */
439 #define SCB_SCR_SEVONPEND_Pos 4U
440 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
442 #define SCB_SCR_SLEEPDEEP_Pos 2U
443 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
445 #define SCB_SCR_SLEEPONEXIT_Pos 1U
446 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
448 /* SCB Configuration Control Register Definitions */
449 #define SCB_CCR_STKALIGN_Pos 9U
450 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
452 #define SCB_CCR_UNALIGN_TRP_Pos 3U
453 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
455 /* SCB System Handler Control and State Register Definitions */
456 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
457 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
459
472 typedef struct
473 {
474 __IOM uint32_t CTRL;
475 __IOM uint32_t LOAD;
476 __IOM uint32_t VAL;
477 __IM uint32_t CALIB;
478 } SysTick_Type;
479
480 /* SysTick Control / Status Register Definitions */
481 #define SysTick_CTRL_COUNTFLAG_Pos 16U
482 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
484 #define SysTick_CTRL_CLKSOURCE_Pos 2U
485 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
487 #define SysTick_CTRL_TICKINT_Pos 1U
488 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
490 #define SysTick_CTRL_ENABLE_Pos 0U
491 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
493 /* SysTick Reload Register Definitions */
494 #define SysTick_LOAD_RELOAD_Pos 0U
495 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
497 /* SysTick Current Register Definitions */
498 #define SysTick_VAL_CURRENT_Pos 0U
499 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
501 /* SysTick Calibration Register Definitions */
502 #define SysTick_CALIB_NOREF_Pos 31U
503 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
505 #define SysTick_CALIB_SKEW_Pos 30U
506 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
508 #define SysTick_CALIB_TENMS_Pos 0U
509 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
511
513 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
514
524 typedef struct
525 {
526 __IM uint32_t TYPE;
527 __IOM uint32_t CTRL;
528 __IOM uint32_t RNR;
529 __IOM uint32_t RBAR;
530 __IOM uint32_t RASR;
531 } MPU_Type;
532
533 #define MPU_TYPE_RALIASES 1U
534
535 /* MPU Type Register Definitions */
536 #define MPU_TYPE_IREGION_Pos 16U
537 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
539 #define MPU_TYPE_DREGION_Pos 8U
540 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
542 #define MPU_TYPE_SEPARATE_Pos 0U
543 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
545 /* MPU Control Register Definitions */
546 #define MPU_CTRL_PRIVDEFENA_Pos 2U
547 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
549 #define MPU_CTRL_HFNMIENA_Pos 1U
550 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
552 #define MPU_CTRL_ENABLE_Pos 0U
553 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
555 /* MPU Region Number Register Definitions */
556 #define MPU_RNR_REGION_Pos 0U
557 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
559 /* MPU Region Base Address Register Definitions */
560 #define MPU_RBAR_ADDR_Pos 8U
561 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)
563 #define MPU_RBAR_VALID_Pos 4U
564 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
566 #define MPU_RBAR_REGION_Pos 0U
567 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
569 /* MPU Region Attribute and Size Register Definitions */
570 #define MPU_RASR_ATTRS_Pos 16U
571 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
573 #define MPU_RASR_XN_Pos 28U
574 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
576 #define MPU_RASR_AP_Pos 24U
577 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
579 #define MPU_RASR_TEX_Pos 19U
580 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
582 #define MPU_RASR_S_Pos 18U
583 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
585 #define MPU_RASR_C_Pos 17U
586 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
588 #define MPU_RASR_B_Pos 16U
589 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
591 #define MPU_RASR_SRD_Pos 8U
592 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
594 #define MPU_RASR_SIZE_Pos 1U
595 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
597 #define MPU_RASR_ENABLE_Pos 0U
598 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/)
600
601 #endif
602
603
611
627 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
628
635 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
636
647 /* Memory mapping of Core Hardware */
648 #define SCS_BASE (0xE000E000UL)
649 #define SysTick_BASE (SCS_BASE + 0x0010UL)
650 #define NVIC_BASE (SCS_BASE + 0x0100UL)
651 #define SCB_BASE (SCS_BASE + 0x0D00UL)
653 #define SCB ((SCB_Type *) SCB_BASE )
654 #define SysTick ((SysTick_Type *) SysTick_BASE )
655 #define NVIC ((NVIC_Type *) NVIC_BASE )
657 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
658 #define MPU_BASE (SCS_BASE + 0x0D90UL)
659 #define MPU ((MPU_Type *) MPU_BASE )
660 #endif
661
666 /*******************************************************************************
667 * Hardware Abstraction Layer
668 Core Function Interface contains:
669 - Core NVIC Functions
670 - Core SysTick Functions
671 - Core Register Access Functions
672 ******************************************************************************/
679 /* ########################## NVIC functions #################################### */
687 #ifdef CMSIS_NVIC_VIRTUAL
688 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
689 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
690 #endif
691 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
692 #else
693 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
694 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
695 #define NVIC_EnableIRQ __NVIC_EnableIRQ
696 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
697 #define NVIC_DisableIRQ __NVIC_DisableIRQ
698 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
699 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
700 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
701 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
702 #define NVIC_SetPriority __NVIC_SetPriority
703 #define NVIC_GetPriority __NVIC_GetPriority
704 #define NVIC_SystemReset __NVIC_SystemReset
705 #endif /* CMSIS_NVIC_VIRTUAL */
706
707 #ifdef CMSIS_VECTAB_VIRTUAL
708 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
709 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
710 #endif
711 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
712 #else
713 #define NVIC_SetVector __NVIC_SetVector
714 #define NVIC_GetVector __NVIC_GetVector
715 #endif /* (CMSIS_VECTAB_VIRTUAL) */
716
717 #define NVIC_USER_IRQ_OFFSET 16
718
719
720 /* The following EXC_RETURN values are saved the LR on exception entry */
721 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
722 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
723 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
724
725
726 /* Interrupt Priorities are WORD accessible only under Armv6-M */
727 /* The following MACROS handle generation of the register offset and byte masks */
728 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
729 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
730 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
731
732 #define __NVIC_SetPriorityGrouping(X) (void)(X)
733 #define __NVIC_GetPriorityGrouping() (0U)
734
741 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
742 {
743 if ((int32_t)(IRQn) >= 0)
744 {
745 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
746 }
747 }
748
749
758 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
759 {
760 if ((int32_t)(IRQn) >= 0)
761 {
762 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
763 }
764 else
765 {
766 return(0U);
767 }
768 }
769
770
777 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
778 {
779 if ((int32_t)(IRQn) >= 0)
780 {
781 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
782 __DSB();
783 __ISB();
784 }
785 }
786
787
796 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
797 {
798 if ((int32_t)(IRQn) >= 0)
799 {
800 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
801 }
802 else
803 {
804 return(0U);
805 }
806 }
807
808
815 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
816 {
817 if ((int32_t)(IRQn) >= 0)
818 {
819 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
820 }
821 }
822
823
830 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
831 {
832 if ((int32_t)(IRQn) >= 0)
833 {
834 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
835 }
836 }
837
838
848 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
849 {
850 if ((int32_t)(IRQn) >= 0)
851 {
852 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
853 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
854 }
855 else
856 {
857 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
858 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
859 }
860 }
861
862
872 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
873 {
874
875 if ((int32_t)(IRQn) >= 0)
876 {
877 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
878 }
879 else
880 {
881 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
882 }
883 }
884
885
897 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
898 {
899 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
900 uint32_t PreemptPriorityBits;
901 uint32_t SubPriorityBits;
902
903 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
904 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
905
906 return (
907 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
908 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
909 );
910 }
911
912
924 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
925 {
926 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
927 uint32_t PreemptPriorityBits;
928 uint32_t SubPriorityBits;
929
930 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
931 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
932
933 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
934 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
935 }
936
937
948 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
949 {
950 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
951 uint32_t *vectors = (uint32_t *)SCB->VTOR;
952 #else
953 uint32_t *vectors = (uint32_t *)0x0U;
954 #endif
955 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
956 }
957
958
967 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
968 {
969 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
970 uint32_t *vectors = (uint32_t *)SCB->VTOR;
971 #else
972 uint32_t *vectors = (uint32_t *)0x0U;
973 #endif
974 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
975
976 }
977
978
983 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
984 {
985 __DSB(); /* Ensure all outstanding memory accesses included
986 buffered write are completed before reset */
987 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
988 SCB_AIRCR_SYSRESETREQ_Msk);
989 __DSB(); /* Ensure completion of memory access */
990
991 for(;;) /* wait until reset */
992 {
993 __NOP();
994 }
995 }
996
999 /* ########################## MPU functions #################################### */
1000
1001 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1002
1003 #include "mpu_armv7.h"
1004
1005 #endif
1006
1007 /* ########################## FPU functions #################################### */
1023 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
1024 {
1025 return 0U; /* No FPU */
1026 }
1027
1028
1033 /* ################################## SysTick function ############################################ */
1041 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
1042
1054 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1055 {
1056 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1057 {
1058 return (1UL); /* Reload value impossible */
1059 }
1060
1061 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1062 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1063 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1064 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1065 SysTick_CTRL_TICKINT_Msk |
1066 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1067 return (0UL); /* Function successful */
1068 }
1069
1070 #endif
1071
1077 #ifdef __cplusplus
1078 }
1079 #endif
1080
1081 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
1082
1083 #endif /* __CMSIS_GENERIC */
__NOP
#define __NOP
No Operation
Definition: cmsis_armcc.h:387
CONTROL_Type::nPRIV
uint32_t nPRIV
Definition: core_cm0plus.h:301
CONTROL_Type::SPSEL
uint32_t SPSEL
Definition: core_cm0plus.h:302
CONTROL_Type::_reserved1
uint32_t _reserved1
Definition: core_cm0plus.h:303
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status
Definition: core_cm0plus.h:758
SysTick
#define SysTick
Definition: core_cm0plus.h:654
APSR_Type::Z
uint32_t Z
Definition: core_cm0plus.h:217
IPSR_Type::w
uint32_t w
Definition: core_cm0plus.h:247
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector
Definition: core_cm0plus.h:967
xPSR_Type::_reserved1
uint32_t _reserved1
Definition: core_cm0plus.h:265
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt
Definition: core_cm0plus.h:741
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt
Definition: core_cm0plus.h:796
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt
Definition: core_cm0plus.h:815
xPSR_Type::ISR
uint32_t ISR
Definition: core_cm0plus.h:262
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_cm0plus.h:240
xPSR_Type::w
uint32_t w
Definition: core_cm0plus.h:271
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: core_cm0plus.h:1023
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority
Definition: core_cm0plus.h:924
NVIC
#define NVIC
Definition: core_cm0plus.h:655
__DSB
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier
Definition: cmsis_gcc.h:877
cmsis_version.h
CMSIS Core(M) Version definitions
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_cm0plus.h:355
SCB
#define SCB
Definition: core_cm0plus.h:653
APSR_Type::N
uint32_t N
Definition: core_cm0plus.h:218
xPSR_Type::C
uint32_t C
Definition: core_cm0plus.h:267
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector
Definition: core_cm0plus.h:948
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt
Definition: core_cm0plus.h:777
APSR_Type::_reserved0
uint32_t _reserved0
Definition: core_cm0plus.h:214
xPSR_Type::_reserved0
uint32_t _reserved0
Definition: core_cm0plus.h:263
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm0plus.h:328
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_cm0plus.h:472
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm0plus.h:423
xPSR_Type::T
uint32_t T
Definition: core_cm0plus.h:264
APSR_Type::w
uint32_t w
Definition: core_cm0plus.h:220
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority
Definition: core_cm0plus.h:848
APSR_Type::C
uint32_t C
Definition: core_cm0plus.h:216
xPSR_Type::N
uint32_t N
Definition: core_cm0plus.h:269
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm0plus.h:433
cmsis_compiler.h
CMSIS compiler generic header file
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_cm0plus.h:210
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm0plus.h:495
IPSR_Type::ISR
uint32_t ISR
Definition: core_cm0plus.h:244
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt
Definition: core_cm0plus.h:830
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_cm0plus.h:297
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm0plus.h:485
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm0plus.h:491
xPSR_Type::V
uint32_t V
Definition: core_cm0plus.h:266
APSR_Type::V
uint32_t V
Definition: core_cm0plus.h:215
CONTROL_Type::w
uint32_t w
Definition: core_cm0plus.h:305
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority
Definition: core_cm0plus.h:897
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset
Definition: core_cm0plus.h:983
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_cm0plus.h:258
xPSR_Type::Z
uint32_t Z
Definition: core_cm0plus.h:268
__ISB
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier
Definition: cmsis_gcc.h:866
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority
Definition: core_cm0plus.h:872
IPSR_Type::_reserved0
uint32_t _reserved0
Definition: core_cm0plus.h:245
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm0plus.h:488