MG32L003 Standard Peripherals Firmware Library

模块
Defines and Type Definitions

Type definitions and defines for Cortex-M processor based devices. 更多...

## 模块
| Status and Control Registers
| Core Register type definitions.
| Nested Vectored Interrupt Controller (NVIC)
| Type definitions for the NVIC Registers
| System Control Block (SCB)
| Type definitions for the System Control Block Registers
| System Tick Timer (SysTick)
| Type definitions for the System Timer Registers.
| Core Debug Registers (CoreDebug)
| Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M0+ header file.
| Core register bit field macros
| Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
| Core Definitions
| Definitions for base addresses, unions, and structures.

## 详细描述

Type definitions and defines for Cortex-M processor based devices.