MG32L003 Standard Peripherals Firmware Library

mg32l003_adc.h
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10 /* Define to prevent recursive inclusion -------------------------------------*/
11 #ifndef __MG32L003_ADC_H
12 #define __MG32L003_ADC_H
13
14 #ifdef __cplusplus
15 extern "C" {
16 #endif
17
18 /* Includes ------------------------------------------------------------------*/
19 #include "mg32l003.h"
20
29 /* Exported types ------------------------------------------------------------*/
30
34 typedef struct
35 {
36 uint32_t ADC_SamplingTime;
39 uint32_t ADC_SingleChannelSel;
42 uint32_t ADC_ClkSel;
45 uint32_t ADC_SingleContinueMode;
48 uint32_t ADC_AutoAccumulation;
51 uint32_t ADC_CircleMode;
54 uint32_t ADC_ConversionTimes;
57 uint32_t ADC_ContinueChannelSel;
60 uint32_t ADC_ExternalTrigConv1;
65 uint32_t ADC_ExternalTrigConv2;
69 } ADC_InitTypeDef;
70
71 /* Exported constants --------------------------------------------------------*/
72
80 #define ADC_SAMPLE_4CYCLE 0x00U
81 #define ADC_SAMPLE_8CYCLE 0x800UL
83 #define IS_ADC_SAMPLE_CYCLE(CYLCE) (((CYLCE) == ADC_SAMPLE_4CYCLE) || ((CYLCE) == ADC_SAMPLE_8CYCLE))
84
91 #define ADC_SINGLE_CHANNEL_0 (0x00000000U)
92 #define ADC_SINGLE_CHANNEL_1 (ADC_CR0_SEL_0)
93 #define ADC_SINGLE_CHANNEL_2 (ADC_CR0_SEL_1)
94 #define ADC_SINGLE_CHANNEL_3 (ADC_CR0_SEL_1 | ADC_CR0_SEL_0)
95 #define ADC_SINGLE_CHANNEL_4 (ADC_CR0_SEL_2)
96 #define ADC_SINGLE_CHANNEL_5 (ADC_CR0_SEL_2 | ADC_CR0_SEL_0)
97 #define ADC_SINGLE_CHANNEL_6 (ADC_CR0_SEL_2 | ADC_CR0_SEL_1)
98 #define ADC_SINGLE_CHANNEL_7 (ADC_CR0_SEL_2 | ADC_CR0_SEL_1 | ADC_CR0_SEL_0)
100 #define ADC_SINGLE_CHANNEL_8 (ADC_CR0_SEL_3)
101 #define ADC_SINGLE_CHANNEL_9 (ADC_CR0_SEL_3 | ADC_CR0_SEL_0)
102 #define ADC_SINGLE_CHANNEL_10 (ADC_CR0_SEL_3 | ADC_CR0_SEL_1)
103 #define ADC_SINGLE_CHANNEL_11 (ADC_CR0_SEL_3 | ADC_CR0_SEL_1 | ADC_CR0_SEL_0)
104 #define ADC_SINGLE_CHANNEL_12 (ADC_CR0_SEL_3 | ADC_CR0_SEL_2)
105 #define ADC_SINGLE_CHANNEL_13 (ADC_CR0_SEL_3 | ADC_CR0_SEL_2 | ADC_CR0_SEL_0)
106 #define ADC_SINGLE_CHANNEL_14 (ADC_CR0_SEL_3 | ADC_CR0_SEL_2 | ADC_CR0_SEL_1)
107 #define ADC_SINGLE_CHANNEL_15 (ADC_CR0_SEL_3 | ADC_CR0_SEL_2 | ADC_CR0_SEL_1 | ADC_CR0_SEL_0)
109 #define IS_ADC_SINGLE_CHANNEL(CHANNEL) (((CHANNEL) == ADC_SINGLE_CHANNEL_0) || \
110 ((CHANNEL) == ADC_SINGLE_CHANNEL_1) || \
111 ((CHANNEL) == ADC_SINGLE_CHANNEL_2) || \
112 ((CHANNEL) == ADC_SINGLE_CHANNEL_3) || \
113 ((CHANNEL) == ADC_SINGLE_CHANNEL_4) || \
114 ((CHANNEL) == ADC_SINGLE_CHANNEL_5) || \
115 ((CHANNEL) == ADC_SINGLE_CHANNEL_6) || \
116 ((CHANNEL) == ADC_SINGLE_CHANNEL_7) || \
117 ((CHANNEL) == ADC_SINGLE_CHANNEL_8) || \
118 ((CHANNEL) == ADC_SINGLE_CHANNEL_9) || \
119 ((CHANNEL) == ADC_SINGLE_CHANNEL_10) || \
120 ((CHANNEL) == ADC_SINGLE_CHANNEL_11) || \
121 ((CHANNEL) == ADC_SINGLE_CHANNEL_12) || \
122 ((CHANNEL) == ADC_SINGLE_CHANNEL_13) || \
123 ((CHANNEL) == ADC_SINGLE_CHANNEL_14) || \
124 ((CHANNEL) == ADC_SINGLE_CHANNEL_15))
125
132 #define ADC_CLOCK_PCLK_DIV1 (0x00000000U)
133 #define ADC_CLOCK_PCLK_DIV2 (ADC_CR0_CLKSEL_0)
134 #define ADC_CLOCK_PCLK_DIV4 (ADC_CR0_CLKSEL_1)
135 #define ADC_CLOCK_PCLK_DIV8 (ADC_CR0_CLKSEL_1 | ADC_CR0_CLKSEL_0)
136 #define ADC_CLOCK_PCLK_DIV16 (ADC_CR0_CLKSEL_2)
137 #define ADC_CLOCK_PCLK_DIV32 (ADC_CR0_CLKSEL_2 | ADC_CR0_CLKSEL_0)
138 #define ADC_CLOCK_PCLK_DIV64 (ADC_CR0_CLKSEL_2 | ADC_CR0_CLKSEL_1)
139 #define ADC_CLOCK_PCLK_DIV128 (ADC_CR0_CLKSEL_2 | ADC_CR0_CLKSEL_1 | ADC_CR0_CLKSEL_0)
141 #define IS_ADC_CLOCK_PCLK_DIV(CLOCK) (((CLOCK) == ADC_CLOCK_PCLK_DIV1) || ((CLOCK) == ADC_CLOCK_PCLK_DIV2) || \
142 ((CLOCK) == ADC_CLOCK_PCLK_DIV4) || ((CLOCK) == ADC_CLOCK_PCLK_DIV8) || \
143 ((CLOCK) == ADC_CLOCK_PCLK_DIV16) || ((CLOCK) == ADC_CLOCK_PCLK_DIV32) || \
144 ((CLOCK) == ADC_CLOCK_PCLK_DIV64) || ((CLOCK) == ADC_CLOCK_PCLK_DIV128))
145
152 #define ADC_MODE_SINGLE (0x00000000U)
153 #define ADC_MODE_CONTINUE (ADC_CR1_CT)
155 #define IS_ADC_SINGLEMODE(MODE) (((MODE) == ADC_MODE_SINGLE) || ((MODE) == ADC_MODE_CONTINUE))
156
163 #define ADC_None_Threshold_Compare (0x00000000)
164 #define ADC_Low_Threshold_Compare (0x01 << 12)
165 #define ADC_High_Threshold_Compare (0x01 << 13)
166 #define ADC_Range_Threshold_Compare (0x01 << 14)
168 #define ADC_Threshold_Comapre_Mask (ADC_Low_Threshold_Compare | ADC_High_Threshold_Compare | ADC_Range_Threshold_Compare)
169 #define ADC_Threshold_Compare_All ADC_Threshold_Comapre_Mask
170
177 #define ADC_AUTOACC_DISABLE (0x00000000U)
178 #define ADC_AUTOACC_ENABLE (ADC_CR1_RACC_EN)
180 #define IS_ADC_ACCMULATION(ACC) (((ACC) == ADC_AUTOACC_ENABLE) || ((ACC) == ADC_AUTOACC_DISABLE))
181
188 #define ADC_MULTICHANNEL_NONCIRCLE (0x00000000U)
189 #define ADC_MULTICHANNEL_CIRCLE (ADC_CR2_CIRCLE_MODE)
191 #define IS_ADC_CIRCLEMODE(MODE) (((MODE) == ADC_MULTICHANNEL_NONCIRCLE) || ((MODE) == ADC_MULTICHANNEL_CIRCLE))
192
199 #define ADC_CONTINUE_CHANNEL_0 (ADC_CR2_CHEN_0)
200 #define ADC_CONTINUE_CHANNEL_1 (ADC_CR2_CHEN_1)
201 #define ADC_CONTINUE_CHANNEL_2 (ADC_CR2_CHEN_2)
202 #define ADC_CONTINUE_CHANNEL_3 (ADC_CR2_CHEN_3)
203 #define ADC_CONTINUE_CHANNEL_4 (ADC_CR2_CHEN_4)
204 #define ADC_CONTINUE_CHANNEL_5 (ADC_CR2_CHEN_5)
205 #define ADC_CONTINUE_CHANNEL_6 (ADC_CR2_CHEN_6)
206 #define ADC_CONTINUE_CHANNEL_7 (ADC_CR2_CHEN_7)
208 #define ADC_CONTINUE_CHANNEL_8 (ADC_CR2_CHEN_8 )
209 #define ADC_CONTINUE_CHANNEL_9 (ADC_CR2_CHEN_9 )
210 #define ADC_CONTINUE_CHANNEL_10 (ADC_CR2_CHEN_10)
211 #define ADC_CONTINUE_CHANNEL_11 (ADC_CR2_CHEN_11)
212 #define ADC_CONTINUE_CHANNEL_12 (ADC_CR2_CHEN_12)
213 #define ADC_CONTINUE_CHANNEL_13 (ADC_CR2_CHEN_13)
214 #define ADC_CONTINUE_CHANNEL_14 (ADC_CR2_CHEN_14)
215 #define ADC_CONTINUE_CHANNEL_15 (ADC_CR2_CHEN_15)
217 #define ADC_CONTINUE_CHANNEL_ALL (0x0FF000FF)
218
219 #define IS_ADC_CONTINUE_CHANNEL(CHANNEL) (((CHANNEL) & ADC_CONTINUE_CHANNEL_ALL) != 0x0000)
220 #define IS_ADC_CHANNEL(CHANNEL) ((IS_ADC_SINGLE_CHANNEL(CHANNEL)) || (IS_ADC_CONTINUE_CHANNEL(CHANNEL)))
221
228 #define ADC_IT_CONTINUE ADC_INTEN_CONT_IEN
229 #define ADC_IT_RANGE_THRESHOLD ADC_INTEN_REG_IEN
230 #define ADC_IT_HIGH_THRESHOLD ADC_INTEN_HHT_IEN
231 #define ADC_IT_LOW_THRESHOLD ADC_INTEN_LLT_IEN
233 #define ADC_IT_CHANNEL15 ADC_INTEN_ADCXIEN_15
234 #define ADC_IT_CHANNEL14 ADC_INTEN_ADCXIEN_14
235 #define ADC_IT_CHANNEL13 ADC_INTEN_ADCXIEN_13
236 #define ADC_IT_CHANNEL12 ADC_INTEN_ADCXIEN_12
237 #define ADC_IT_CHANNEL11 ADC_INTEN_ADCXIEN_11
238 #define ADC_IT_CHANNEL10 ADC_INTEN_ADCXIEN_10
239 #define ADC_IT_CHANNEL9 ADC_INTEN_ADCXIEN_9
240 #define ADC_IT_CHANNEL8 ADC_INTEN_ADCXIEN_8
242 #define ADC_IT_CHANNEL7 ADC_INTEN_ADCXIEN_7
243 #define ADC_IT_CHANNEL6 ADC_INTEN_ADCXIEN_6
244 #define ADC_IT_CHANNEL5 ADC_INTEN_ADCXIEN_5
245 #define ADC_IT_CHANNEL4 ADC_INTEN_ADCXIEN_4
246 #define ADC_IT_CHANNEL3 ADC_INTEN_ADCXIEN_3
247 #define ADC_IT_CHANNEL2 ADC_INTEN_ADCXIEN_2
248 #define ADC_IT_CHANNEL1 ADC_INTEN_ADCXIEN_1
249 #define ADC_IT_CHANNEL0 ADC_INTEN_ADCXIEN_0
250 #define ADC_IT_MASK (0xFFFFFUL)
252 #define IS_ADC_IT(ADC_IT) (((ADC_IT) & ADC_IT_MASK) != 0x00000)
253
260 #define ADC_RAWINTFLAG ADC_RAWINTSR_CONT_INTF
261 #define ADC_RAWINTFLAG_RANGE_THRESHOLD ADC_RAWINTSR_REG_INTF
262 #define ADC_RAWINTFLAG_HIGH_THRESHOLD ADC_RAWINTSR_HHT_INTF
263 #define ADC_RAWINTFLAG_LOW_THERSHOLD ADC_RAWINTSR_LLT_INTF
265 #define ADC_RAWINTFLAG_CHANNEL15 ADC_RAWINTSR_ADCRIS_15
266 #define ADC_RAWINTFLAG_CHANNEL14 ADC_RAWINTSR_ADCRIS_14
267 #define ADC_RAWINTFLAG_CHANNEL13 ADC_RAWINTSR_ADCRIS_13
268 #define ADC_RAWINTFLAG_CHANNEL12 ADC_RAWINTSR_ADCRIS_12
269 #define ADC_RAWINTFLAG_CHANNEL11 ADC_RAWINTSR_ADCRIS_11
270 #define ADC_RAWINTFLAG_CHANNEL10 ADC_RAWINTSR_ADCRIS_10
271 #define ADC_RAWINTFLAG_CHANNEL9 ADC_RAWINTSR_ADCRIS_9
272 #define ADC_RAWINTFLAG_CHANNEL8 ADC_RAWINTSR_ADCRIS_8
274 #define ADC_RAWINTFLAG_CHANNEL7 ADC_RAWINTSR_ADCRIS_7
275 #define ADC_RAWINTFLAG_CHANNEL6 ADC_RAWINTSR_ADCRIS_6
276 #define ADC_RAWINTFLAG_CHANNEL5 ADC_RAWINTSR_ADCRIS_5
277 #define ADC_RAWINTFLAG_CHANNEL4 ADC_RAWINTSR_ADCRIS_4
278 #define ADC_RAWINTFLAG_CHANNEL3 ADC_RAWINTSR_ADCRIS_3
279 #define ADC_RAWINTFLAG_CHANNEL2 ADC_RAWINTSR_ADCRIS_2
280 #define ADC_RAWINTFLAG_CHANNEL1 ADC_RAWINTSR_ADCRIS_1
281 #define ADC_RAWINTFLAG_CHANNEL0 ADC_RAWINTSR_ADCRIS_0
283 #define ADC_RAWINTFLAG_CHANNEL_ALL (ADC_RAWINTFLAG_CHANNEL0 | ADC_RAWINTFLAG_CHANNEL1 | ADC_RAWINTFLAG_CHANNEL2 | ADC_RAWINTFLAG_CHANNEL3 | \
284 ADC_RAWINTFLAG_CHANNEL4 | ADC_RAWINTFLAG_CHANNEL5 | ADC_RAWINTFLAG_CHANNEL6 | ADC_RAWINTFLAG_CHANNEL7 | \
285 ADC_RAWINTFLAG_CHANNEL8 | ADC_RAWINTFLAG_CHANNEL9 | ADC_RAWINTFLAG_CHANNEL10 | ADC_RAWINTFLAG_CHANNEL11 | \
286 ADC_RAWINTFLAG_CHANNEL12 | ADC_RAWINTFLAG_CHANNEL13 | ADC_RAWINTFLAG_CHANNEL14 | ADC_RAWINTFLAG_CHANNEL15)
287 #define IS_ADC_RAWINTFLAG(FLAG) (((FLAG) & ADC_RAWINTFLAG_LOW_THERSHOLD) | \
288 ((FLAG) & ADC_RAWINTFLAG_LOW_THERSHOLD) | \
289 ((FLAG) & ADC_RAWINTFLAG_LOW_THERSHOLD) | \
290 ((FLAG) & ADC_RAWINTFLAG_LOW_THERSHOLD) | \
291 ((FLAG) & ADC_RAWINTFLAG_CHANNEL_ALL))
292
299 #define ADC_INTFLAG ADC_MSKINTSR_CONT_MIF
300 #define ADC_INTFLAG_RANGE_THRESHOLD ADC_MSKINTSR_REG_MIF
301 #define ADC_INTFLAG_HIGH_THRESHOLD ADC_MSKINTSR_HHT_MIF
302 #define ADC_INTFLAG_LOW_THERSHOLD ADC_MSKINTSR_LLT_MIF
304 #define ADC_INTFLAG_CHANNEL15 ADC_MSKINTSR_ADCMIS_15
305 #define ADC_INTFLAG_CHANNEL14 ADC_MSKINTSR_ADCMIS_14
306 #define ADC_INTFLAG_CHANNEL13 ADC_MSKINTSR_ADCMIS_13
307 #define ADC_INTFLAG_CHANNEL12 ADC_MSKINTSR_ADCMIS_12
308 #define ADC_INTFLAG_CHANNEL11 ADC_MSKINTSR_ADCMIS_11
309 #define ADC_INTFLAG_CHANNEL10 ADC_MSKINTSR_ADCMIS_10
310 #define ADC_INTFLAG_CHANNEL9 ADC_MSKINTSR_ADCMIS_9
311 #define ADC_INTFLAG_CHANNEL8 ADC_MSKINTSR_ADCMIS_8
313 #define ADC_INTFLAG_CHANNEL7 ADC_MSKINTSR_ADCMIS_7
314 #define ADC_INTFLAG_CHANNEL6 ADC_MSKINTSR_ADCMIS_6
315 #define ADC_INTFLAG_CHANNEL5 ADC_MSKINTSR_ADCMIS_5
316 #define ADC_INTFLAG_CHANNEL4 ADC_MSKINTSR_ADCMIS_4
317 #define ADC_INTFLAG_CHANNEL3 ADC_MSKINTSR_ADCMIS_3
318 #define ADC_INTFLAG_CHANNEL2 ADC_MSKINTSR_ADCMIS_2
319 #define ADC_INTFLAG_CHANNEL1 ADC_MSKINTSR_ADCMIS_1
320 #define ADC_INTFLAG_CHANNEL0 ADC_MSKINTSR_ADCMIS_0
322 #define ADC_INTFLAG_CHANNEL_ALL (ADC_INTFLAG_CHANNEL0 | ADC_INTFLAG_CHANNEL1 | ADC_INTFLAG_CHANNEL2 | ADC_INTFLAG_CHANNEL3 | \
323 ADC_INTFLAG_CHANNEL4 | ADC_INTFLAG_CHANNEL5 | ADC_INTFLAG_CHANNEL6 | ADC_INTFLAG_CHANNEL7 | \
324 ADC_INTFLAG_CHANNEL8 | ADC_INTFLAG_CHANNEL9 | ADC_INTFLAG_CHANNEL10 | ADC_INTFLAG_CHANNEL11 | \
325 ADC_INTFLAG_CHANNEL12 | ADC_INTFLAG_CHANNEL13 | ADC_INTFLAG_CHANNEL14 | ADC_INTFLAG_CHANNEL15)
326 #define IS_ADC_INTFLAG(FLAG) (((FLAG) & ADC_INTFLAG_LOW_THERSHOLD) | \
327 ((FLAG) & ADC_INTFLAG_LOW_THERSHOLD) | \
328 ((FLAG) & ADC_INTFLAG_LOW_THERSHOLD) | \
329 ((FLAG) & ADC_INTFLAG_LOW_THERSHOLD) | \
330 ((FLAG) & ADC_INTFLAG_CHANNEL_ALL))
331
338 #define ADC_SOFTWARE_START (0x00000000U)
339 #define ADC_EXTTRIG1_TIM10 (ADC_CR1_TRIGS0_0)
340 #define ADC_EXTTRIG1_TIM11 (ADC_CR1_TRIGS0_1)
341 #define ADC_EXTTRIG1_TIM1 (ADC_CR1_TRIGS0_1 | ADC_CR1_TRIGS0_0)
342 #define ADC_EXTTRIG1_LPTIM (ADC_CR1_TRIGS0_2)
343 #define ADC_EXTTRIG1_TIM1_TRGO (ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_0)
344 #define ADC_EXTTRIG1_TIM2_TRGO (ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_1)
345 #define ADC_EXTTRIG1_TIM2_INT (ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_1 | ADC_CR1_TRIGS0_0)
346 #define ADC_EXTTRIG1_UART1_INT (ADC_CR1_TRIGS0_3)
347 #define ADC_EXTTRIG1_UART2_INT (ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_0)
348 #define ADC_EXTTRIG1_LPUART_INT (ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_1)
349 #define ADC_EXTTRIG1_VC0_INT (ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_1 | ADC_CR1_TRIGS0_0)
350 #define ADC_EXTTRIG1_NC (ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_2)
351 #define ADC_EXTTRIG1_RTC_INT (ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_0)
352 #define ADC_EXTTRIG1_PCA_INT (ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_1)
353 #define ADC_EXTTRIG1_SPI_INT (ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_1 | ADC_CR1_TRIGS0_0)
354 #define ADC_EXTTRIG1_PA1_INT (ADC_CR1_TRIGS0_4)
355 #define ADC_EXTTRIG1_PA2_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_0)
356 #define ADC_EXTTRIG1_PA3_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_1)
357 #define ADC_EXTTRIG1_PB4_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_1 | ADC_CR1_TRIGS0_0)
358 #define ADC_EXTTRIG1_PB5_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_2)
359 #define ADC_EXTTRIG1_PC3_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_0)
360 #define ADC_EXTTRIG1_PC4_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_0)
361 #define ADC_EXTTRIG1_PC5_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_1)
362 #define ADC_EXTTRIG1_PC6_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_3)
363 #define ADC_EXTTRIG1_PC7_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_0)
364 #define ADC_EXTTRIG1_PD1_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_1)
365 #define ADC_EXTTRIG1_PD2_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_1 | ADC_CR1_TRIGS0_0)
366 #define ADC_EXTTRIG1_PD3_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_2)
367 #define ADC_EXTTRIG1_PD4_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_0)
368 #define ADC_EXTTRIG1_PD5_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_1)
369 #define ADC_EXTTRIG1_PD6_INT (ADC_CR1_TRIGS0_4 | ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_1 | ADC_CR1_TRIGS0_0)
370
371 #define ADC_EXTTRIG1_PA4_INT (ADC_CR1_TRIGS0_5 | ADC_CR1_TRIGS0_0)
372 #define ADC_EXTTRIG1_PB0_INT (ADC_CR1_TRIGS0_5 | ADC_CR1_TRIGS0_1)
373 #define ADC_EXTTRIG1_PB1_INT (ADC_CR1_TRIGS0_5 | ADC_CR1_TRIGS0_1 | ADC_CR1_TRIGS0_0)
374 #define ADC_EXTTRIG1_PB2_INT (ADC_CR1_TRIGS0_5 | ADC_CR1_TRIGS0_2)
375 #define ADC_EXTTRIG1_PB3_INT (ADC_CR1_TRIGS0_5 | ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_0)
376 #define ADC_EXTTRIG1_PB6_INT (ADC_CR1_TRIGS0_5 | ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_1)
377 #define ADC_EXTTRIG1_PB7_INT (ADC_CR1_TRIGS0_5 | ADC_CR1_TRIGS0_2 | ADC_CR1_TRIGS0_1 | ADC_CR1_TRIGS0_0)
378 #define ADC_EXTTRIG1_PC0_INT (ADC_CR1_TRIGS0_5 | ADC_CR1_TRIGS0_3)
379 #define ADC_EXTTRIG1_PC1_INT (ADC_CR1_TRIGS0_5 | ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_0)
380 #define ADC_EXTTRIG1_PC2_INT (ADC_CR1_TRIGS0_5 | ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_1)
381 #define ADC_EXTTRIG1_PD0_INT (ADC_CR1_TRIGS0_5 | ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_1 | ADC_CR1_TRIGS0_0)
382 #define ADC_EXTTRIG1_PD7_INT (ADC_CR1_TRIGS0_5 | ADC_CR1_TRIGS0_3 | ADC_CR1_TRIGS0_2)
383 #define ADC_EXTTRIG1_MASK (0x1F | 0x10000)
384
385 #define IS_ADC_EXTRIG1(EXTRIG) ((((EXTRIG) & ADC_EXTTRIG1_MASK) != 0x0000) || ((EXTRIG) == ADC_SOFTWARE_START))
386
393 #define ADC_EXTTRIG2_TIM10 (ADC_CR1_TRIGS1_0)
394 #define ADC_EXTTRIG2_TIM11 (ADC_CR1_TRIGS1_1)
395 #define ADC_EXTTRIG2_TIM1 (ADC_CR1_TRIGS1_1 | ADC_CR1_TRIGS1_0)
396 #define ADC_EXTTRIG2_LPTIM (ADC_CR1_TRIGS1_2 |)
397 #define ADC_EXTTRIG2_TIM1_TRGO (ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_0)
398 #define ADC_EXTTRIG2_TIM2_TRGO (ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_1)
399 #define ADC_EXTTRIG2_TIM2_INT (ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_1 | ADC_CR1_TRIGS1_0)
400 #define ADC_EXTTRIG2_UART0_INT (ADC_CR1_TRIGS1_3)
401 #define ADC_EXTTRIG2_UART1_INT (ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_0)
402 #define ADC_EXTTRIG2_LPUART_INT (ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_1)
403 #define ADC_EXTTRIG2_VC0_INT (ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_1 | ADC_CR1_TRIGS1_0)
404 #define ADC_EXTTRIG2_NC (ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_2)
405 #define ADC_EXTTRIG2_RTC_INT (ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_0)
406 #define ADC_EXTTRIG2_PCA_INT (ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_1)
407 #define ADC_EXTTRIG2_SPI_INT (ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_1 | ADC_CR1_TRIGS1_0)
408 #define ADC_EXTTRIG2_PA1_INT (ADC_CR1_TRIGS1_4)
409 #define ADC_EXTTRIG2_PA2_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_0)
410 #define ADC_EXTTRIG2_PA3_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_1)
411 #define ADC_EXTTRIG2_PB4_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_1 | ADC_CR1_TRIGS1_0)
412 #define ADC_EXTTRIG2_PB5_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_2)
413 #define ADC_EXTTRIG2_PC3_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_0)
414 #define ADC_EXTTRIG2_PC4_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_0)
415 #define ADC_EXTTRIG2_PC5_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_1)
416 #define ADC_EXTTRIG2_PC6_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_3)
417 #define ADC_EXTTRIG2_PC7_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_0)
418 #define ADC_EXTTRIG2_PD1_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_1)
419 #define ADC_EXTTRIG2_PD2_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_1 | ADC_CR1_TRIGS1_0)
420 #define ADC_EXTTRIG2_PD3_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_2)
421 #define ADC_EXTTRIG2_PD4_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_0)
422 #define ADC_EXTTRIG2_PD5_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_1)
423 #define ADC_EXTTRIG2_PD6_INT (ADC_CR1_TRIGS1_4 | ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_1 | ADC_CR1_TRIGS1_0)
424
425 #define ADC_EXTTRIG2_PA4_INT (ADC_CR1_TRIGS1_5 | ADC_CR1_TRIGS1_0)
426 #define ADC_EXTTRIG2_PB0_INT (ADC_CR1_TRIGS1_5 | ADC_CR1_TRIGS1_1)
427 #define ADC_EXTTRIG2_PB1_INT (ADC_CR1_TRIGS1_5 | ADC_CR1_TRIGS1_1 | ADC_CR1_TRIGS1_0)
428 #define ADC_EXTTRIG2_PB2_INT (ADC_CR1_TRIGS1_5 | ADC_CR1_TRIGS1_2)
429 #define ADC_EXTTRIG2_PB3_INT (ADC_CR1_TRIGS1_5 | ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_0)
430 #define ADC_EXTTRIG2_PB6_INT (ADC_CR1_TRIGS1_5 | ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_1)
431 #define ADC_EXTTRIG2_PB7_INT (ADC_CR1_TRIGS1_5 | ADC_CR1_TRIGS1_2 | ADC_CR1_TRIGS1_1 | ADC_CR1_TRIGS1_0)
432 #define ADC_EXTTRIG2_PC0_INT (ADC_CR1_TRIGS1_5 | ADC_CR1_TRIGS1_3)
433 #define ADC_EXTTRIG2_PC1_INT (ADC_CR1_TRIGS1_5 | ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_0)
434 #define ADC_EXTTRIG2_PC2_INT (ADC_CR1_TRIGS1_5 | ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_1)
435 #define ADC_EXTTRIG2_PD0_INT (ADC_CR1_TRIGS1_5 | ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_1 | ADC_CR1_TRIGS1_0)
436 #define ADC_EXTTRIG2_PD7_INT (ADC_CR1_TRIGS1_5 | ADC_CR1_TRIGS1_3 | ADC_CR1_TRIGS1_2)
437 #define ADC_EXTTRIG2_MASK (0x3E0 | 0x20000)
438
439 #define IS_ADC_EXTRIG2(EXTRIG) ((((EXTRIG) & ADC_EXTTRIG2_MASK) != 0x0000) || ((EXTRIG) == ADC_SOFTWARE_START))
440
448 /* Exported macro ------------------------------------------------------------*/
449 /* Exported functions --------------------------------------------------------*/
450
451 void ADC_DeInit(void);
452 void ADC_Init(ADC_InitTypeDef *ADC_InitStruct);
453 void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct);
454 void ADC_Cmd(FunctionalState NewState);
455 void ADC_ITConfig(uint32_t ADC_IT, FunctionalState NewState);
456 void ADC_SoftwareStartConvCmd(FunctionalState NewState);
457 FlagStatus ADC_GetSoftwareStartConvStatus(void);
458 uint16_t ADC_GetConversionValue(uint32_t Chnannel);
459 uint32_t ADC_GetAccValue(void);
460 FlagStatus ADC_GetFlagStatus(uint16_t ADC_FLAG);
461 FlagStatus ADC_GetRawFlagStatus(uint16_t ADC_FLAG);
462 ITStatus ADC_GetITStatus(uint16_t ADC_IT);
463 void ADC_ClearFlag(uint16_t ADC_FLAG);
464 void ADC_ClearITPendingBit(uint16_t ADC_IT);
465 void ADC_ThresholdsConfig(uint16_t LowThreshold, uint16_t HighThreshold);
466 void ADC_ThresholdsCompareCmd(uint16_t Threshold_Config, FunctionalState NewState);
467
476 #ifdef __cplusplus
477 }
478 #endif
479
480 #endif /*__MG32L003_ADC_H */
ADC_ThresholdsConfig
void ADC_ThresholdsConfig(uint16_t LowThreshold, uint16_t HighThreshold)
Configures the high and low thresholds of the analog watchdog.
Definition: mg32l003_adc.c:611
ADC_Init
void ADC_Init(ADC_InitTypeDef *ADC_InitStruct)
Initializes the ADC peripheral according to the specified parameters in the ADC_InitStruct.
Definition: mg32l003_adc.c:64
ADC_GetConversionValue
uint16_t ADC_GetConversionValue(uint32_t Chnannel)
Returns the last ADC conversion result data for regular channel.
Definition: mg32l003_adc.c:300
ADC_GetRawFlagStatus
FlagStatus ADC_GetRawFlagStatus(uint16_t ADC_FLAG)
Checks whether the specified ADC flag is set or not.
Definition: mg32l003_adc.c:582
ADC_ThresholdsCompareCmd
void ADC_ThresholdsCompareCmd(uint16_t Threshold_Config, FunctionalState NewState)
Enables or disables the thresholds to compare with the function of analog watchdog.
Definition: mg32l003_adc.c:630
ADC_InitTypeDef::ADC_SingleContinueMode
uint32_t ADC_SingleContinueMode
Definition: mg32l003_adc.h:45
ADC_InitTypeDef::ADC_AutoAccumulation
uint32_t ADC_AutoAccumulation
Definition: mg32l003_adc.h:48
ADC_ITConfig
void ADC_ITConfig(uint32_t ADC_IT, FunctionalState NewState)
Enables or disables the specified ADC interrupts.
Definition: mg32l003_adc.c:198
ADC_ClearITPendingBit
void ADC_ClearITPendingBit(uint16_t ADC_IT)
Clears the ADC pending interrupt bits.
Definition: mg32l003_adc.c:512
ADC_DeInit
void ADC_DeInit(void)
Deinitializes the ADC peripheral registers to their default reset values.
Definition: mg32l003_adc.c:51
ADC_InitTypeDef
ADC Init structure definition
Definition: mg32l003_adc.h:34
ADC_InitTypeDef::ADC_SamplingTime
uint32_t ADC_SamplingTime
Definition: mg32l003_adc.h:36
ADC_InitTypeDef::ADC_SingleChannelSel
uint32_t ADC_SingleChannelSel
Definition: mg32l003_adc.h:39
ADC_GetITStatus
ITStatus ADC_GetITStatus(uint16_t ADC_IT)
Checks whether the specified ADC interrupt is set or not.
Definition: mg32l003_adc.c:414
ADC_SoftwareStartConvCmd
void ADC_SoftwareStartConvCmd(FunctionalState NewState)
Enables or disables the selected ADC software start conversion.
Definition: mg32l003_adc.c:222
ADC_ClearFlag
void ADC_ClearFlag(uint16_t ADC_FLAG)
Clears the ADC pending interrupt flags.
Definition: mg32l003_adc.c:547
ADC_InitTypeDef::ADC_ContinueChannelSel
uint32_t ADC_ContinueChannelSel
Definition: mg32l003_adc.h:57
ADC_GetAccValue
uint32_t ADC_GetAccValue(void)
Gets ADC accumulation conversion result.
Definition: mg32l003_adc.c:379
ADC_InitTypeDef::ADC_ClkSel
uint32_t ADC_ClkSel
Definition: mg32l003_adc.h:42
ADC_InitTypeDef::ADC_ConversionTimes
uint32_t ADC_ConversionTimes
Definition: mg32l003_adc.h:54
ADC_InitTypeDef::ADC_ExternalTrigConv1
uint32_t ADC_ExternalTrigConv1
Definition: mg32l003_adc.h:60
ADC_StructInit
void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct)
Fills each ADC_InitStruct member with its default value.
Definition: mg32l003_adc.c:126
ADC_InitTypeDef::ADC_CircleMode
uint32_t ADC_CircleMode
Definition: mg32l003_adc.h:51
ADC_GetFlagStatus
FlagStatus ADC_GetFlagStatus(uint16_t ADC_FLAG)
Checks whether the specified ADC flag is set or not.
Definition: mg32l003_adc.c:465
ADC_Cmd
void ADC_Cmd(FunctionalState NewState)
Enables or disables the ADC peripheral.
Definition: mg32l003_adc.c:154
ADC_InitTypeDef::ADC_ExternalTrigConv2
uint32_t ADC_ExternalTrigConv2
Definition: mg32l003_adc.h:65
ADC_GetSoftwareStartConvStatus
FlagStatus ADC_GetSoftwareStartConvStatus(void)
Gets the selected ADC Software start conversion Status.
Definition: mg32l003_adc.c:244