MG32L003 Standard Peripherals Firmware Library

结构体 | 宏定义
Status and Control Registers
Defines and Type Definitions

Core Register type definitions. 更多...

## 结构体
union | APSR_Type
| Union type to access the Application Program Status Register (APSR). 更多...
union | IPSR_Type
| Union type to access the Interrupt Program Status Register (IPSR). 更多...
union | xPSR_Type
| Union type to access the Special-Purpose Program Status Registers (xPSR). 更多...
union | CONTROL_Type
| Union type to access the Control Registers (CONTROL). 更多...

## 宏定义
#define | APSR_N_Pos 31U
#define | APSR_N_Msk (1UL << APSR_N_Pos)
#define | APSR_Z_Pos 30U
#define | APSR_Z_Msk (1UL << APSR_Z_Pos)
#define | APSR_C_Pos 29U
#define | APSR_C_Msk (1UL << APSR_C_Pos)
#define | APSR_V_Pos 28U
#define | APSR_V_Msk (1UL << APSR_V_Pos)
#define | IPSR_ISR_Pos 0U
#define | IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
#define | xPSR_N_Pos 31U
#define | xPSR_N_Msk (1UL << xPSR_N_Pos)
#define | xPSR_Z_Pos 30U
#define | xPSR_Z_Msk (1UL << xPSR_Z_Pos)
#define | xPSR_C_Pos 29U
#define | xPSR_C_Msk (1UL << xPSR_C_Pos)
#define | xPSR_V_Pos 28U
#define | xPSR_V_Msk (1UL << xPSR_V_Pos)
#define | xPSR_T_Pos 24U
#define | xPSR_T_Msk (1UL << xPSR_T_Pos)
#define | xPSR_ISR_Pos 0U
#define | xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
#define | CONTROL_SPSEL_Pos 1U
#define | CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
#define | CONTROL_nPRIV_Pos 0U
#define | CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)

## 详细描述

Core Register type definitions.

## 宏定义说明

## ◆ APSR_C_Msk

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

## ◆ APSR_C_Pos

#define APSR_C_Pos 29U

APSR: C Position

## ◆ APSR_N_Msk

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

## ◆ APSR_N_Pos

#define APSR_N_Pos 31U

APSR: N Position

## ◆ APSR_V_Msk

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

## ◆ APSR_V_Pos

#define APSR_V_Pos 28U

APSR: V Position

## ◆ APSR_Z_Msk

#define APSR_Z_Msk (1UL << APSR_Z_Pos)

APSR: Z Mask

## ◆ APSR_Z_Pos

#define APSR_Z_Pos 30U

APSR: Z Position

## ◆ CONTROL_nPRIV_Msk

#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)

CONTROL: nPRIV Mask

## ◆ CONTROL_nPRIV_Pos

#define CONTROL_nPRIV_Pos 0U

CONTROL: nPRIV Position

## ◆ CONTROL_SPSEL_Msk

#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

## ◆ CONTROL_SPSEL_Pos

#define CONTROL_SPSEL_Pos 1U

CONTROL: SPSEL Position

## ◆ IPSR_ISR_Msk

#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

## ◆ IPSR_ISR_Pos

#define IPSR_ISR_Pos 0U

IPSR: ISR Position

## ◆ xPSR_C_Msk

#define xPSR_C_Msk (1UL << xPSR_C_Pos)

xPSR: C Mask

## ◆ xPSR_C_Pos

#define xPSR_C_Pos 29U

xPSR: C Position

## ◆ xPSR_ISR_Msk

#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)

xPSR: ISR Mask

## ◆ xPSR_ISR_Pos

#define xPSR_ISR_Pos 0U

xPSR: ISR Position

## ◆ xPSR_N_Msk

#define xPSR_N_Msk (1UL << xPSR_N_Pos)

xPSR: N Mask

## ◆ xPSR_N_Pos

#define xPSR_N_Pos 31U

xPSR: N Position

## ◆ xPSR_T_Msk

#define xPSR_T_Msk (1UL << xPSR_T_Pos)

xPSR: T Mask

## ◆ xPSR_T_Pos

#define xPSR_T_Pos 24U

xPSR: T Position

## ◆ xPSR_V_Msk

#define xPSR_V_Msk (1UL << xPSR_V_Pos)

xPSR: V Mask

## ◆ xPSR_V_Pos

#define xPSR_V_Pos 28U

xPSR: V Position

## ◆ xPSR_Z_Msk

#define xPSR_Z_Msk (1UL << xPSR_Z_Pos)

xPSR: Z Mask

## ◆ xPSR_Z_Pos

#define xPSR_Z_Pos 30U

xPSR: Z Position