MG32L003 Standard Peripherals Firmware Library

mg32l003_rcc.h
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1
10 /* Define to prevent recursive inclusion -------------------------------------*/
11 #ifndef __MG32L003_RCC_H
12 #define __MG32L003_RCC_H
13
14 #ifdef __cplusplus
15 extern "C" {
16 #endif
17
18 /* Includes ------------------------------------------------------------------*/
19 #include "mg32l003.h"
20
29 /* Exported types ------------------------------------------------------------*/
30 typedef struct
31 {
32 uint32_t SYSCLK_Frequency;
33 uint32_t AHBCLK_Frequency;
34 uint32_t APBCLK_Frequency;
35 } RCC_ClocksTypeDef;
36
37 /* Exported constants --------------------------------------------------------*/
38
46 #define HSI_VALUE_24M ((uint32_t)24000000)
47 #define HSI_VALUE_22M ((uint32_t)22120000)
48 #define HSI_VALUE_16M ((uint32_t)16000000)
49 #define HSI_VALUE_8M ((uint32_t)8000000)
50 #define HSI_VALUE_4M ((uint32_t)4000000)
59 #define LSI_VALUE_38K ((uint32_t)38400)
60 #define LSI_VALUE_32K ((uint32_t)32768)
69 #define RCC_LSI_STARTUP_4CYCLE ((uint32_t)(0x00U << RCC_LSICR_LSISTARTUP_Pos))
70 #define RCC_LSI_STARTUP_16CYCLE ((uint32_t)(0x01U << RCC_LSICR_LSISTARTUP_Pos))
71 #define RCC_LSI_STARTUP_64CYCLE ((uint32_t)(0x02U << RCC_LSICR_LSISTARTUP_Pos))
72 #define RCC_LSI_STARTUP_256CYCLE ((uint32_t)(0x03U << RCC_LSICR_LSISTARTUP_Pos))
80 #define RCC_HSE_OFF ((uint32_t)0x00)
81 #define RCC_HSE_ON ((uint32_t)0x01)
82 #define RCC_HSE_BYPASS ((uint32_t)0x02)
83 #define RCC_HSE_DEFAULT ((uint32_t)0x03)
84
92 #define RCC_LSE_OFF ((uint32_t)0x00)
93 #define RCC_LSE_ON ((uint32_t)0x01)
94 #define RCC_LSE_BYPASS ((uint32_t)0x02)
95 #define RCC_LSE_DEFAULT ((uint32_t)0x03)
96
104 #define RCC_SYSCLKSource_HSI ((uint32_t)(0x01U << RCC_SYSCLKSEL_CLKSW_Pos))
105 #define RCC_SYSCLKSource_HSE ((uint32_t)(0x02U << RCC_SYSCLKSEL_CLKSW_Pos))
106 #define RCC_SYSCLKSource_LSI ((uint32_t)(0x04U << RCC_SYSCLKSEL_CLKSW_Pos))
107 #define RCC_SYSCLKSource_LSE ((uint32_t)(0x08U << RCC_SYSCLKSEL_CLKSW_Pos))
108
116 #define RCC_AHBCLKDiv1 ((uint32_t)0x00)
117 #define RCC_AHBCLKDiv2 ((uint32_t)0x01)
118
126 #define RCC_APBCLKDiv1 ((uint32_t)0x00)
127 #define RCC_APBCLKDiv2 ((uint32_t)0x01)
128
136 #define RCC_MCOSOURCE_HSI ((uint32_t)(0x00U << RCC_MCOCR_MCOSEL_Pos))
137 #define RCC_MCOSOURCE_HSE ((uint32_t)(0x01U << RCC_MCOCR_MCOSEL_Pos))
138 #define RCC_MCOSOURCE_LSI ((uint32_t)(0x02U << RCC_MCOCR_MCOSEL_Pos))
139 #define RCC_MCOSOURCE_LSE ((uint32_t)(0x03U << RCC_MCOCR_MCOSEL_Pos))
140 #define RCC_MCOSOURCE_SYSCLK ((uint32_t)(0x04U << RCC_MCOCR_MCOSEL_Pos))
141 #define RCC_MCOSOURCE_HCLK ((uint32_t)(0x05U << RCC_MCOCR_MCOSEL_Pos))
142
150 #define RCC_MCOHCLkDiv1 ((uint32_t)0x00)
151 #define RCC_MCOHCLkDiv2 ((uint32_t)0x01)
152
160 #define RCC_AHBPeriph_GPIOA ((uint32_t)(0x01U << 0))
161 #define RCC_AHBPeriph_GPIOB ((uint32_t)(0x01U << 1))
162 #define RCC_AHBPeriph_GPIOC ((uint32_t)(0x01U << 2))
163 #define RCC_AHBPeriph_GPIOD ((uint32_t)(0x01U << 3))
164 #define RCC_AHBPeriph_CRC ((uint32_t)(0x01U << 4))
165 #define RCC_AHBPeriph_FLASH ((uint32_t)(0x01U << 8))
166 #define RCC_AHBPeriph_ALL ((uint32_t)0x0000011F)
167
175 #define RCC_APBPeriph_UART1 ((uint32_t)(0x01U << 0))
176 #define RCC_APBPeriph_UART2 ((uint32_t)(0x01U << 1))
177 #define RCC_APBPeriph_I2C ((uint32_t)(0x01U << 2))
178 #define RCC_APBPeriph_LPUART ((uint32_t)(0x01U << 3))
179 #define RCC_APBPeriph_SPI ((uint32_t)(0x01U << 4))
180 #define RCC_APBPeriph_LPTIM ((uint32_t)(0x01U << 5))
181 #define RCC_APBPeriph_BASETIM ((uint32_t)(0x01U << 6))
182 #define RCC_APBPeriph_SYSCON ((uint32_t)(0x01U << 7))
183 #define RCC_APBPeriph_PCA ((uint32_t)(0x01U << 8))
184 #define RCC_APBPeriph_OWIRE ((uint32_t)(0x01U << 9))
185 #define RCC_APBPeriph_TIM1 ((uint32_t)(0x01U << 10))
186 #define RCC_APBPeriph_TIM2 ((uint32_t)(0x01U << 11))
187 #define RCC_APBPeriph_WWDG ((uint32_t)(0x01U << 12))
188 #define RCC_APBPeriph_ADC ((uint32_t)(0x01U << 13))
189 #define RCC_APBPeriph_AWK ((uint32_t)(0x01U << 14))
190 #define RCC_APBPeriph_RTC ((uint32_t)(0x01U << 15))
191 #define RCC_APBPeriph_CLKTRIM ((uint32_t)(0x01U << 16))
192 #define RCC_APBPeriph_IWDG ((uint32_t)(0x01U << 17))
193 #define RCC_APBPeriph_LVDVC ((uint32_t)(0x01U << 18))
194 #define RCC_APBPeriph_BEEP ((uint32_t)(0x01U << 19))
195 #define RCC_APBPeriph_DBG ((uint32_t)(0x01U << 20))
196 #define RCC_APBPeriph_ALL ((uint32_t)0x001FFFFF)
197
205 #define RCC_RSTFLAG_MCURST ((uint32_t)(0x01U << 0))
206 #define RCC_RSTFLAG_CPURST ((uint32_t)(0x01U << 1))
207 #define RCC_RSTFLAG_WWDGRST ((uint32_t)(0x01U << 2))
208 #define RCC_RSTFLAG_IWDGRST ((uint32_t)(0x01U << 3))
209 #define RCC_RSTFLAG_LVDRST ((uint32_t)(0x01U << 4))
210 #define RCC_RSTFLAG_PORRST ((uint32_t)(0x01U << 5))
211 #define RCC_RSTFLAG_LOCKUPRST ((uint32_t)(0x01U << 6))
212 #define RCC_RSTFLAG_PADRST ((uint32_t)(0x01U << 7))
213 #define RCC_RSTFLAG_SFTRST ((uint32_t)(0x01U << 8))
214
222 #define HSI24M_TRIM_ADDR ((uint32_t)0x180000A0)
223 #define HSI22M_TRIM_ADDR ((uint32_t)0x180000A2)
224 #define HSI16M_TRIM_ADDR ((uint32_t)0x180000A4)
225 #define HSI8M_TRIM_ADDR ((uint32_t)0x180000A6)
226 #define HSI4M_TRIM_ADDR ((uint32_t)0x180000A8)
227
228 #define HSI24M_TC_ADDR ((uint32_t)0x18000090)
229 #define HSI22M_TC_ADDR ((uint32_t)0x18000092)
230 #define HSI16M_TC_ADDR ((uint32_t)0x18000094)
231 #define HSI8M_TC_ADDR ((uint32_t)0x18000096)
232 #define HSI4M_TC_ADDR ((uint32_t)0x18000098)
233
234 #define RCC_HSITRIM_24M (*(uint16_t *)(HSI24M_TRIM_ADDR))
235 #define RCC_HSITRIM_22M (*(uint16_t *)(HSI22M_TRIM_ADDR))
236 #define RCC_HSITRIM_16M (*(uint16_t *)(HSI16M_TRIM_ADDR))
237 #define RCC_HSITRIM_8M (*(uint16_t *)(HSI8M_TRIM_ADDR))
238 #define RCC_HSITRIM_4M (*(uint16_t *)(HSI4M_TRIM_ADDR))
239
240 #define RCC_HSITC_24M (*(uint16_t *)(HSI24M_TC_ADDR))
241 #define RCC_HSITC_22M (*(uint16_t *)(HSI22M_TC_ADDR))
242 #define RCC_HSITC_16M (*(uint16_t *)(HSI16M_TC_ADDR))
243 #define RCC_HSITC_8M (*(uint16_t *)(HSI8M_TC_ADDR))
244 #define RCC_HSITC_4M (*(uint16_t *)(HSI4M_TC_ADDR))
245
246 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x00000312)
247
255 #define LSI38K_TRIM_ADDR ((uint32_t)0x180000B4)
256 #define LSI32K_TRIM_ADDR ((uint32_t)0x180000B0)
257
258 #define LSI38K_TC_ADDR ((uint32_t)0x180000BC)
259 #define LSI32K_TC_ADDR ((uint32_t)0x180000B8)
260
261 #define RCC_LSITRIM_38K (*(uint16_t *)(LSI38K_TRIM_ADDR))
262 #define RCC_LSITRIM_32K (*(uint16_t *)(LSI32K_TRIM_ADDR))
263
264 #define RCC_LSITC_38K (*(uint16_t *)(LSI38K_TC_ADDR))
265 #define RCC_LSITC_32K (*(uint16_t *)(LSI32K_TC_ADDR))
266
267 #define RCC_LSICALIBRATION_DEFAULT 0x0000007FU
268
277 /* Exported macro ------------------------------------------------------------*/
278
279 #define IS_HSI_VALUE(VALUE) (((VALUE) == HSI_VALUE_24M) || \
280 ((VALUE) == HSI_VALUE_22M) || \
281 ((VALUE) == HSI_VALUE_16M) || \
282 ((VALUE) == HSI_VALUE_8M) || \
283 ((VALUE) == HSI_VALUE_4M))
284
285 #define IS_LSI_VALUE(VALUE) (((VALUE) == LSI_VALUE_38K) || \
286 ((VALUE) == LSI_VALUE_32K))
287
288 #define IS_RCC_LSI_STARTUP(TIME) (((TIME) == RCC_LSI_STARTUP_4CYCLE) || \
289 ((TIME) == RCC_LSI_STARTUP_16CYCLE) || \
290 ((TIME) == RCC_LSI_STARTUP_64CYCLE) || \
291 ((TIME) == RCC_LSI_STARTUP_256CYCLE))
292
293 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || \
294 ((HSE) == RCC_HSE_ON) || \
295 ((HSE) == RCC_HSE_BYPASS) || \
296 ((HSE) == RCC_HSE_DEFAULT))
297
298 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || \
299 ((LSE) == RCC_LSE_ON) || \
300 ((LSE) == RCC_LSE_BYPASS) || \
301 ((LSE) == RCC_LSE_DEFAULT))
302
303 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
304 ((SOURCE) == RCC_SYSCLKSource_HSE) || \
305 ((SOURCE) == RCC_SYSCLKSource_LSI) || \
306 ((SOURCE) == RCC_SYSCLKSource_LSE))
307
308 #define IS_RCC_AHBCLKDiv(DIV) (((int32_t)(DIV) > 0) && ((DIV) <= 510))
309
310 #define IS_RCC_APBCLKDiv(DIV) (((int32_t)(DIV) > 0) && ((DIV) <= 510))
311
312 #define IS_RCC_MCO_HCLkDiv(DIV) (((int32_t)(DIV) > 0) && ((DIV) <= 510))
313
314 #define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_HSI) || \
315 ((SOURCE) == RCC_MCOSOURCE_HSE) || \
316 ((SOURCE) == RCC_MCOSOURCE_LSI) || \
317 ((SOURCE) == RCC_MCOSOURCE_LSE) || \
318 ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
319 ((SOURCE) == RCC_MCOSOURCE_HCLK))
320
321 #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & RCC_AHBPeriph_ALL) != 0))
322
323 #define IS_RCC_APB_PERIPH(PERIPH) ((((PERIPH) & RCC_APBPeriph_ALL) != 0))
324
325 #define IS_RCC_RESET_FLAG(FLAG) (((FLAG) == RCC_RSTFLAG_MCURST) || \
326 ((FLAG) == RCC_RSTFLAG_CPURST) || \
327 ((FLAG) == RCC_RSTFLAG_WWDGRST) || \
328 ((FLAG) == RCC_RSTFLAG_IWDGRST) || \
329 ((FLAG) == RCC_RSTFLAG_LVDRST) || \
330 ((FLAG) == RCC_RSTFLAG_PORRST) || \
331 ((FLAG) == RCC_RSTFLAG_LOCKUPRST) || \
332 ((FLAG) == RCC_RSTFLAG_PADRST) || \
333 ((FLAG) == RCC_RSTFLAG_SFTRST))
334 /* Exported functions --------------------------------------------------------*/
335
336 void RCC_DeInit(void);
337
338 void RCC_HSIConfig(uint32_t HSI_Value, FunctionalState NewState);
339 void RCC_LSIConfig(uint32_t LSI_Value, uint32_t LSI_StartUPTime, FunctionalState NewState);
340 void RCC_HSEConfig(uint32_t RCC_HSE);
341 void RCC_LSEConfig(uint32_t RCC_LSE);
342
343 void RCC_HSEDriveCurrentConfig(uint32_t Current);
344 void RCC_HSEStartTimeConfig(uint32_t Time);
345 void RCC_LSEDriveCurrentConfig(uint32_t Current);
346 void RCC_LSEStartTimeConfig(uint32_t Time);
347
348 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
349 void RCC_AHBCLKConfig(uint32_t RCC_AHBCLKDiv);
350 void RCC_APBCLKConfig(uint32_t RCC_APBCLKDiv);
351
352 void RCC_MCOConfig(uint32_t RCC_MCOSource, uint32_t RCC_MCOHCLKDiv);
353 void RCC_MCOCmd(FunctionalState NewState);
354 void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks);
355
356 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
357 void RCC_APBPeriphClockCmd(uint32_t RCC_APBPeriph, FunctionalState NewState);
358 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
359 void RCC_APBPeriphResetCmd(uint32_t RCC_APBPeriph, FunctionalState NewState);
360 void RCC_RTCPeriphResetCmd(FunctionalState NewState);
361
362 FlagStatus RCC_GetResetFlagStatus(uint32_t RCC_RSTFLAG);
363 void RCC_ClearResetFlags(uint32_t RCC_RSTFLAG);
364
373 #ifdef __cplusplus
374 }
375 #endif
376
377 #endif /* __MG32L003_RCC_H */
RCC_ClocksTypeDef::AHBCLK_Frequency
uint32_t AHBCLK_Frequency
Definition: mg32l003_rcc.h:33
RCC_MCOCmd
void RCC_MCOCmd(FunctionalState NewState)
Enable or Disable the MCO Clock output.
Definition: mg32l003_rcc.c:466
RCC_LSEDriveCurrentConfig
void RCC_LSEDriveCurrentConfig(uint32_t Current)
Configures the drive current of Low Speed oscillator (LSE).
Definition: mg32l003_rcc.c:359
RCC_APBPeriphResetCmd
void RCC_APBPeriphResetCmd(uint32_t RCC_APBPeriph, FunctionalState NewState)
Forces or releases APB peripheral reset.
Definition: mg32l003_rcc.c:692
RCC_DeInit
void RCC_DeInit(void)
Resets the RCC clock configuration to the default reset state.
Definition: mg32l003_rcc.c:58
RCC_HSIConfig
void RCC_HSIConfig(uint32_t HSI_Value, FunctionalState NewState)
Configures the Internal High Speed oscillator (HSI).
Definition: mg32l003_rcc.c:106
RCC_MCOConfig
void RCC_MCOConfig(uint32_t RCC_MCOSource, uint32_t RCC_MCOHCLKDiv)
Selects the clock source to output on MCO pin.
Definition: mg32l003_rcc.c:451
RCC_AHBPeriphClockCmd
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
Enables or disables the AHB peripheral clock.
Definition: mg32l003_rcc.c:572
RCC_ClearResetFlags
void RCC_ClearResetFlags(uint32_t RCC_RSTFLAG)
Clear the specified RCC reset flag.
Definition: mg32l003_rcc.c:788
RCC_HSEConfig
void RCC_HSEConfig(uint32_t RCC_HSE)
Configures the External High Speed oscillator (HSE).
Definition: mg32l003_rcc.c:251
RCC_HSEStartTimeConfig
void RCC_HSEStartTimeConfig(uint32_t Time)
Configures the start time of High Speed oscillator (HSE).
Definition: mg32l003_rcc.c:343
RCC_HSEDriveCurrentConfig
void RCC_HSEDriveCurrentConfig(uint32_t Current)
Configures the drive current of High Speed oscillator (HSE).
Definition: mg32l003_rcc.c:327
RCC_LSEStartTimeConfig
void RCC_LSEStartTimeConfig(uint32_t Time)
Configures the start time of Low Speed oscillator (LSE).
Definition: mg32l003_rcc.c:375
RCC_GetResetFlagStatus
FlagStatus RCC_GetResetFlagStatus(uint32_t RCC_RSTFLAG)
Checks whether the specified RCC reset flag is set or not.
Definition: mg32l003_rcc.c:753
RCC_APBPeriphClockCmd
void RCC_APBPeriphClockCmd(uint32_t RCC_APBPeriph, FunctionalState NewState)
Enables or disables the APB peripheral clock.
Definition: mg32l003_rcc.c:616
RCC_RTCPeriphResetCmd
void RCC_RTCPeriphResetCmd(FunctionalState NewState)
Forces or releases RTC peripheral reset.
Definition: mg32l003_rcc.c:717
RCC_APBCLKConfig
void RCC_APBCLKConfig(uint32_t RCC_APBCLKDiv)
Configures the APB clock (APBCLK).
Definition: mg32l003_rcc.c:428
RCC_ClocksTypeDef::SYSCLK_Frequency
uint32_t SYSCLK_Frequency
Definition: mg32l003_rcc.h:32
RCC_LSEConfig
void RCC_LSEConfig(uint32_t RCC_LSE)
Configures the External Low Speed oscillator (LSE).
Definition: mg32l003_rcc.c:289
RCC_ClocksTypeDef::APBCLK_Frequency
uint32_t APBCLK_Frequency
Definition: mg32l003_rcc.h:34
RCC_AHBCLKConfig
void RCC_AHBCLKConfig(uint32_t RCC_AHBCLKDiv)
Configures the AHB clock (AHBCLK).
Definition: mg32l003_rcc.c:413
RCC_LSIConfig
void RCC_LSIConfig(uint32_t LSI_Value, uint32_t LSI_StartUPTime, FunctionalState NewState)
Configures the Internal low Speed oscillator (LSI).
Definition: mg32l003_rcc.c:174
RCC_AHBPeriphResetCmd
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
Forces or releases AHB peripheral reset.
Definition: mg32l003_rcc.c:644
RCC_GetClocksFreq
void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks)
Returns the frequencies of different on chip clocks.
Definition: mg32l003_rcc.c:484
RCC_SYSCLKConfig
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
Configures the SYS Clock (SYSCLK).
Definition: mg32l003_rcc.c:394
RCC_ClocksTypeDef
Definition: mg32l003_rcc.h:30