MG32L003 Standard Peripherals Firmware Library

模块 | 宏定义
SYSCON
MG32L003_StdPeriph_Driver

SYSCON driver modules 更多...

## 模块
| SYSCON_Exported_Constants

## 宏定义
#define | SYSCON_REGWR_LOCK() (SYSCON->UNLOCK = (0x2AD5334C << SYSCON_UNLOCK_KEY_Pos) & SYSCON_UNLOCK_KEY)
#define | SYSCON_REGWR_UNLOCK() (SYSCON->UNLOCK = SYSCON_UNLOCK_UNLOCK | (0x2AD5334C << SYSCON_UNLOCK_KEY_Pos))
#define | SYSCON_DBGDEEPSLEEP_ENABLE()
| Macro to disable deep sleep mode in debug mode, allow to debug deep sleep mode. 更多...
#define | SYSCON_DBGDEEPSLEEP_DISABLE()
| Macro to enable deep sleep mode in debug mode, debug mode will quit in deep sleep mode. 更多...
#define | SYSCON_LOCKUP_ENABLE()
| Macro to enable cpu lock up function. 更多...
#define | SYSCON_LOCKUP_DISABLE()
| Macro to disable cpu lock up function. 更多...
#define | SYSCON_DEEPSLEEP_PADINT_AUTO()
| Macro to config PAD interrupt mode as AUTO for deep sleep:. 更多...
#define | SYSCON_DEEPSLEEP_PADINT_ACTIVE()
| Macro to config PAD interrupt mode as ACTIVE for deep sleep. 更多...
#define | SYSCON_LPTIM_GATE(SOURCE)
| Macro to select low power timer gate signal input source from gpio. 更多...
#define | SYSCON_TIM11_GATE(SOURCE)
| Macro to select timer11 gate signal input source from gpio. 更多...
#define | SYSCON_TIM10_GATE(SOURCE)
| Macro to select timer10 gate signal input source from gpio. 更多...
#define | SYSCON_SPINCS(SOURCE)
| Macro to select spi slave mode NCS signal input source from gpio. 更多...
#define | SYSCON_PCA_CAP4(SOURCE)
| Macro to select pca cap4 signal input source from gpio. 更多...
#define | SYSCON_PCA_CAP3(SOURCE)
| Macro to select pca cap3 signal input source from gpio. 更多...
#define | SYSCON_PCA_CAP2(SOURCE)
| Macro to select pca cap2 signal input source from gpio. 更多...
#define | SYSCON_PCA_CAP1(SOURCE)
| Macro to select pca cap1 signal input source from gpio. 更多...
#define | SYSCON_PCA_CAP0(SOURCE)
| Macro to select pca cap0 signal input source from gpio. 更多...
#define | SYSCON_TIM1_BREAKIN_SEL(SOURCE)
| Macro to select timer1 break signal input source from other peripheral. 更多...
#define | SYSCON_TIM1_BREAKOUT_CFG(CONFIG)
| Macro to configure timer1 ocxp/ocxnp output signal when break. 更多...
#define | SYSCON_TIM1ETR_SEL(SOURCE)
| Macro to select timer1 etr signal input source from gpio. 更多...
#define | SYSCON_TIM1CH4IN_SEL(SOURCE)
| Macro to select tim1 ch4 signal input source from gpio. 更多...
#define | SYSCON_TIM1CH3IN_SEL(SOURCE)
| Macro to select tim1 ch3 signal input source from gpio. 更多...
#define | SYSCON_TIM1CH2IN_SEL(SOURCE)
| Macro to select tim1 ch2 signal input source from gpio. 更多...
#define | SYSCON_TIM1CH1IN_SEL(SOURCE)
| Macro to select tim1 ch1 signal input source from gpio. 更多...
#define | SYSCON_TIM2ETR_SEL(SOURCE)
| Macro to select timer2 etr signal input source from gpio. 更多...
#define | SYSCON_TIM2CH4IN_SEL(SOURCE)
| Macro to select tim2 ch4 signal input source from gpio. 更多...
#define | SYSCON_TIM2CH3IN_SEL(SOURCE)
| Macro to select tim2 ch3 signal input source from gpio. 更多...
#define | SYSCON_TIM2CH2IN_SEL(SOURCE)
| Macro to select tim2 ch2 signal input source from gpio. 更多...
#define | SYSCON_TIM2CH1IN_SEL(SOURCE)
| Macro to select tim2 ch1 signal input source from gpio. 更多...

## 详细描述

SYSCON driver modules

## 宏定义说明

## ◆ SYSCON_DBGDEEPSLEEP_DISABLE

#define SYSCON_DBGDEEPSLEEP_DISABLE | ( |  | ) |

值:
do { \
SYSCON_REGWR_UNLOCK(); \
CLEAR_WPBIT(SYSCON->CFGR0, SYSCON_CFGR0_DBGDLSP_DIS, (SYSCON_CFGR0_KEY << SYSCON_CFGR0_KEY_Pos)); \
SYSCON_REGWR_LOCK(); \
} while (0)
SYSCON_CFGR0_KEY_Pos
#define SYSCON_CFGR0_KEY_Pos
Definition: mg32l003.h:3140

Macro to enable deep sleep mode in debug mode, debug mode will quit in deep sleep mode.

注解
  In debug mode, deep sleep mode will make debug mode quit

## ◆ SYSCON_DBGDEEPSLEEP_ENABLE

#define SYSCON_DBGDEEPSLEEP_ENABLE | ( |  | ) |

值:
do { \
SYSCON_REGWR_UNLOCK(); \
SET_BIT(SYSCON->CFGR0, SYSCON_CFGR0_DBGDLSP_DIS | (SYSCON_CFGR0_KEY << SYSCON_CFGR0_KEY_Pos)); \
SYSCON_REGWR_LOCK(); \
} while (0)
SYSCON_CFGR0_KEY_Pos
#define SYSCON_CFGR0_KEY_Pos
Definition: mg32l003.h:3140

Macro to disable deep sleep mode in debug mode, allow to debug deep sleep mode.

注解
  In debug mode, CPU will not enter deep sleep mode

## ◆ SYSCON_DEEPSLEEP_PADINT_ACTIVE

#define SYSCON_DEEPSLEEP_PADINT_ACTIVE | ( |  | ) |

值:
do { \
SYSCON_REGWR_UNLOCK(); \
SET_BIT(SYSCON->PORTINTCR, SYSCON_PORTINTCR_PADDLSPCON | (SYSCON_UNLOCK_KEY << SYSCON_PORTINTCR_KEY_Pos)); \
CLEAR_WPBIT(SYSCON->PORTINTCR, SYSCON_PORTINTCR_PADINTSEL, (SYSCON_UNLOCK_KEY << SYSCON_PORTINTCR_KEY_Pos)); \
SYSCON_REGWR_LOCK(); \
} while (0)
SYSCON_PORTINTCR_KEY_Pos
#define SYSCON_PORTINTCR_KEY_Pos
Definition: mg32l003.h:3150

Macro to config PAD interrupt mode as ACTIVE for deep sleep.

## ◆ SYSCON_DEEPSLEEP_PADINT_AUTO

#define SYSCON_DEEPSLEEP_PADINT_AUTO | ( |  | ) |

值:
do { \
SYSCON_REGWR_UNLOCK(); \
CLEAR_WPBIT(SYSCON->PORTINTCR, SYSCON_PORTINTCR_PADDLSPCON, (SYSCON_UNLOCK_KEY << SYSCON_PORTINTCR_KEY_Pos)); \
SYSCON_REGWR_LOCK(); \
} while (0)
SYSCON_PORTINTCR_KEY_Pos
#define SYSCON_PORTINTCR_KEY_Pos
Definition: mg32l003.h:3150

Macro to config PAD interrupt mode as AUTO for deep sleep:.

## ◆ SYSCON_LOCKUP_DISABLE

#define SYSCON_LOCKUP_DISABLE | ( |  | ) |

值:
do { \
SYSCON_REGWR_UNLOCK(); \
CLEAR_WPBIT(SYSCON->CFGR0, SYSCON_CFGR0_LOCKUPEN, (SYSCON_CFGR0_KEY << SYSCON_CFGR0_KEY_Pos)); \
SYSCON_REGWR_LOCK(); \
} while (0)
SYSCON_CFGR0_KEY_Pos
#define SYSCON_CFGR0_KEY_Pos
Definition: mg32l003.h:3140

Macro to disable cpu lock up function.

## ◆ SYSCON_LOCKUP_ENABLE

#define SYSCON_LOCKUP_ENABLE | ( |  | ) |

值:
do { \
SYSCON_REGWR_UNLOCK(); \
SET_BIT(SYSCON->CFGR0, SYSCON_CFGR0_LOCKUPEN | (SYSCON_CFGR0_KEY << SYSCON_CFGR0_KEY_Pos)); \
SYSCON_REGWR_LOCK(); \
} while (0)
SYSCON_CFGR0_KEY_Pos
#define SYSCON_CFGR0_KEY_Pos
Definition: mg32l003.h:3140

Macro to enable cpu lock up function.

## ◆ SYSCON_LPTIM_GATE

#define SYSCON_LPTIM_GATE | ( |  | SOURCE | ) |

值:
do { \
SYSCON_REGWR_UNLOCK(); \
MODIFY_REG(SYSCON->PORTCR, SYSCON_PORTCR_LPTIM_GATE_SEL, ((SOURCE) << SYSCON_PORTCR_LPTIM_GATE_SEL_Pos)); \
SYSCON_REGWR_UNLOCK(); \
} while (0)
SYSCON_PORTCR_LPTIM_GATE_SEL_Pos
#define SYSCON_PORTCR_LPTIM_GATE_SEL_Pos
Definition: mg32l003.h:3169

Macro to select low power timer gate signal input source from gpio.

参数

  SOURCE | source for LPTIM gate input This parameter can be one of the following values: SYSCON_DEFAULT: LPTIM_GATE alternate function is low power timer gate signal input source SYSCON_UART1_RXD: UART1_RXD alternate function is low power timer gate signal input source SYSCON_UART2_RXD: UART2_RXD alternate function is low power timer gate signal input source SYSCON_LPUART_RXD: LPUART_RXD alternate function is low power timer gate signal input source

## ◆ SYSCON_PCA_CAP0

#define SYSCON_PCA_CAP0 | ( |  | SOURCE | ) |

值:
do { \
SYSCON_REGWR_UNLOCK(); \
MODIFY_REG(SYSCON->PCACR, SYSCON_PCACR_PCA_CAP0_SEL, ((SOURCE) << SYSCON_PCACR_PCA_CAP0_SEL_Pos)); \
SYSCON_REGWR_LOCK(); \
} while (0)
SYSCON_PCACR_PCA_CAP0_SEL_Pos
#define SYSCON_PCACR_PCA_CAP0_SEL_Pos
Definition: mg32l003.h:3173

Macro to select pca cap0 signal input source from gpio.

参数

  SOURCE | source for pca cap0 input This parameter can be one of the following values: SYSCON_DEFAULT: PCA_CH0 alternate function is pca cap0 signal input source SYSCON_UART1_RXD: UART1_RXD alternate function is pca cap0 signal input source SYSCON_UART2_RXD: UART2_RXD alternate function is pca cap0 signal input source SYSCON_LPUART_RXD: LPUART_RXD alternate function is pca cap0 signal input source

## ◆ SYSCON_PCA_CAP1

#define SYSCON_PCA_CAP1 | ( |  | SOURCE | ) |

值:
do { \
SYSCON_REGWR_UNLOCK(); \
MODIFY_REG(SYSCON->PCACR, SYSCON_PCACR_PCA_CAP1_SEL, ((SOURCE) << SYSCON_PCACR_PCA_CAP1_SEL_Pos)); \
SYSCON_REGWR_LOCK(); \
} while (0)
SYSCON_PCACR_PCA_CAP1_SEL_Pos
#define SYSCON_PCACR_PCA_CAP1_SEL_Pos
Definition: mg32l003.h:3176

Macro to select pca cap1 signal input source from gpio.

参数

  SOURCE | source for pca cap1 input This parameter can be one of the following values: SYSCON_DEFAULT: PCA_CH1 alternate function is pca cap1 signal input source SYSCON_UART1_RXD: UART1_RXD alternate function is pca cap1 signal input source SYSCON_UART2_RXD: UART2_RXD alternate function is pca cap1 signal input source SYSCON_LPUART_RXD: LPUART_RXD alternate function is pca cap1 signal input source

## ◆ SYSCON_PCA_CAP2

#define SYSCON_PCA_CAP2 | ( |  | SOURCE | ) |

值:
do { \
SYSCON_REGWR_UNLOCK(); \
MODIFY_REG(SYSCON->PCACR, SYSCON_PCACR_PCA_CAP2_SEL, ((SOURCE) << SYSCON_PCACR_PCA_CAP2_SEL_Pos)); \
SYSCON_REGWR_LOCK(); \
} while (0)
SYSCON_PCACR_PCA_CAP2_SEL_Pos
#define SYSCON_PCACR_PCA_CAP2_SEL_Pos
Definition: mg32l003.h:3179

Macro to select pca cap2 signal input source from gpio.

参数

  SOURCE | source for pca cap2 input This parameter can be one of the following values: SYSCON_DEFAULT: PCA_CH2 alternate function is pca cap2 signal input source SYSCON_UART1_RXD: UART1_RXD alternate function is pca cap2 signal input source SYSCON_UART2_RXD: UART2_RXD alternate function is pca cap2 signal input source SYSCON_LPUART_RXD: LPUART_RXD alternate function is pca cap2 signal input source

## ◆ SYSCON_PCA_CAP3

#define SYSCON_PCA_CAP3 | ( |  | SOURCE | ) |

值:
do { \
SYSCON_REGWR_UNLOCK(); \
MODIFY_REG(SYSCON->PCACR, SYSCON_PCACR_PCA_CAP3_SEL, ((SOURCE) << SYSCON_PCACR_PCA_CAP3_SEL_Pos)); \
SYSCON_REGWR_LOCK(); \
} while (0)
SYSCON_PCACR_PCA_CAP3_SEL_Pos
#define SYSCON_PCACR_PCA_CAP3_SEL_Pos
Definition: mg32l003.h:3182

Macro to select pca cap3 signal input source from gpio.

参数

  SOURCE | source for pca cap3 input This parameter can be one of the following values: SYSCON_DEFAULT: PCA_CH3 alternate function is pca cap3 signal input source SYSCON_UART1_RXD: UART1_RXD alternate function is pca cap3 signal input source SYSCON_UART2_RXD: UART2_RXD alternate function is pca cap3 signal input source SYSCON_LPUART_RXD: LPUART_RXD alternate function is pca cap3 signal input source

## ◆ SYSCON_PCA_CAP4

#define SYSCON_PCA_CAP4 | ( |  | SOURCE | ) |

值:
do { \
SYSCON_REGWR_UNLOCK(); \
MODIFY_REG(SYSCON->PCACR, SYSCON_PCACR_PCA_CAP4_SEL, ((SOURCE) << SYSCON_PCACR_PCA_CAP4_SEL_Pos)); \
SYSCON_REGWR_LOCK(); \
} while (0)
SYSCON_PCACR_PCA_CAP4_SEL_Pos
#define SYSCON_PCACR_PCA_CAP4_SEL_Pos
Definition: mg32l003.h:3185

Macro to select pca cap4 signal input source from gpio.

参数

  SOURCE | source for pca cap4 input This parameter can be one of the following values: SYSCON_DEFAULT: PCA_CH4 alternate function is pca cap4 signal input source SYSCON_UART1_RXD: UART1_RXD alternate function is pca cap4 signal input source SYSCON_UART2_RXD: UART2_RXD alternate function is pca cap4 signal input source SYSCON_LPUART_RXD: LPUART_RXD alternate function is pca cap4 signal input source

## ◆ SYSCON_SPINCS

#define SYSCON_SPINCS | ( |  | SOURCE | ) |

值:
do { \
SYSCON_REGWR_UNLOCK(); \
MODIFY_REG(SYSCON->PORTCR, SYSCON_PORTCR_SPINCS_SEL, (SOURCE)); \
SYSCON_REGWR_LOCK(); \
} while (0)

Macro to select spi slave mode NCS signal input source from gpio.

参数

  SOURCE | source for spi NCS signal input This parameter can be one of the following values: SYSCON_SPI_NCS_HIGHLEVEL: high level is spi NCS input source SYSCON_SPI_NCS_PA1: PA1 is spi NCS input source SYSCON_SPI_NCS_PA2: PA2 is spi NCS input source SYSCON_SPI_NCS_PA3: PA3 is spi NCS input source SYSCON_SPI_NCS_PB4: PB4 is spi NCS input source SYSCON_SPI_NCS_PB5: PB5 is spi NCS input source SYSCON_SPI_NCS_PC3: PC3 is spi NCS input source SYSCON_SPI_NCS_PC4: PC4 is spi NCS input source SYSCON_SPI_NCS_PC5: PC5 is spi NCS input source SYSCON_SPI_NCS_PC6: PC6 is spi NCS input source SYSCON_SPI_NCS_PC7: PC7 is spi NCS input source SYSCON_SPI_NCS_PD1: PD1 is spi NCS input source SYSCON_SPI_NCS_PD2: PD2 is spi NCS input source SYSCON_SPI_NCS_PD3: PD3 is spi NCS input source SYSCON_SPI_NCS_PD4: PD4 is spi NCS input source SYSCON_SPI_NCS_PD6: PD6 is spi NCS input source SYSCON_SPI_NCS_PA4: PA4 is spi NCS input source SYSCON_SPI_NCS_PB0: PB0 is spi NCS input source SYSCON_SPI_NCS_PB1: PB1 is spi NCS input source SYSCON_SPI_NCS_PB2: PB2 is spi NCS input source SYSCON_SPI_NCS_PB3: PB3 is spi NCS input source SYSCON_SPI_NCS_PB6: PB6 is spi NCS input source SYSCON_SPI_NCS_PB7: PB7 is spi NCS input source SYSCON_SPI_NCS_PC0: PC0 is spi NCS input source SYSCON_SPI_NCS_PC1: PC1 is spi NCS input source SYSCON_SPI_NCS_PC2: PC2 is spi NCS input source SYSCON_SPI_NCS_PD0: PD0 is spi NCS input source SYSCON_SPI_NCS_PD7: PD7 is spi NCS input source

## ◆ SYSCON_TIM10_GATE

#define SYSCON_TIM10_GATE | ( |  | SOURCE | ) |

值:
do { \
SYSCON_REGWR_UNLOCK(); \
MODIFY_REG(SYSCON->PORTCR, SYSCON_PORTCR_TIM10_GATE_SEL, ((SOURCE) << SYSCON_PORTCR_TIM10_GATE_SEL_Pos)); \
SYSCON_REGWR_LOCK(); \
} while (0)
SYSCON_PORTCR_TIM10_GATE_SEL_Pos
#define SYSCON_PORTCR_TIM10_GATE_SEL_Pos
Definition: mg32l003.h:3163

Macro to select timer10 gate signal input source from gpio.

参数

  SOURCE | source for TIM10 gate input This parameter can be one of the following values: SYSCON_DEFAULT: TIM10_GATE alternate function is timer10 gate signal input source SYSCON_UART1_RXD: UART1_RXD alternate function is timer10 gate signal input source SYSCON_UART2_RXD: UART2_RXD alternate function is timer10 gate signal input source SYSCON_LPUART_RXD: LPUART_RXD alternate function is timer10 gate signal input source

## ◆ SYSCON_TIM11_GATE

#define SYSCON_TIM11_GATE | ( |  | SOURCE | ) |

值:
do { \
SYSCON_REGWR_UNLOCK(); \
MODIFY_REG(SYSCON->PORTCR, SYSCON_PORTCR_TIM11_GATE_SEL, ((SOURCE) << SYSCON_PORTCR_TIM11_GATE_SEL_Pos)); \
SYSCON_REGWR_LOCK(); \
} while (0)
SYSCON_PORTCR_TIM11_GATE_SEL_Pos
#define SYSCON_PORTCR_TIM11_GATE_SEL_Pos
Definition: mg32l003.h:3166

Macro to select timer11 gate signal input source from gpio.

参数

  SOURCE | source for TIM11 gate input This parameter can be one of the following values: SYSCON_DEFAULT: TIM11_GATE alternate function is timer11 gate signal input source SYSCON_UART1_RXD: UART1_RXD alternate function is timer11 gate signal input source SYSCON_UART2_RXD: UART2_RXD alternate function is timer11 gate signal input source SYSCON_LPUART_RXD: LPUART_RXD alternate function is timer11 gate signal input source

## ◆ SYSCON_TIM1_BREAKIN_SEL

#define SYSCON_TIM1_BREAKIN_SEL | ( |  | SOURCE | ) |

值:
do { \
SYSCON_REGWR_UNLOCK(); \
MODIFY_REG(SYSCON->TIM1CR, SYSCON_TIM1CR_CLKFAILBRKEN | SYSCON_TIM1CR_DSLPBRKEN, (SOURCE)); \
SYSCON_REGWR_LOCK(); \
} while (0)

Macro to select timer1 break signal input source from other peripheral.

参数

  SOURCE | source for timer1 break signal input This parameter can be any combination the following values: SYSCON_CLKFAILBRKEN: clock fail is timer1 break signal input source SYSCON_DSLPBRKEN: deep sleep is timer1 break signal input source

## ◆ SYSCON_TIM1_BREAKOUT_CFG

#define SYSCON_TIM1_BREAKOUT_CFG | ( |  | CONFIG | ) |

值:
do { \
SYSCON_REGWR_UNLOCK(); \
MODIFY_REG(SYSCON->TIM1CR, SYSCON_TIM1CR_TIM1BRKOUTCFG, (CONFIG)); \
SYSCON_REGWR_LOCK(); \
} while (0)

Macro to configure timer1 ocxp/ocxnp output signal when break.

参数

  CONFIG | config ocxp/ocxnp output signal when break received This parameter can be one of the following values: SYSCON_OCOUT_LOWLEVEL: ocxp/ocxnp output low level when break received SYSCON_OCOUT_BYTIM1: ocxp/ocxnp output controlled by timer1 configuration when break received

## ◆ SYSCON_TIM1CH1IN_SEL

#define SYSCON_TIM1CH1IN_SEL | ( |  | SOURCE | ) |

值:
do { \
SYSCON_REGWR_UNLOCK(); \
MODIFY_REG(SYSCON->TIM1CR, SYSCON_TIM1CR_TIM1CH1IN_SEL, ((SOURCE) << SYSCON_TIM1CR_TIM1CH1IN_SEL_Pos)); \
SYSCON_REGWR_LOCK(); \
} while (0)
SYSCON_TIM1CR_TIM1CH1IN_SEL_Pos
#define SYSCON_TIM1CR_TIM1CH1IN_SEL_Pos
Definition: mg32l003.h:3189

Macro to select tim1 ch1 signal input source from gpio.

参数

  SOURCE | source for tim1 ch1 input This parameter can be one of the following values: SYSCON_DEFAULT: TIM1_CH1 alternate function is tim1 ch1 signal input source SYSCON_UART1_RXD: UART1_RXD alternate function is tim1 ch1 signal input source SYSCON_UART2_RXD: UART2_RXD alternate function is tim1 ch1 signal input source SYSCON_LPUART_RXD: LPUART_RXD alternate function is tim1 ch1 signal input source SYSCON_LSI: LSI is tim1 ch1 signal input source

## ◆ SYSCON_TIM1CH2IN_SEL

#define SYSCON_TIM1CH2IN_SEL | ( |  | SOURCE | ) |

值:
do { \
SYSCON_REGWR_UNLOCK(); \
MODIFY_REG(SYSCON->TIM1CR, SYSCON_TIM1CR_TIM1CH2IN_SEL, ((SOURCE) << SYSCON_TIM1CR_TIM1CH2IN_SEL_Pos)); \
SYSCON_REGWR_LOCK(); \
} while (0)
SYSCON_TIM1CR_TIM1CH2IN_SEL_Pos
#define SYSCON_TIM1CR_TIM1CH2IN_SEL_Pos
Definition: mg32l003.h:3192

Macro to select tim1 ch2 signal input source from gpio.

参数

  SOURCE | source for tim1 ch2 input This parameter can be one of the following values: SYSCON_DEFAULT: TIM1_CH2 alternate function is tim1 ch2 signal input source SYSCON_UART1_RXD: UART1_RXD alternate function is tim1 ch2 signal input source SYSCON_UART2_RXD: UART2_RXD alternate function is tim1 ch2 signal input source SYSCON_LPUART_RXD: LPUART_RXD alternate function is tim1 ch2 signal input source SYSCON_LSI: LSI is tim1 ch2 signal input source

## ◆ SYSCON_TIM1CH3IN_SEL

#define SYSCON_TIM1CH3IN_SEL | ( |  | SOURCE | ) |

值:
do { \
SYSCON_REGWR_UNLOCK(); \
MODIFY_REG(SYSCON->TIM1CR, SYSCON_TIM1CR_TIM1CH3IN_SEL, ((SOURCE) << SYSCON_TIM1CR_TIM1CH3IN_SEL_Pos)); \
SYSCON_REGWR_LOCK(); \
} while (0)
SYSCON_TIM1CR_TIM1CH3IN_SEL_Pos
#define SYSCON_TIM1CR_TIM1CH3IN_SEL_Pos
Definition: mg32l003.h:3195

Macro to select tim1 ch3 signal input source from gpio.

参数

  SOURCE | source for tim1 ch3 input This parameter can be one of the following values: SYSCON_DEFAULT: TIM1_CH3 alternate function is tim1 ch3 signal input source SYSCON_UART1_RXD: UART1_RXD alternate function is tim1 ch3 signal input source SYSCON_UART2_RXD: UART2_RXD alternate function is tim1 ch3 signal input source SYSCON_LPUART_RXD: LPUART_RXD alternate function is tim1 ch3 signal input source SYSCON_LSI: LSI is tim1 ch3 signal input source

## ◆ SYSCON_TIM1CH4IN_SEL

#define SYSCON_TIM1CH4IN_SEL | ( |  | SOURCE | ) |

值:
do { \
SYSCON_REGWR_UNLOCK(); \
MODIFY_REG(SYSCON->TIM1CR, SYSCON_TIM1CR_TIM1CH4IN_SEL, ((SOURCE) << SYSCON_TIM1CR_TIM1CH4IN_SEL_Pos)); \
SYSCON_REGWR_LOCK(); \
} while (0)
SYSCON_TIM1CR_TIM1CH4IN_SEL_Pos
#define SYSCON_TIM1CR_TIM1CH4IN_SEL_Pos
Definition: mg32l003.h:3198

Macro to select tim1 ch4 signal input source from gpio.

参数

  SOURCE | source for tim1 ch4 input This parameter can be one of the following values: SYSCON_DEFAULT: TIM1_CH4 alternate function is tim1 ch4 signal input source SYSCON_UART1_RXD: UART1_RXD alternate function is tim1 ch4 signal input source SYSCON_UART2_RXD: UART2_RXD alternate function is tim1 ch4 signal input source SYSCON_LPUART_RXD: LPUART_RXD alternate function is tim1 ch4 signal input source SYSCON_LSI: LSI is tim1 ch4 signal input source

## ◆ SYSCON_TIM1ETR_SEL

#define SYSCON_TIM1ETR_SEL | ( |  | SOURCE | ) |

值:
do { \
SYSCON_REGWR_UNLOCK(); \
MODIFY_REG(SYSCON->TIM1CR, SYSCON_TIM1CR_TIM1ETR_SEL, (SOURCE)); \
SYSCON_REGWR_LOCK(); \
} while (0)

Macro to select timer1 etr signal input source from gpio.

参数

  SOURCE | source for timer1 etr input This parameter can be one of the following values: SYSCON_TIM_ETR_LOWLEVEL: low level is timer1 etr input source SYSCON_TIM_ETR_PA1: PA1 is timer1 etr input source SYSCON_TIM_ETR_PA2: PA2 is timer1 etr input source SYSCON_TIM_ETR_PA3: PA3 is timer1 etr input source SYSCON_TIM_ETR_PB4: PB4 is timer1 etr input source SYSCON_TIM_ETR_PB5: PB5 is timer1 etr input source SYSCON_TIM_ETR_PC3: PC3 is timer1 etr input source SYSCON_TIM_ETR_PC4: PC4 is timer1 etr input source SYSCON_TIM_ETR_PC5: PC5 is timer1 etr input source SYSCON_TIM_ETR_PC6: PC6 is timer1 etr input source SYSCON_TIM_ETR_PC7: PC7 is timer1 etr input source SYSCON_TIM_ETR_PD1: PD1 is timer1 etr input source SYSCON_TIM_ETR_PD2: PD2 is timer1 etr input source SYSCON_TIM_ETR_PD3: PD3 is timer1 etr input source SYSCON_TIM_ETR_PD4: PD4 is timer1 etr input source SYSCON_TIM_ETR_PD6: PD6 is timer1 etr input source SYSCON_TIM_ETR_PA4: PA4 is timer1 etr input source SYSCON_TIM_ETR_PB0: PB0 is timer1 etr input source SYSCON_TIM_ETR_PB1: PB1 is timer1 etr input source SYSCON_TIM_ETR_PB2: PB2 is timer1 etr input source SYSCON_TIM_ETR_PB3: PB3 is timer1 etr input source SYSCON_TIM_ETR_PB6: PB6 is timer1 etr input source SYSCON_TIM_ETR_PB7: PB7 is timer1 etr input source SYSCON_TIM_ETR_PC0: PC0 is timer1 etr input source SYSCON_TIM_ETR_PC1: PC1 is timer1 etr input source SYSCON_TIM_ETR_PC2: PC2 is timer1 etr input source SYSCON_TIM_ETR_PD0: PD0 is timer1 etr input source SYSCON_TIM_ETR_PD7: PD7 is timer1 etr input source

## ◆ SYSCON_TIM2CH1IN_SEL

#define SYSCON_TIM2CH1IN_SEL | ( |  | SOURCE | ) |

值:
do { \
SYSCON_REGWR_UNLOCK(); \
MODIFY_REG(SYSCON->TIM2CR, SYSCON_TIM2CR_TIM2CH1IN_SEL, ((SOURCE) << SYSCON_TIM2CR_TIM2CH1IN_SEL_Pos)); \
SYSCON_REGWR_LOCK(); \
} while (0)
SYSCON_TIM2CR_TIM2CH1IN_SEL_Pos
#define SYSCON_TIM2CR_TIM2CH1IN_SEL_Pos
Definition: mg32l003.h:3220

Macro to select tim2 ch1 signal input source from gpio.

参数

  SOURCE | source for tim2 ch1 input This parameter can be one of the following values: SYSCON_DEFAULT: TIM2_CH1 alternate function is tim2 ch1 signal input source SYSCON_UART1_RXD: UART1_RXD alternate function is tim2 ch1 signal input source SYSCON_UART2_RXD: UART2_RXD alternate function is tim2 ch1 signal input source SYSCON_LPUART_RXD: LPUART_RXD alternate function is tim2 ch1 signal input source SYSCON_LSI: LSI is tim2 ch1 signal input source

## ◆ SYSCON_TIM2CH2IN_SEL

#define SYSCON_TIM2CH2IN_SEL | ( |  | SOURCE | ) |

值:
do { \
SYSCON_REGWR_UNLOCK(); \
MODIFY_REG(SYSCON->TIM2CR, SYSCON_TIM2CR_TIM2CH2IN_SEL, ((SOURCE) << SYSCON_TIM2CR_TIM2CH2IN_SEL_Pos)); \
SYSCON_REGWR_LOCK(); \
} while (0)
SYSCON_TIM2CR_TIM2CH2IN_SEL_Pos
#define SYSCON_TIM2CR_TIM2CH2IN_SEL_Pos
Definition: mg32l003.h:3223

Macro to select tim2 ch2 signal input source from gpio.

参数

  SOURCE | source for tim2 ch2 input This parameter can be one of the following values: SYSCON_DEFAULT: TIM2_CH2 alternate function is tim2 ch2 signal input source SYSCON_UART1_RXD: UART1_RXD alternate function is tim2 ch2 signal input source SYSCON_UART2_RXD: UART2_RXD alternate function is tim2 ch2 signal input source SYSCON_LPUART_RXD: LPUART_RXD alternate function is tim2 ch2 signal input source SYSCON_LSI: LSI is tim2 ch2 signal input source

## ◆ SYSCON_TIM2CH3IN_SEL

#define SYSCON_TIM2CH3IN_SEL | ( |  | SOURCE | ) |

值:
do { \
SYSCON_REGWR_UNLOCK(); \
MODIFY_REG(SYSCON->TIM2CR, SYSCON_TIM2CR_TIM2CH3IN_SEL, ((SOURCE) << SYSCON_TIM2CR_TIM2CH3IN_SEL_Pos)); \
SYSCON_REGWR_LOCK(); \
} while (0)
SYSCON_TIM2CR_TIM2CH3IN_SEL_Pos
#define SYSCON_TIM2CR_TIM2CH3IN_SEL_Pos
Definition: mg32l003.h:3226

Macro to select tim2 ch3 signal input source from gpio.

参数

  SOURCE | source for tim2 ch3 input This parameter can be one of the following values: SYSCON_DEFAULT: TIM2_CH3 alternate function is tim2 ch3 signal input source SYSCON_UART1_RXD: UART1_RXD alternate function is tim2 ch3 signal input source SYSCON_UART2_RXD: UART2_RXD alternate function is tim2 ch3 signal input source SYSCON_LPUART_RXD: LPUART_RXD alternate function is tim2 ch3 signal input source SYSCON_LSI: LSI is tim2 ch3 signal input source

## ◆ SYSCON_TIM2CH4IN_SEL

#define SYSCON_TIM2CH4IN_SEL | ( |  | SOURCE | ) |

值:
do { \
SYSCON_REGWR_UNLOCK(); \
MODIFY_REG(SYSCON->TIM2CR, SYSCON_TIM2CR_TIM2CH4IN_SEL, ((SOURCE) << SYSCON_TIM2CR_TIM2CH4IN_SEL_Pos)); \
SYSCON_REGWR_LOCK(); \
} while (0)
SYSCON_TIM2CR_TIM2CH4IN_SEL_Pos
#define SYSCON_TIM2CR_TIM2CH4IN_SEL_Pos
Definition: mg32l003.h:3229

Macro to select tim2 ch4 signal input source from gpio.

参数

  SOURCE | source for tim2 ch4 input This parameter can be one of the following values: SYSCON_DEFAULT: TIM2_CH4 alternate function is tim2 ch4 signal input source SYSCON_UART1_RXD: UART1_RXD alternate function is tim2 ch4 signal input source SYSCON_UART2_RXD: UART2_RXD alternate function is tim2 ch4 signal input source SYSCON_LPUART_RXD: LPUART_RXD alternate function is tim2 ch4 signal input source SYSCON_LSI: LSI is tim2 ch4 signal input source

## ◆ SYSCON_TIM2ETR_SEL

#define SYSCON_TIM2ETR_SEL | ( |  | SOURCE | ) |

值:
do { \
SYSCON_REGWR_UNLOCK(); \
MODIFY_REG(SYSCON->TIM2CR, SYSCON_TIM2CR_TIM2ETR_SEL, (SOURCE)); \
SYSCON_REGWR_LOCK(); \
} while (0)

Macro to select timer2 etr signal input source from gpio.

参数

  SOURCE | source for timer2 etr input This parameter can be one of the following values: SYSCON_TIM_ETR_LOWLEVEL: low level is timer2 etr input source SYSCON_TIM_ETR_PA1: PA1 is timer2 etr input source SYSCON_TIM_ETR_PA2: PA2 is timer2 etr input source SYSCON_TIM_ETR_PA3: PA3 is timer2 etr input source SYSCON_TIM_ETR_PB4: PB4 is timer2 etr input source SYSCON_TIM_ETR_PB5: PB5 is timer2 etr input source SYSCON_TIM_ETR_PC3: PC3 is timer2 etr input source SYSCON_TIM_ETR_PC4: PC4 is timer2 etr input source SYSCON_TIM_ETR_PC5: PC5 is timer2 etr input source SYSCON_TIM_ETR_PC6: PC6 is timer2 etr input source SYSCON_TIM_ETR_PC7: PC7 is timer2 etr input source SYSCON_TIM_ETR_PD1: PD1 is timer2 etr input source SYSCON_TIM_ETR_PD2: PD2 is timer2 etr input source SYSCON_TIM_ETR_PD3: PD3 is timer2 etr input source SYSCON_TIM_ETR_PD4: PD4 is timer2 etr input source SYSCON_TIM_ETR_PD6: PD6 is timer2 etr input source SYSCON_TIM_ETR_PA4: PA4 is timer2 etr input source SYSCON_TIM_ETR_PB0: PB0 is timer2 etr input source SYSCON_TIM_ETR_PB1: PB1 is timer2 etr input source SYSCON_TIM_ETR_PB2: PB2 is timer2 etr input source SYSCON_TIM_ETR_PB3: PB3 is timer2 etr input source SYSCON_TIM_ETR_PB6: PB6 is timer2 etr input source SYSCON_TIM_ETR_PB7: PB7 is timer2 etr input source SYSCON_TIM_ETR_PC0: PC0 is timer2 etr input source SYSCON_TIM_ETR_PC1: PC1 is timer2 etr input source SYSCON_TIM_ETR_PC2: PC2 is timer2 etr input source SYSCON_TIM_ETR_PD0: PD0 is timer2 etr input source SYSCON_TIM_ETR_PD7: PD7 is timer2 etr input source