MG32L003 Standard Peripherals Firmware Library
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Macros | |
#define | ADC_SINGLE_CHANNEL_0 (0x00000000U) |
#define | ADC_SINGLE_CHANNEL_1 (ADC_CR0_SEL_0) |
#define | ADC_SINGLE_CHANNEL_2 (ADC_CR0_SEL_1) |
#define | ADC_SINGLE_CHANNEL_3 (ADC_CR0_SEL_1 | ADC_CR0_SEL_0) |
#define | ADC_SINGLE_CHANNEL_4 (ADC_CR0_SEL_2) |
#define | ADC_SINGLE_CHANNEL_5 (ADC_CR0_SEL_2 | ADC_CR0_SEL_0) |
#define | ADC_SINGLE_CHANNEL_6 (ADC_CR0_SEL_2 | ADC_CR0_SEL_1) |
#define | ADC_SINGLE_CHANNEL_7 (ADC_CR0_SEL_2 | ADC_CR0_SEL_1 | ADC_CR0_SEL_0) |
#define | ADC_SINGLE_CHANNEL_8 (ADC_CR0_SEL_3) |
#define | ADC_SINGLE_CHANNEL_9 (ADC_CR0_SEL_3 | ADC_CR0_SEL_0) |
#define | ADC_SINGLE_CHANNEL_10 (ADC_CR0_SEL_3 | ADC_CR0_SEL_1) |
#define | ADC_SINGLE_CHANNEL_11 (ADC_CR0_SEL_3 | ADC_CR0_SEL_1 | ADC_CR0_SEL_0) |
#define | ADC_SINGLE_CHANNEL_12 (ADC_CR0_SEL_3 | ADC_CR0_SEL_2) |
#define | ADC_SINGLE_CHANNEL_13 (ADC_CR0_SEL_3 | ADC_CR0_SEL_2 | ADC_CR0_SEL_0) |
#define | ADC_SINGLE_CHANNEL_14 (ADC_CR0_SEL_3 | ADC_CR0_SEL_2 | ADC_CR0_SEL_1) |
#define | ADC_SINGLE_CHANNEL_15 (ADC_CR0_SEL_3 | ADC_CR0_SEL_2 | ADC_CR0_SEL_1 | ADC_CR0_SEL_0) |
#define | IS_ADC_SINGLE_CHANNEL(CHANNEL) |
#define ADC_SINGLE_CHANNEL_0 (0x00000000U) |
Select ADC channel 0 in single mode
#define ADC_SINGLE_CHANNEL_1 (ADC_CR0_SEL_0) |
Select ADC channel 1 in single mode
#define ADC_SINGLE_CHANNEL_10 (ADC_CR0_SEL_3 | ADC_CR0_SEL_1) |
Select ADC channel 10 in single mode
#define ADC_SINGLE_CHANNEL_11 (ADC_CR0_SEL_3 | ADC_CR0_SEL_1 | ADC_CR0_SEL_0) |
Select ADC channel 11 in single mode
#define ADC_SINGLE_CHANNEL_12 (ADC_CR0_SEL_3 | ADC_CR0_SEL_2) |
Select ADC channel 12 in single mode
#define ADC_SINGLE_CHANNEL_13 (ADC_CR0_SEL_3 | ADC_CR0_SEL_2 | ADC_CR0_SEL_0) |
Select ADC channel 13 in single mode
#define ADC_SINGLE_CHANNEL_14 (ADC_CR0_SEL_3 | ADC_CR0_SEL_2 | ADC_CR0_SEL_1) |
Select ADC channel 14 in single mode
#define ADC_SINGLE_CHANNEL_15 (ADC_CR0_SEL_3 | ADC_CR0_SEL_2 | ADC_CR0_SEL_1 | ADC_CR0_SEL_0) |
Select ADC channel 15 in single mode
#define ADC_SINGLE_CHANNEL_2 (ADC_CR0_SEL_1) |
Select ADC channel 2 in single mode
#define ADC_SINGLE_CHANNEL_3 (ADC_CR0_SEL_1 | ADC_CR0_SEL_0) |
Select ADC channel 3 in single mode
#define ADC_SINGLE_CHANNEL_4 (ADC_CR0_SEL_2) |
Select ADC channel 4 in single mode
#define ADC_SINGLE_CHANNEL_5 (ADC_CR0_SEL_2 | ADC_CR0_SEL_0) |
Select ADC channel 5 in single mode
#define ADC_SINGLE_CHANNEL_6 (ADC_CR0_SEL_2 | ADC_CR0_SEL_1) |
Select ADC channel 6 in single mode
#define ADC_SINGLE_CHANNEL_7 (ADC_CR0_SEL_2 | ADC_CR0_SEL_1 | ADC_CR0_SEL_0) |
Select ADC channel 7(VCAP) in single mode
#define ADC_SINGLE_CHANNEL_8 (ADC_CR0_SEL_3) |
Select ADC channel 8 in single mode
#define ADC_SINGLE_CHANNEL_9 (ADC_CR0_SEL_3 | ADC_CR0_SEL_0) |
Select ADC channel 9 in single mode
#define IS_ADC_SINGLE_CHANNEL | ( | CHANNEL | ) |