◆ HCLKDIV
RCC AHB clock prescale register, Address offset: 0x000
◆ HCLKEN
RCC AHB peripheral model clock enable register, Address offset: 0x008
◆ HSECR
RCC hse control register, Address offset: 0x02C
◆ HSICR
RCC hsi control register, Address offset: 0x028
◆ HSISTABCR
RCC register, Address offset: 0x390
◆ HSITC
RCC Internal high speed OSC control register 2, Address offset: 0x394
◆ IRQLATENCY
__IOM uint32_t IRQLATENCY |
RCC m0 irq delay register, Address offset: 0x038
◆ LSECR
RCC lse control register, Address offset: 0x034
◆ LSICR
RCC lsi control register, Address offset: 0x030
◆ LSITC
RCC register, Address offset: 0x398
◆ MCOCR
RCC clock output control register, Address offset: 0x010
◆ PCLKDIV
RCC apb clock prescale register, Address offset: 0x004
◆ PCLKEN
RCC apb peripheral model clock enable register, Address offset: 0x00C
◆ PERIRST
RCC peripheral model control register, Address offset: 0x044
◆ RESERVED0
◆ RESERVED1
__IM uint32_t RESERVED1[5] |
◆ RESERVED2
__IOM uint32_t RESERVED2[203] |
◆ RSTCR
RCC system reset control register, Address offset: 0x018
◆ RSTSR
RCC reset status register, Address offset: 0x01C
◆ RTCRST
RCC rtc control register, Address offset: 0x048
◆ STICKCR
RCC systick timer circle adjust register, Address offset: 0x03C
◆ SWDIOCR
RCC endpoint function select register, Address offset: 0x040
◆ SYSCLKCR
RCC clk setting register, Address offset: 0x020
◆ SYSCLKSEL
RCC system clock select register, Address offset: 0x024
◆ UNLOCK
RCC register protect register, Address offset: 0x060
The documentation for this struct was generated from the following file: