11 #ifndef __MG32L003_TIM_H 12 #define __MG32L003_TIM_H 154 #define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 158 #define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1)) 161 #define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1)) 164 #define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 168 #define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 172 #define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 176 #define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 180 #define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 184 #define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 188 #define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 195 #define TIM_OCMode_Timing ((uint16_t)0x0000) 196 #define TIM_OCMode_Active ((uint16_t)0x0010) 197 #define TIM_OCMode_Inactive ((uint16_t)0x0020) 198 #define TIM_OCMode_Toggle ((uint16_t)0x0030) 199 #define TIM_OCMode_PWM1 ((uint16_t)0x0060) 200 #define TIM_OCMode_PWM2 ((uint16_t)0x0070) 201 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ 202 ((MODE) == TIM_OCMode_Active) || \ 203 ((MODE) == TIM_OCMode_Inactive) || \ 204 ((MODE) == TIM_OCMode_Toggle)|| \ 205 ((MODE) == TIM_OCMode_PWM1) || \ 206 ((MODE) == TIM_OCMode_PWM2)) 207 #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ 208 ((MODE) == TIM_OCMode_Active) || \ 209 ((MODE) == TIM_OCMode_Inactive) || \ 210 ((MODE) == TIM_OCMode_Toggle)|| \ 211 ((MODE) == TIM_OCMode_PWM1) || \ 212 ((MODE) == TIM_OCMode_PWM2) || \ 213 ((MODE) == TIM_ForcedAction_Active) || \ 214 ((MODE) == TIM_ForcedAction_InActive)) 223 #define TIM_OPMode_Single ((uint16_t)0x0008) 224 #define TIM_OPMode_Repetitive ((uint16_t)0x0000) 225 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ 226 ((MODE) == TIM_OPMode_Repetitive)) 235 #define TIM_Channel_1 ((uint16_t)0x0000) 236 #define TIM_Channel_2 ((uint16_t)0x0004) 237 #define TIM_Channel_3 ((uint16_t)0x0008) 238 #define TIM_Channel_4 ((uint16_t)0x000C) 239 #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ 240 ((CHANNEL) == TIM_Channel_2) || \ 241 ((CHANNEL) == TIM_Channel_3) || \ 242 ((CHANNEL) == TIM_Channel_4)) 243 #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ 244 ((CHANNEL) == TIM_Channel_2)) 245 #define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ 246 ((CHANNEL) == TIM_Channel_2) || \ 247 ((CHANNEL) == TIM_Channel_3)) 256 #define TIM_CKD_DIV1 ((uint16_t)0x0000) 257 #define TIM_CKD_DIV2 ((uint16_t)0x0100) 258 #define TIM_CKD_DIV4 ((uint16_t)0x0200) 259 #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ 260 ((DIV) == TIM_CKD_DIV2) || \ 261 ((DIV) == TIM_CKD_DIV4)) 270 #define TIM_CounterMode_Up ((uint16_t)0x0000) 271 #define TIM_CounterMode_Down ((uint16_t)0x0010) 272 #define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) 273 #define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) 274 #define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) 275 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ 276 ((MODE) == TIM_CounterMode_Down) || \ 277 ((MODE) == TIM_CounterMode_CenterAligned1) || \ 278 ((MODE) == TIM_CounterMode_CenterAligned2) || \ 279 ((MODE) == TIM_CounterMode_CenterAligned3)) 288 #define TIM_OCPolarity_High ((uint16_t)0x0000) 289 #define TIM_OCPolarity_Low ((uint16_t)0x0002) 290 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ 291 ((POLARITY) == TIM_OCPolarity_Low)) 300 #define TIM_OCNPolarity_High ((uint16_t)0x0000) 301 #define TIM_OCNPolarity_Low ((uint16_t)0x0008) 302 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ 303 ((POLARITY) == TIM_OCNPolarity_Low)) 312 #define TIM_OutputState_Disable ((uint16_t)0x0000) 313 #define TIM_OutputState_Enable ((uint16_t)0x0001) 314 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ 315 ((STATE) == TIM_OutputState_Enable)) 324 #define TIM_OutputNState_Disable ((uint16_t)0x0000) 325 #define TIM_OutputNState_Enable ((uint16_t)0x0004) 326 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ 327 ((STATE) == TIM_OutputNState_Enable)) 336 #define TIM_CCx_Enable ((uint16_t)0x0001) 337 #define TIM_CCx_Disable ((uint16_t)0x0000) 338 #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ 339 ((CCX) == TIM_CCx_Disable)) 348 #define TIM_CCxN_Enable ((uint16_t)0x0004) 349 #define TIM_CCxN_Disable ((uint16_t)0x0000) 350 #define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ 351 ((CCXN) == TIM_CCxN_Disable)) 360 #define TIM_Break_Enable ((uint16_t)0x1000) 361 #define TIM_Break_Disable ((uint16_t)0x0000) 362 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ 363 ((STATE) == TIM_Break_Disable)) 372 #define TIM_BreakPolarity_Low ((uint16_t)0x0000) 373 #define TIM_BreakPolarity_High ((uint16_t)0x2000) 374 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ 375 ((POLARITY) == TIM_BreakPolarity_High)) 384 #define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) 385 #define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) 386 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ 387 ((STATE) == TIM_AutomaticOutput_Disable)) 396 #define TIM_LOCKLevel_OFF ((uint16_t)0x0000) 397 #define TIM_LOCKLevel_1 ((uint16_t)0x0100) 398 #define TIM_LOCKLevel_2 ((uint16_t)0x0200) 399 #define TIM_LOCKLevel_3 ((uint16_t)0x0300) 400 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ 401 ((LEVEL) == TIM_LOCKLevel_1) || \ 402 ((LEVEL) == TIM_LOCKLevel_2) || \ 403 ((LEVEL) == TIM_LOCKLevel_3)) 412 #define TIM_OSSIState_Enable ((uint16_t)0x0400) 413 #define TIM_OSSIState_Disable ((uint16_t)0x0000) 414 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ 415 ((STATE) == TIM_OSSIState_Disable)) 424 #define TIM_OSSRState_Enable ((uint16_t)0x0800) 425 #define TIM_OSSRState_Disable ((uint16_t)0x0000) 426 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ 427 ((STATE) == TIM_OSSRState_Disable)) 436 #define TIM_OCIdleState_Set ((uint16_t)0x0100) 437 #define TIM_OCIdleState_Reset ((uint16_t)0x0000) 438 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ 439 ((STATE) == TIM_OCIdleState_Reset)) 448 #define TIM_OCNIdleState_Set ((uint16_t)0x0200) 449 #define TIM_OCNIdleState_Reset ((uint16_t)0x0000) 450 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ 451 ((STATE) == TIM_OCNIdleState_Reset)) 460 #define TIM_ICPolarity_Rising ((uint16_t)0x0000) 461 #define TIM_ICPolarity_Falling ((uint16_t)0x0002) 462 #define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) 463 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ 464 ((POLARITY) == TIM_ICPolarity_Falling)) 465 #define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ 466 ((POLARITY) == TIM_ICPolarity_Falling)|| \ 467 ((POLARITY) == TIM_ICPolarity_BothEdge)) 475 #define TIM_ICSelection_DirectTI ((uint16_t)0x0001) 477 #define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) 479 #define TIM_ICSelection_TRC ((uint16_t)0x0003) 480 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ 481 ((SELECTION) == TIM_ICSelection_IndirectTI) || \ 482 ((SELECTION) == TIM_ICSelection_TRC)) 491 #define TIM_ICPSC_DIV1 ((uint16_t)0x0000) 492 #define TIM_ICPSC_DIV2 ((uint16_t)0x0004) 493 #define TIM_ICPSC_DIV4 ((uint16_t)0x0008) 494 #define TIM_ICPSC_DIV8 ((uint16_t)0x000C) 495 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ 496 ((PRESCALER) == TIM_ICPSC_DIV2) || \ 497 ((PRESCALER) == TIM_ICPSC_DIV4) || \ 498 ((PRESCALER) == TIM_ICPSC_DIV8)) 507 #define TIM_IT_Update ((uint16_t)0x0001) 508 #define TIM_IT_CC1 ((uint16_t)0x0002) 509 #define TIM_IT_CC2 ((uint16_t)0x0004) 510 #define TIM_IT_CC3 ((uint16_t)0x0008) 511 #define TIM_IT_CC4 ((uint16_t)0x0010) 512 #define TIM_IT_COM ((uint16_t)0x0020) 513 #define TIM_IT_Trigger ((uint16_t)0x0040) 514 #define TIM_IT_Break ((uint16_t)0x0080) 515 #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) 517 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ 518 ((IT) == TIM_IT_CC1) || \ 519 ((IT) == TIM_IT_CC2) || \ 520 ((IT) == TIM_IT_CC3) || \ 521 ((IT) == TIM_IT_CC4) || \ 522 ((IT) == TIM_IT_COM) || \ 523 ((IT) == TIM_IT_Trigger) || \ 524 ((IT) == TIM_IT_Break)) 533 #define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) 534 #define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) 535 #define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) 536 #define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) 537 #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ 538 ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ 539 ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ 540 ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) 549 #define TIM_TS_ITR0 ((uint16_t)0x0000) 550 #define TIM_TS_ITR1 ((uint16_t)0x0010) 551 #define TIM_TS_ITR2 ((uint16_t)0x0020) 552 #define TIM_TS_ITR3 ((uint16_t)0x0030) 553 #define TIM_TS_TI1F_ED ((uint16_t)0x0040) 554 #define TIM_TS_TI1FP1 ((uint16_t)0x0050) 555 #define TIM_TS_TI2FP2 ((uint16_t)0x0060) 556 #define TIM_TS_ETRF ((uint16_t)0x0070) 557 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ 558 ((SELECTION) == TIM_TS_ITR1) || \ 559 ((SELECTION) == TIM_TS_ITR2) || \ 560 ((SELECTION) == TIM_TS_ITR3) || \ 561 ((SELECTION) == TIM_TS_TI1F_ED) || \ 562 ((SELECTION) == TIM_TS_TI1FP1) || \ 563 ((SELECTION) == TIM_TS_TI2FP2) || \ 564 ((SELECTION) == TIM_TS_ETRF)) 565 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ 566 ((SELECTION) == TIM_TS_ITR1) || \ 567 ((SELECTION) == TIM_TS_ITR2) || \ 568 ((SELECTION) == TIM_TS_ITR3)) 577 #define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) 578 #define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) 579 #define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) 580 #define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \ 581 ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \ 582 ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED)) 590 #define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) 591 #define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) 592 #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ 593 ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) 602 #define TIM_PSCReloadMode_Update ((uint16_t)0x0000) 603 #define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) 604 #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ 605 ((RELOAD) == TIM_PSCReloadMode_Immediate)) 614 #define TIM_ForcedAction_Active ((uint16_t)0x0050) 615 #define TIM_ForcedAction_InActive ((uint16_t)0x0040) 616 #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ 617 ((ACTION) == TIM_ForcedAction_InActive)) 626 #define TIM_EncoderMode_TI1 ((uint16_t)0x0001) 627 #define TIM_EncoderMode_TI2 ((uint16_t)0x0002) 628 #define TIM_EncoderMode_TI12 ((uint16_t)0x0003) 629 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ 630 ((MODE) == TIM_EncoderMode_TI2) || \ 631 ((MODE) == TIM_EncoderMode_TI12)) 640 #define TIM_EventSource_Update ((uint16_t)0x0001) 641 #define TIM_EventSource_CC1 ((uint16_t)0x0002) 642 #define TIM_EventSource_CC2 ((uint16_t)0x0004) 643 #define TIM_EventSource_CC3 ((uint16_t)0x0008) 644 #define TIM_EventSource_CC4 ((uint16_t)0x0010) 645 #define TIM_EventSource_COM ((uint16_t)0x0020) 646 #define TIM_EventSource_Trigger ((uint16_t)0x0040) 647 #define TIM_EventSource_Break ((uint16_t)0x0080) 648 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) 657 #define TIM_UpdateSource_Global ((uint16_t)0x0000) 660 #define TIM_UpdateSource_Regular ((uint16_t)0x0001) 661 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ 662 ((SOURCE) == TIM_UpdateSource_Regular)) 671 #define TIM_OCPreload_Enable ((uint16_t)0x0008) 672 #define TIM_OCPreload_Disable ((uint16_t)0x0000) 673 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ 674 ((STATE) == TIM_OCPreload_Disable)) 683 #define TIM_OCFast_Enable ((uint16_t)0x0004) 684 #define TIM_OCFast_Disable ((uint16_t)0x0000) 685 #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ 686 ((STATE) == TIM_OCFast_Disable)) 695 #define TIM_OCClear_Enable ((uint16_t)0x0080) 696 #define TIM_OCClear_Disable ((uint16_t)0x0000) 697 #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ 698 ((STATE) == TIM_OCClear_Disable)) 706 #define TIM_TRGOSource_Reset ((uint16_t)0x0000) 707 #define TIM_TRGOSource_Enable ((uint16_t)0x0010) 708 #define TIM_TRGOSource_Update ((uint16_t)0x0020) 709 #define TIM_TRGOSource_OC1 ((uint16_t)0x0030) 710 #define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) 711 #define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) 712 #define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) 713 #define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) 714 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ 715 ((SOURCE) == TIM_TRGOSource_Enable) || \ 716 ((SOURCE) == TIM_TRGOSource_Update) || \ 717 ((SOURCE) == TIM_TRGOSource_OC1) || \ 718 ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ 719 ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ 720 ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ 721 ((SOURCE) == TIM_TRGOSource_OC4Ref)) 730 #define TIM_SlaveMode_Reset ((uint16_t)0x0004) 731 #define TIM_SlaveMode_Gated ((uint16_t)0x0005) 732 #define TIM_SlaveMode_Trigger ((uint16_t)0x0006) 733 #define TIM_SlaveMode_External1 ((uint16_t)0x0007) 734 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ 735 ((MODE) == TIM_SlaveMode_Gated) || \ 736 ((MODE) == TIM_SlaveMode_Trigger) || \ 737 ((MODE) == TIM_SlaveMode_External1)) 746 #define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) 747 #define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) 748 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ 749 ((STATE) == TIM_MasterSlaveMode_Disable)) 758 #define TIM_FLAG_Update ((uint16_t)0x0001) 759 #define TIM_FLAG_CC1 ((uint16_t)0x0002) 760 #define TIM_FLAG_CC2 ((uint16_t)0x0004) 761 #define TIM_FLAG_CC3 ((uint16_t)0x0008) 762 #define TIM_FLAG_CC4 ((uint16_t)0x0010) 763 #define TIM_FLAG_COM ((uint16_t)0x0020) 764 #define TIM_FLAG_Trigger ((uint16_t)0x0040) 765 #define TIM_FLAG_Break ((uint16_t)0x0080) 766 #define TIM_FLAG_CC1OF ((uint16_t)0x0200) 767 #define TIM_FLAG_CC2OF ((uint16_t)0x0400) 768 #define TIM_FLAG_CC3OF ((uint16_t)0x0800) 769 #define TIM_FLAG_CC4OF ((uint16_t)0x1000) 770 #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ 771 ((FLAG) == TIM_FLAG_CC1) || \ 772 ((FLAG) == TIM_FLAG_CC2) || \ 773 ((FLAG) == TIM_FLAG_CC3) || \ 774 ((FLAG) == TIM_FLAG_CC4) || \ 775 ((FLAG) == TIM_FLAG_COM) || \ 776 ((FLAG) == TIM_FLAG_Trigger) || \ 777 ((FLAG) == TIM_FLAG_Break) || \ 778 ((FLAG) == TIM_FLAG_CC1OF) || \ 779 ((FLAG) == TIM_FLAG_CC2OF) || \ 780 ((FLAG) == TIM_FLAG_CC3OF) || \ 781 ((FLAG) == TIM_FLAG_CC4OF)) 784 #define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) 793 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) 802 #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) 835 uint16_t TIM_ICPolarity, uint16_t ICFilter);
837 uint16_t ExtTRGFilter);
839 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
841 uint16_t ExtTRGFilter);
846 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
uint16_t TIM_Break
Definition: mg32l003_tim.h:138
uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 4 value.
Definition: mg32l003_tim.c:2260
void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIMx's Hall sensor interface.
Definition: mg32l003_tim.c:1912
void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIM peripheral Main Outputs.
Definition: mg32l003_tim.c:694
uint16_t TIM_BreakPolarity
Definition: mg32l003_tim.h:141
void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3)
Sets the TIMx Capture Compare3 Register value.
Definition: mg32l003_tim.c:2084
void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the specified TIM peripheral.
Definition: mg32l003_tim.c:669
uint16_t TIM_DeadTime
Definition: mg32l003_tim.h:134
void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF4 signal on an external event.
Definition: mg32l003_tim.c:1550
void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 3 Fast feature.
Definition: mg32l003_tim.c:1426
uint16_t TIM_Prescaler
Definition: mg32l003_tim.h:36
uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx)
Gets the TIMx Prescaler value.
Definition: mg32l003_tim.c:2286
void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 2 prescaler.
Definition: mg32l003_tim.c:2139
void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 3 prescaler.
Definition: mg32l003_tim.c:2161
void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 3 polarity.
Definition: mg32l003_tim.c:1668
uint16_t TIM_ICPolarity
Definition: mg32l003_tim.h:104
uint16_t TIM_OSSRState
Definition: mg32l003_tim.h:125
void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct)
Fills each TIM_OCInitStruct member with its default value.
Definition: mg32l003_tim.c:615
void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct.
Definition: mg32l003_tim.c:308
void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF1 signal on an external event.
Definition: mg32l003_tim.c:1476
void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode)
Selects the TIMx's One Pulse Mode.
Definition: mg32l003_tim.c:1938
void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter)
Sets the TIMx Counter Register value.
Definition: mg32l003_tim.c:2028
void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR3.
Definition: mg32l003_tim.c:1327
void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 2N polarity.
Definition: mg32l003_tim.c:1644
void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Configures the TIMx Internal Trigger as External Clock.
Definition: mg32l003_tim.c:802
void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIM peripheral Commutation event.
Definition: mg32l003_tim.c:1227
void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1)
Sets the TIMx Capture Compare1 Register value.
Definition: mg32l003_tim.c:2056
void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 4 Fast feature.
Definition: mg32l003_tim.c:1451
void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 3 waveform to active or inactive level.
Definition: mg32l003_tim.c:1157
void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
Definition: mg32l003_tim.c:942
void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables TIMx peripheral Preload register on ARR.
Definition: mg32l003_tim.c:1203
void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
Enables or disables the TIM Capture Compare Channel x.
Definition: mg32l003_tim.c:1743
void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode2.
Definition: mg32l003_tim.c:911
void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 2 waveform to active or inactive level.
Definition: mg32l003_tim.c:1133
void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
Configures the TIMx Prescaler.
Definition: mg32l003_tim.c:970
uint16_t TIM_OCNPolarity
Definition: mg32l003_tim.h:81
uint16_t TIM_OCNIdleState
Definition: mg32l003_tim.h:89
void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct.
Definition: mg32l003_tim.c:144
uint16_t TIM_ClockDivision
Definition: mg32l003_tim.h:46
void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel2 according to the specified parameters in the TIM_OCInitStruct.
Definition: mg32l003_tim.c:226
void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct)
Fills each TIM_ICInitStruct member with its default value.
Definition: mg32l003_tim.c:634
uint16_t TIM_ICPrescaler
Definition: mg32l003_tim.h:110
void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode1.
Definition: mg32l003_tim.c:869
void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or Disables the TIMx Update event.
Definition: mg32l003_tim.c:1861
void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 1 waveform to active or inactive level.
Definition: mg32l003_tim.c:1109
void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct.
Definition: mg32l003_tim.c:451
uint16_t TIM_OSSIState
Definition: mg32l003_tim.h:128
void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Clears the TIMx's pending flags.
Definition: mg32l003_tim.c:2358
uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 3 value.
Definition: mg32l003_tim.c:2247
void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 4 prescaler.
Definition: mg32l003_tim.c:2183
void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF3 signal on an external event.
Definition: mg32l003_tim.c:1526
TIM Output Compare Init structure definition.
Definition: mg32l003_tim.h:63
void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
Configures the: Break feature, dead time, Lock level, the OSSI, the OSSR State and the AOE(automatic ...
Definition: mg32l003_tim.c:575
uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 2 value.
Definition: mg32l003_tim.c:2234
TIM Time Base Init structure definition.
Definition: mg32l003_tim.h:34
void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState)
Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
Definition: mg32l003_tim.c:1252
void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode)
Sets or Resets the TIMx Master/Slave Mode.
Definition: mg32l003_tim.c:2010
void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF2 signal on an external event.
Definition: mg32l003_tim.c:1502
void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4)
Sets the TIMx Capture Compare4 Register value.
Definition: mg32l003_tim.c:2098
FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Checks whether the specified TIM flag is set or not.
Definition: mg32l003_tim.c:2317
void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
Configures the TIMx Encoder Interface.
Definition: mg32l003_tim.c:1058
void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 1 prescaler.
Definition: mg32l003_tim.c:2117
void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD)
Sets the TIMx Clock Division value.
Definition: mg32l003_tim.c:2205
Definition: mg32l003.h:480
uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 1 value.
Definition: mg32l003_tim.c:2221
void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR1.
Definition: mg32l003_tim.c:1278
uint16_t TIM_Channel
Definition: mg32l003_tim.h:101
void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
Selects the TIM Output Compare Mode.
Definition: mg32l003_tim.c:1814
void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT)
Clears the TIMx's interrupt pending bits.
Definition: mg32l003_tim.c:2428
void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 1N polarity.
Definition: mg32l003_tim.c:1597
uint16_t TIM_Period
Definition: mg32l003_tim.h:42
void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2)
Sets the TIMx Capture Compare2 Register value.
Definition: mg32l003_tim.c:2070
uint16_t TIM_OCMode
Definition: mg32l003_tim.h:65
void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload)
Sets the TIMx Autoreload Register value.
Definition: mg32l003_tim.c:2042
void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource)
Configures the TIMx event to be generate by software.
Definition: mg32l003_tim.c:767
uint16_t TIM_LOCKLevel
Definition: mg32l003_tim.h:131
uint16_t TIM_ICSelection
Definition: mg32l003_tim.h:107
void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource)
Configures the TIMx Update Request Interrupt source.
Definition: mg32l003_tim.c:1888
uint16_t TIM_OCPolarity
Definition: mg32l003_tim.h:78
void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 1 polarity.
Definition: mg32l003_tim.c:1574
void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 4 polarity.
Definition: mg32l003_tim.c:1716
void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter)
Configures the TIMx Trigger as External Clock.
Definition: mg32l003_tim.c:829
void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode)
Specifies the TIMx Counter Mode to be used.
Definition: mg32l003_tim.c:993
void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Initializes the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_TimeB...
Definition: mg32l003_tim.c:95
void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
Enables or disables the TIM Capture Compare Channel xN.
Definition: mg32l003_tim.c:1773
ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT)
Checks whether the TIM interrupt has occurred or not.
Definition: mg32l003_tim.c:2387
void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 4 waveform to active or inactive level.
Definition: mg32l003_tim.c:1181
void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Selects the Input Trigger source.
Definition: mg32l003_tim.c:1023
TIM Input Capture Init structure definition.
Definition: mg32l003_tim.h:98
void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode)
Selects the TIMx Slave Mode.
Definition: mg32l003_tim.c:1989
void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
Fills each TIM_BDTRInitStruct member with its default value.
Definition: mg32l003_tim.c:650
void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 2 polarity.
Definition: mg32l003_tim.c:1621
uint16_t TIM_Pulse
Definition: mg32l003_tim.h:75
void TIM_DeInit(TIM_TypeDef *TIMx)
Deinitializes the TIMx peripheral registers to their default reset values.
Definition: mg32l003_tim.c:69
uint16_t TIM_OutputState
Definition: mg32l003_tim.h:68
void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 1 Fast feature.
Definition: mg32l003_tim.c:1375
uint16_t TIM_OCIdleState
Definition: mg32l003_tim.h:85
uint16_t TIM_AutomaticOutput
Definition: mg32l003_tim.h:144
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Fills each TIM_TimeBaseInitStruct member with its default value.
Definition: mg32l003_tim.c:599
void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState)
Enables or disables the specified TIM interrupts.
Definition: mg32l003_tim.c:732
void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource)
Selects the TIMx Trigger Output Mode.
Definition: mg32l003_tim.c:1966
uint16_t TIM_CounterMode
Definition: mg32l003_tim.h:39
void TIM_InternalClockConfig(TIM_TypeDef *TIMx)
Configures the TIMx internal Clock.
Definition: mg32l003_tim.c:783
void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR2.
Definition: mg32l003_tim.c:1303
void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 2 Fast feature.
Definition: mg32l003_tim.c:1401
uint16_t TIM_OutputNState
Definition: mg32l003_tim.h:71
uint16_t TIM_GetCounter(TIM_TypeDef *TIMx)
Gets the TIMx Counter value.
Definition: mg32l003_tim.c:2273
uint16_t TIM_ICFilter
Definition: mg32l003_tim.h:113
void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR4.
Definition: mg32l003_tim.c:1351
void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 3N polarity.
Definition: mg32l003_tim.c:1691
BDTR structure definition.
Definition: mg32l003_tim.h:122
uint8_t TIM_RepetitionCounter
Definition: mg32l003_tim.h:49
void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measur...
Definition: mg32l003_tim.c:517
void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel4 according to the specified parameters in the TIM_OCInitStruct.
Definition: mg32l003_tim.c:387