◆ CFGR0
SYSCON setting register 0, Address offset: 0x000
◆ PCACR
SYSCON pca capture channel source select register, Address offset: 0x00C
◆ PORTCR
SYSCON port control register, Address offset: 0x008
◆ PORTINTCR
SYSCON port interrupt mode setting register, Address offset: 0x004
◆ RESERVED0
__IM uint32_t RESERVED0[14] |
◆ TIM1CR
SYSCON tim1 channel source select register, Address offset: 0x010
◆ TIM2CR
SYSCON tim2 channel source select register, Address offset: 0x014
◆ UNLOCK
SYSCON write enable register, Address offset: 0x050
The documentation for this struct was generated from the following file: