MG32L003 Standard Peripherals Firmware Library
mg32l003_syscon.h
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1 
10 /* Define to prevent recursive inclusion -------------------------------------*/
11 #ifndef __MG32L003_SYSCON_H
12 #define __MG32L003_SYSCON_H
13 
14 #ifdef __cplusplus
15  extern "C" {
16 #endif
17 
18 /* Includes ------------------------------------------------------------------*/
19 #include "mg32l003.h"
20 
30 /* Exported types ------------------------------------------------------------*/
31 /* Exported constants --------------------------------------------------------*/
32 
37 #define SYSCON_KEY_UNLOCK (0x5A69)
38 
39 #define SYSCON_DEFAULT (0x00U)
40 #define SYSCON_UART1_RXD (0x01U)
41 #define SYSCON_UART2_RXD (0x02U)
42 #define SYSCON_LPUART_RXD (0x03U)
43 #define SYSCON_LSI (0x04U)
44 
45 #define SYSCON_SPINCS_SEL_0 (0x01U << 0)
46 #define SYSCON_SPINCS_SEL_1 (0x01U << 1)
47 #define SYSCON_SPINCS_SEL_2 (0x01U << 2)
48 #define SYSCON_SPINCS_SEL_3 (0x01U << 3)
49 #define SYSCON_SPINCS_SEL_4 (0x01U << 10)
50 
51 #define SYSCON_TIMETR_SEL_0 (0x01U << 16)
52 #define SYSCON_TIMETR_SEL_1 (0x01U << 17)
53 #define SYSCON_TIMETR_SEL_2 (0x01U << 18)
54 #define SYSCON_TIMETR_SEL_3 (0x01U << 19)
55 #define SYSCON_TIMETR_SEL_4 (0x01U << 23)
56 
57 #define SYSCON_TIM_ETR_LOWLEVEL (0x00000000U)
58 #define SYSCON_TIM_ETR_PA1 (SYSCON_TIMETR_SEL_0)
59 #define SYSCON_TIM_ETR_PA2 (SYSCON_TIMETR_SEL_1)
60 #define SYSCON_TIM_ETR_PA3 (SYSCON_TIMETR_SEL_1 | SYSCON_TIMETR_SEL_0)
61 #define SYSCON_TIM_ETR_PB4 (SYSCON_TIMETR_SEL_2)
62 #define SYSCON_TIM_ETR_PB5 (SYSCON_TIMETR_SEL_2 | SYSCON_TIMETR_SEL_0)
63 #define SYSCON_TIM_ETR_PC3 (SYSCON_TIMETR_SEL_2 | SYSCON_TIMETR_SEL_1)
64 #define SYSCON_TIM_ETR_PC4 (SYSCON_TIMETR_SEL_2 | SYSCON_TIMETR_SEL_1 | SYSCON_TIMETR_SEL_0)
65 #define SYSCON_TIM_ETR_PC5 (SYSCON_TIMETR_SEL_3)
66 #define SYSCON_TIM_ETR_PC6 (SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_0)
67 #define SYSCON_TIM_ETR_PC7 (SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_1)
68 #define SYSCON_TIM_ETR_PD1 (SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_1 | SYSCON_TIMETR_SEL_0)
69 #define SYSCON_TIM_ETR_PD2 (SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_2)
70 #define SYSCON_TIM_ETR_PD3 (SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_2 | SYSCON_TIMETR_SEL_0)
71 #define SYSCON_TIM_ETR_PD4 (SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_2 | SYSCON_TIMETR_SEL_1)
72 #define SYSCON_TIM_ETR_PD6 (SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_2 | SYSCON_TIMETR_SEL_1 | SYSCON_TIMETR_SEL_0)
73 #define SYSCON_TIM_ETR_PA4 (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_0)
74 #define SYSCON_TIM_ETR_PB0 (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_1)
75 #define SYSCON_TIM_ETR_PB1 (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_1 | SYSCON_TIMETR_SEL_0)
76 #define SYSCON_TIM_ETR_PB2 (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_2)
77 #define SYSCON_TIM_ETR_PB3 (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_2 | SYSCON_TIMETR_SEL_0)
78 #define SYSCON_TIM_ETR_PB6 (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_2 | SYSCON_TIMETR_SEL_1)
79 #define SYSCON_TIM_ETR_PB7 (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_2 | SYSCON_TIMETR_SEL_1 | SYSCON_TIMETR_SEL_0)
80 #define SYSCON_TIM_ETR_PC0 (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_3)
81 #define SYSCON_TIM_ETR_PC1 (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_0)
82 #define SYSCON_TIM_ETR_PC2 (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_1)
83 #define SYSCON_TIM_ETR_PD0 (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_1 | SYSCON_TIMETR_SEL_0)
84 #define SYSCON_TIM_ETR_PD7 (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_2)
85 
86 #define SYSCON_SPI_NCS_HIGHLEVEL (0x00000000U)
87 #define SYSCON_SPI_NCS_PA1 (SYSCON_SPINCS_SEL_0)
88 #define SYSCON_SPI_NCS_PA2 (SYSCON_SPINCS_SEL_1)
89 #define SYSCON_SPI_NCS_PA3 (SYSCON_SPINCS_SEL_1 | SYSCON_SPINCS_SEL_0)
90 #define SYSCON_SPI_NCS_PB4 (SYSCON_SPINCS_SEL_2)
91 #define SYSCON_SPI_NCS_PB5 (SYSCON_SPINCS_SEL_2 | SYSCON_SPINCS_SEL_0)
92 #define SYSCON_SPI_NCS_PC3 (SYSCON_SPINCS_SEL_2 | SYSCON_SPINCS_SEL_1)
93 #define SYSCON_SPI_NCS_PC4 (SYSCON_SPINCS_SEL_2 | SYSCON_SPINCS_SEL_1 | SYSCON_SPINCS_SEL_0)
94 #define SYSCON_SPI_NCS_PC5 (SYSCON_SPINCS_SEL_3)
95 #define SYSCON_SPI_NCS_PC6 (SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_0)
96 #define SYSCON_SPI_NCS_PC7 (SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_1)
97 #define SYSCON_SPI_NCS_PD1 (SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_1 | SYSCON_SPINCS_SEL_0)
98 #define SYSCON_SPI_NCS_PD2 (SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_2)
99 #define SYSCON_SPI_NCS_PD3 (SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_2 | SYSCON_SPINCS_SEL_0)
100 #define SYSCON_SPI_NCS_PD4 (SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_2 | SYSCON_SPINCS_SEL_1)
101 #define SYSCON_SPI_NCS_PD6 (SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_2 | SYSCON_SPINCS_SEL_1 | SYSCON_SPINCS_SEL_0)
102 #define SYSCON_SPI_NCS_PA4 (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_0)
103 #define SYSCON_SPI_NCS_PB0 (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_1)
104 #define SYSCON_SPI_NCS_PB1 (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_1 | SYSCON_SPINCS_SEL_0)
105 #define SYSCON_SPI_NCS_PB2 (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_2)
106 #define SYSCON_SPI_NCS_PB3 (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_2 | SYSCON_SPINCS_SEL_0)
107 #define SYSCON_SPI_NCS_PB6 (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_2 | SYSCON_SPINCS_SEL_1)
108 #define SYSCON_SPI_NCS_PB7 (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_2 | SYSCON_SPINCS_SEL_1 | SYSCON_SPINCS_SEL_0)
109 #define SYSCON_SPI_NCS_PC0 (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_3)
110 #define SYSCON_SPI_NCS_PC1 (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_0)
111 #define SYSCON_SPI_NCS_PC2 (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_1)
112 #define SYSCON_SPI_NCS_PD0 (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_1 | SYSCON_SPINCS_SEL_0)
113 #define SYSCON_SPI_NCS_PD7 (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_2)
114 
115 #define SYSCON_CLKFAILBRKEN SYSCON_TIM1CR_CLKFAILBRKEN
116 #define SYSCON_DSLPBRKEN SYSCON_TIM1CR_DSLPBRKEN
117 
118 #define SYSCON_OCOUT_LOWLEVEL SYSCON_TIM1CR_TIM1BRKOUTCFG
119 #define SYSCON_OCOUT_BYTIM1 (0x00U)
120 
125 /* Exported macro ------------------------------------------------------------*/
126 
127 #define SYSCON_REGWR_LOCK() (SYSCON->UNLOCK = (0x2AD5334C << SYSCON_UNLOCK_KEY_Pos) & SYSCON_UNLOCK_KEY)
128 #define SYSCON_REGWR_UNLOCK() (SYSCON->UNLOCK = SYSCON_UNLOCK_UNLOCK | (0x2AD5334C << SYSCON_UNLOCK_KEY_Pos))
129 
133 #define SYSCON_DBGDEEPSLEEP_ENABLE() \
134  do { \
135  SYSCON_REGWR_UNLOCK(); \
136  SET_BIT(SYSCON->CFGR0, SYSCON_CFGR0_DBGDLSP_DIS | (SYSCON_CFGR0_KEY << SYSCON_CFGR0_KEY_Pos)); \
137  SYSCON_REGWR_LOCK(); \
138  } while (0)
139 
143 #define SYSCON_DBGDEEPSLEEP_DISABLE() \
144  do { \
145  SYSCON_REGWR_UNLOCK(); \
146  CLEAR_WPBIT(SYSCON->CFGR0, SYSCON_CFGR0_DBGDLSP_DIS, (SYSCON_CFGR0_KEY << SYSCON_CFGR0_KEY_Pos)); \
147  SYSCON_REGWR_LOCK(); \
148  } while (0)
149 
152 #define SYSCON_LOCKUP_ENABLE() \
153  do { \
154  SYSCON_REGWR_UNLOCK(); \
155  SET_BIT(SYSCON->CFGR0, SYSCON_CFGR0_LOCKUPEN | (SYSCON_CFGR0_KEY << SYSCON_CFGR0_KEY_Pos)); \
156  SYSCON_REGWR_LOCK(); \
157  } while (0)
158 
161 #define SYSCON_LOCKUP_DISABLE() \
162  do { \
163  SYSCON_REGWR_UNLOCK(); \
164  CLEAR_WPBIT(SYSCON->CFGR0, SYSCON_CFGR0_LOCKUPEN, (SYSCON_CFGR0_KEY << SYSCON_CFGR0_KEY_Pos)); \
165  SYSCON_REGWR_LOCK(); \
166  } while (0)
167 
170 #define SYSCON_DEEPSLEEP_PADINT_AUTO() \
171  do { \
172  SYSCON_REGWR_UNLOCK(); \
173  CLEAR_WPBIT(SYSCON->PORTINTCR, SYSCON_PORTINTCR_PADDLSPCON, (SYSCON_UNLOCK_KEY << SYSCON_PORTINTCR_KEY_Pos)); \
174  SYSCON_REGWR_LOCK(); \
175  } while (0)
176 
179 #define SYSCON_DEEPSLEEP_PADINT_ACTIVE() \
180  do { \
181  SYSCON_REGWR_UNLOCK(); \
182  SET_BIT(SYSCON->PORTINTCR, SYSCON_PORTINTCR_PADDLSPCON | (SYSCON_UNLOCK_KEY << SYSCON_PORTINTCR_KEY_Pos)); \
183  CLEAR_WPBIT(SYSCON->PORTINTCR, SYSCON_PORTINTCR_PADINTSEL, (SYSCON_UNLOCK_KEY << SYSCON_PORTINTCR_KEY_Pos)); \
184  SYSCON_REGWR_LOCK(); \
185  } while (0)
186 
195 #define SYSCON_LPTIM_GATE(SOURCE) \
196  do { \
197  SYSCON_REGWR_UNLOCK(); \
198  MODIFY_REG(SYSCON->PORTCR, SYSCON_PORTCR_LPTIM_GATE_SEL, ((SOURCE) << SYSCON_PORTCR_LPTIM_GATE_SEL_Pos)); \
199  SYSCON_REGWR_UNLOCK(); \
200  } while (0)
201 
210 #define SYSCON_TIM11_GATE(SOURCE) \
211  do { \
212  SYSCON_REGWR_UNLOCK(); \
213  MODIFY_REG(SYSCON->PORTCR, SYSCON_PORTCR_TIM11_GATE_SEL, ((SOURCE) << SYSCON_PORTCR_TIM11_GATE_SEL_Pos)); \
214  SYSCON_REGWR_LOCK(); \
215  } while (0)
216 
225 #define SYSCON_TIM10_GATE(SOURCE) \
226  do { \
227  SYSCON_REGWR_UNLOCK(); \
228  MODIFY_REG(SYSCON->PORTCR, SYSCON_PORTCR_TIM10_GATE_SEL, ((SOURCE) << SYSCON_PORTCR_TIM10_GATE_SEL_Pos)); \
229  SYSCON_REGWR_LOCK(); \
230  } while (0)
231 
264 #define SYSCON_SPINCS(SOURCE) \
265  do { \
266  SYSCON_REGWR_UNLOCK(); \
267  MODIFY_REG(SYSCON->PORTCR, SYSCON_PORTCR_SPINCS_SEL, (SOURCE)); \
268  SYSCON_REGWR_LOCK(); \
269  } while (0)
270 
279 #define SYSCON_PCA_CAP4(SOURCE) \
280  do { \
281  SYSCON_REGWR_UNLOCK(); \
282  MODIFY_REG(SYSCON->PCACR, SYSCON_PCACR_PCA_CAP4_SEL, ((SOURCE) << SYSCON_PCACR_PCA_CAP4_SEL_Pos)); \
283  SYSCON_REGWR_LOCK(); \
284  } while (0)
285 
294 #define SYSCON_PCA_CAP3(SOURCE) \
295  do { \
296  SYSCON_REGWR_UNLOCK(); \
297  MODIFY_REG(SYSCON->PCACR, SYSCON_PCACR_PCA_CAP3_SEL, ((SOURCE) << SYSCON_PCACR_PCA_CAP3_SEL_Pos)); \
298  SYSCON_REGWR_LOCK(); \
299  } while (0)
300 
309 #define SYSCON_PCA_CAP2(SOURCE) \
310  do { \
311  SYSCON_REGWR_UNLOCK(); \
312  MODIFY_REG(SYSCON->PCACR, SYSCON_PCACR_PCA_CAP2_SEL, ((SOURCE) << SYSCON_PCACR_PCA_CAP2_SEL_Pos)); \
313  SYSCON_REGWR_LOCK(); \
314  } while (0)
315 
324 #define SYSCON_PCA_CAP1(SOURCE) \
325  do { \
326  SYSCON_REGWR_UNLOCK(); \
327  MODIFY_REG(SYSCON->PCACR, SYSCON_PCACR_PCA_CAP1_SEL, ((SOURCE) << SYSCON_PCACR_PCA_CAP1_SEL_Pos)); \
328  SYSCON_REGWR_LOCK(); \
329  } while (0)
330 
339 #define SYSCON_PCA_CAP0(SOURCE) \
340  do { \
341  SYSCON_REGWR_UNLOCK(); \
342  MODIFY_REG(SYSCON->PCACR, SYSCON_PCACR_PCA_CAP0_SEL, ((SOURCE) << SYSCON_PCACR_PCA_CAP0_SEL_Pos)); \
343  SYSCON_REGWR_LOCK(); \
344  } while (0)
345 
352 #define SYSCON_TIM1_BREAKIN_SEL(SOURCE) \
353  do { \
354  SYSCON_REGWR_UNLOCK(); \
355  MODIFY_REG(SYSCON->TIM1CR, SYSCON_TIM1CR_CLKFAILBRKEN | SYSCON_TIM1CR_DSLPBRKEN, (SOURCE)); \
356  SYSCON_REGWR_LOCK(); \
357  } while (0)
358 
365 #define SYSCON_TIM1_BREAKOUT_CFG(CONFIG) \
366  do { \
367  SYSCON_REGWR_UNLOCK(); \
368  MODIFY_REG(SYSCON->TIM1CR, SYSCON_TIM1CR_TIM1BRKOUTCFG, (CONFIG)); \
369  SYSCON_REGWR_LOCK(); \
370  } while (0)
371 
404 #define SYSCON_TIM1ETR_SEL(SOURCE) \
405  do { \
406  SYSCON_REGWR_UNLOCK(); \
407  MODIFY_REG(SYSCON->TIM1CR, SYSCON_TIM1CR_TIM1ETR_SEL, (SOURCE)); \
408  SYSCON_REGWR_LOCK(); \
409  } while (0)
410 
420 #define SYSCON_TIM1CH4IN_SEL(SOURCE) \
421  do { \
422  SYSCON_REGWR_UNLOCK(); \
423  MODIFY_REG(SYSCON->TIM1CR, SYSCON_TIM1CR_TIM1CH4IN_SEL, ((SOURCE) << SYSCON_TIM1CR_TIM1CH4IN_SEL_Pos)); \
424  SYSCON_REGWR_LOCK(); \
425  } while (0)
426 
436 #define SYSCON_TIM1CH3IN_SEL(SOURCE) \
437  do { \
438  SYSCON_REGWR_UNLOCK(); \
439  MODIFY_REG(SYSCON->TIM1CR, SYSCON_TIM1CR_TIM1CH3IN_SEL, ((SOURCE) << SYSCON_TIM1CR_TIM1CH3IN_SEL_Pos)); \
440  SYSCON_REGWR_LOCK(); \
441  } while (0)
442 
452 #define SYSCON_TIM1CH2IN_SEL(SOURCE) \
453  do { \
454  SYSCON_REGWR_UNLOCK(); \
455  MODIFY_REG(SYSCON->TIM1CR, SYSCON_TIM1CR_TIM1CH2IN_SEL, ((SOURCE) << SYSCON_TIM1CR_TIM1CH2IN_SEL_Pos)); \
456  SYSCON_REGWR_LOCK(); \
457  } while (0)
458 
468 #define SYSCON_TIM1CH1IN_SEL(SOURCE) \
469  do { \
470  SYSCON_REGWR_UNLOCK(); \
471  MODIFY_REG(SYSCON->TIM1CR, SYSCON_TIM1CR_TIM1CH1IN_SEL, ((SOURCE) << SYSCON_TIM1CR_TIM1CH1IN_SEL_Pos)); \
472  SYSCON_REGWR_LOCK(); \
473  } while (0)
474 
507 #define SYSCON_TIM2ETR_SEL(SOURCE) \
508  do { \
509  SYSCON_REGWR_UNLOCK(); \
510  MODIFY_REG(SYSCON->TIM2CR, SYSCON_TIM2CR_TIM2ETR_SEL, (SOURCE)); \
511  SYSCON_REGWR_LOCK(); \
512  } while (0)
513 
523 #define SYSCON_TIM2CH4IN_SEL(SOURCE) \
524  do { \
525  SYSCON_REGWR_UNLOCK(); \
526  MODIFY_REG(SYSCON->TIM2CR, SYSCON_TIM2CR_TIM2CH4IN_SEL, ((SOURCE) << SYSCON_TIM2CR_TIM2CH4IN_SEL_Pos)); \
527  SYSCON_REGWR_LOCK(); \
528  } while (0)
529 
539 #define SYSCON_TIM2CH3IN_SEL(SOURCE) \
540  do { \
541  SYSCON_REGWR_UNLOCK(); \
542  MODIFY_REG(SYSCON->TIM2CR, SYSCON_TIM2CR_TIM2CH3IN_SEL, ((SOURCE) << SYSCON_TIM2CR_TIM2CH3IN_SEL_Pos)); \
543  SYSCON_REGWR_LOCK(); \
544  } while (0)
545 
555 #define SYSCON_TIM2CH2IN_SEL(SOURCE) \
556  do { \
557  SYSCON_REGWR_UNLOCK(); \
558  MODIFY_REG(SYSCON->TIM2CR, SYSCON_TIM2CR_TIM2CH2IN_SEL, ((SOURCE) << SYSCON_TIM2CR_TIM2CH2IN_SEL_Pos)); \
559  SYSCON_REGWR_LOCK(); \
560  } while (0)
561 
571 #define SYSCON_TIM2CH1IN_SEL(SOURCE) \
572  do { \
573  SYSCON_REGWR_UNLOCK(); \
574  MODIFY_REG(SYSCON->TIM2CR, SYSCON_TIM2CR_TIM2CH1IN_SEL, ((SOURCE) << SYSCON_TIM2CR_TIM2CH1IN_SEL_Pos)); \
575  SYSCON_REGWR_LOCK(); \
576  } while (0)
577 
578 /* Exported functions --------------------------------------------------------*/
579 
588 #ifdef __cplusplus
589 }
590 #endif
591 
592 #endif /*__MG32L003_SYSCON_H */