◆ AFR
GPIO multiplex function register, Address offset: 0x048
◆ DBCLKCR
GPIO input debounce clock config register, Address offset: 0x038
◆ DIRCR
GPIO input output model register, Address offset: 0x000
◆ DRVCR
GPIO driver strength config register, Address offset: 0x044
◆ IDR
GPIO input data register, Address offset: 0x00C
◆ INDBEN
GPIO input debounce and synchronous enable register, Address offset: 0x034
◆ INTANY
GPIO edge trigger interrupt register, Address offset: 0x028
◆ INTCLR
GPIO interrupt clear register, Address offset: 0x01C
◆ INTEN
GPIO inerrupt enable register, Address offset: 0x010
◆ INTPOLCR
GPIO interrupt sytle value register, Address offset: 0x024
◆ INTTYPCR
GPIO interrupt style register, Address offset: 0x020
◆ MSKINTSR
GPIO interrupt status register, Address offset: 0x018
◆ ODCLR
GPIO output clear register, Address offset: 0x030
◆ ODR
GPIO output data register, Address offset: 0x008
◆ ODSET
GPIO output setting register, Address offset: 0x02C
◆ OTYPER
GPIO output type register, Address offset: 0x004
◆ PUPDR
GPIO pullup and pulldown register, Address offset: 0x03C
◆ RAWINTST
GPIO interrupt raw status register, Address offset: 0x014
◆ SLEWCR
GPIO voltage convertion speed control register, Address offset: 0x040
The documentation for this struct was generated from the following file: