MG32L003 Standard Peripherals Firmware Library
Libraries
MG32L003_StdPeriph_Driver
inc
mg32l003_syscon.h
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __MG32L003_SYSCON_H
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#define __MG32L003_SYSCON_H
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "mg32l003.h"
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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#define SYSCON_KEY_UNLOCK (0x5A69)
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#define SYSCON_DEFAULT (0x00U)
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#define SYSCON_UART1_RXD (0x01U)
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#define SYSCON_UART2_RXD (0x02U)
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#define SYSCON_LPUART_RXD (0x03U)
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#define SYSCON_LSI (0x04U)
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#define SYSCON_SPINCS_SEL_0 (0x01U << 0)
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#define SYSCON_SPINCS_SEL_1 (0x01U << 1)
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#define SYSCON_SPINCS_SEL_2 (0x01U << 2)
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#define SYSCON_SPINCS_SEL_3 (0x01U << 3)
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#define SYSCON_SPINCS_SEL_4 (0x01U << 10)
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#define SYSCON_TIMETR_SEL_0 (0x01U << 16)
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#define SYSCON_TIMETR_SEL_1 (0x01U << 17)
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#define SYSCON_TIMETR_SEL_2 (0x01U << 18)
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#define SYSCON_TIMETR_SEL_3 (0x01U << 19)
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#define SYSCON_TIMETR_SEL_4 (0x01U << 23)
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#define SYSCON_TIM_ETR_LOWLEVEL (0x00000000U)
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#define SYSCON_TIM_ETR_PA1 (SYSCON_TIMETR_SEL_0)
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#define SYSCON_TIM_ETR_PA2 (SYSCON_TIMETR_SEL_1)
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#define SYSCON_TIM_ETR_PA3 (SYSCON_TIMETR_SEL_1 | SYSCON_TIMETR_SEL_0)
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#define SYSCON_TIM_ETR_PB4 (SYSCON_TIMETR_SEL_2)
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#define SYSCON_TIM_ETR_PB5 (SYSCON_TIMETR_SEL_2 | SYSCON_TIMETR_SEL_0)
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#define SYSCON_TIM_ETR_PC3 (SYSCON_TIMETR_SEL_2 | SYSCON_TIMETR_SEL_1)
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#define SYSCON_TIM_ETR_PC4 (SYSCON_TIMETR_SEL_2 | SYSCON_TIMETR_SEL_1 | SYSCON_TIMETR_SEL_0)
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#define SYSCON_TIM_ETR_PC5 (SYSCON_TIMETR_SEL_3)
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#define SYSCON_TIM_ETR_PC6 (SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_0)
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#define SYSCON_TIM_ETR_PC7 (SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_1)
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#define SYSCON_TIM_ETR_PD1 (SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_1 | SYSCON_TIMETR_SEL_0)
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#define SYSCON_TIM_ETR_PD2 (SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_2)
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#define SYSCON_TIM_ETR_PD3 (SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_2 | SYSCON_TIMETR_SEL_0)
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#define SYSCON_TIM_ETR_PD4 (SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_2 | SYSCON_TIMETR_SEL_1)
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#define SYSCON_TIM_ETR_PD6 (SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_2 | SYSCON_TIMETR_SEL_1 | SYSCON_TIMETR_SEL_0)
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#define SYSCON_TIM_ETR_PA4 (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_0)
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#define SYSCON_TIM_ETR_PB0 (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_1)
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#define SYSCON_TIM_ETR_PB1 (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_1 | SYSCON_TIMETR_SEL_0)
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#define SYSCON_TIM_ETR_PB2 (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_2)
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#define SYSCON_TIM_ETR_PB3 (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_2 | SYSCON_TIMETR_SEL_0)
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#define SYSCON_TIM_ETR_PB6 (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_2 | SYSCON_TIMETR_SEL_1)
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#define SYSCON_TIM_ETR_PB7 (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_2 | SYSCON_TIMETR_SEL_1 | SYSCON_TIMETR_SEL_0)
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#define SYSCON_TIM_ETR_PC0 (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_3)
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#define SYSCON_TIM_ETR_PC1 (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_0)
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#define SYSCON_TIM_ETR_PC2 (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_1)
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#define SYSCON_TIM_ETR_PD0 (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_1 | SYSCON_TIMETR_SEL_0)
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#define SYSCON_TIM_ETR_PD7 (SYSCON_TIMETR_SEL_4 | SYSCON_TIMETR_SEL_3 | SYSCON_TIMETR_SEL_2)
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#define SYSCON_SPI_NCS_HIGHLEVEL (0x00000000U)
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#define SYSCON_SPI_NCS_PA1 (SYSCON_SPINCS_SEL_0)
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#define SYSCON_SPI_NCS_PA2 (SYSCON_SPINCS_SEL_1)
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#define SYSCON_SPI_NCS_PA3 (SYSCON_SPINCS_SEL_1 | SYSCON_SPINCS_SEL_0)
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#define SYSCON_SPI_NCS_PB4 (SYSCON_SPINCS_SEL_2)
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#define SYSCON_SPI_NCS_PB5 (SYSCON_SPINCS_SEL_2 | SYSCON_SPINCS_SEL_0)
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#define SYSCON_SPI_NCS_PC3 (SYSCON_SPINCS_SEL_2 | SYSCON_SPINCS_SEL_1)
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#define SYSCON_SPI_NCS_PC4 (SYSCON_SPINCS_SEL_2 | SYSCON_SPINCS_SEL_1 | SYSCON_SPINCS_SEL_0)
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#define SYSCON_SPI_NCS_PC5 (SYSCON_SPINCS_SEL_3)
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#define SYSCON_SPI_NCS_PC6 (SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_0)
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#define SYSCON_SPI_NCS_PC7 (SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_1)
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#define SYSCON_SPI_NCS_PD1 (SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_1 | SYSCON_SPINCS_SEL_0)
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#define SYSCON_SPI_NCS_PD2 (SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_2)
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#define SYSCON_SPI_NCS_PD3 (SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_2 | SYSCON_SPINCS_SEL_0)
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#define SYSCON_SPI_NCS_PD4 (SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_2 | SYSCON_SPINCS_SEL_1)
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#define SYSCON_SPI_NCS_PD6 (SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_2 | SYSCON_SPINCS_SEL_1 | SYSCON_SPINCS_SEL_0)
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#define SYSCON_SPI_NCS_PA4 (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_0)
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#define SYSCON_SPI_NCS_PB0 (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_1)
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#define SYSCON_SPI_NCS_PB1 (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_1 | SYSCON_SPINCS_SEL_0)
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#define SYSCON_SPI_NCS_PB2 (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_2)
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#define SYSCON_SPI_NCS_PB3 (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_2 | SYSCON_SPINCS_SEL_0)
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#define SYSCON_SPI_NCS_PB6 (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_2 | SYSCON_SPINCS_SEL_1)
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#define SYSCON_SPI_NCS_PB7 (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_2 | SYSCON_SPINCS_SEL_1 | SYSCON_SPINCS_SEL_0)
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#define SYSCON_SPI_NCS_PC0 (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_3)
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#define SYSCON_SPI_NCS_PC1 (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_0)
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#define SYSCON_SPI_NCS_PC2 (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_1)
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#define SYSCON_SPI_NCS_PD0 (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_1 | SYSCON_SPINCS_SEL_0)
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#define SYSCON_SPI_NCS_PD7 (SYSCON_SPINCS_SEL_4 | SYSCON_SPINCS_SEL_3 | SYSCON_SPINCS_SEL_2)
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#define SYSCON_CLKFAILBRKEN SYSCON_TIM1CR_CLKFAILBRKEN
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#define SYSCON_DSLPBRKEN SYSCON_TIM1CR_DSLPBRKEN
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#define SYSCON_OCOUT_LOWLEVEL SYSCON_TIM1CR_TIM1BRKOUTCFG
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#define SYSCON_OCOUT_BYTIM1 (0x00U)
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/* Exported macro ------------------------------------------------------------*/
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#define SYSCON_REGWR_LOCK() (SYSCON->UNLOCK = (0x2AD5334C << SYSCON_UNLOCK_KEY_Pos) & SYSCON_UNLOCK_KEY)
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#define SYSCON_REGWR_UNLOCK() (SYSCON->UNLOCK = SYSCON_UNLOCK_UNLOCK | (0x2AD5334C << SYSCON_UNLOCK_KEY_Pos))
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#define SYSCON_DBGDEEPSLEEP_ENABLE() \
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do { \
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SYSCON_REGWR_UNLOCK(); \
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SET_BIT(SYSCON->CFGR0, SYSCON_CFGR0_DBGDLSP_DIS | (SYSCON_CFGR0_KEY << SYSCON_CFGR0_KEY_Pos)); \
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SYSCON_REGWR_LOCK(); \
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} while (0)
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#define SYSCON_DBGDEEPSLEEP_DISABLE() \
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do { \
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SYSCON_REGWR_UNLOCK(); \
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CLEAR_WPBIT(SYSCON->CFGR0, SYSCON_CFGR0_DBGDLSP_DIS, (SYSCON_CFGR0_KEY << SYSCON_CFGR0_KEY_Pos)); \
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SYSCON_REGWR_LOCK(); \
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} while (0)
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#define SYSCON_LOCKUP_ENABLE() \
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do { \
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SYSCON_REGWR_UNLOCK(); \
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SET_BIT(SYSCON->CFGR0, SYSCON_CFGR0_LOCKUPEN | (SYSCON_CFGR0_KEY << SYSCON_CFGR0_KEY_Pos)); \
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SYSCON_REGWR_LOCK(); \
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} while (0)
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#define SYSCON_LOCKUP_DISABLE() \
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do { \
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SYSCON_REGWR_UNLOCK(); \
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CLEAR_WPBIT(SYSCON->CFGR0, SYSCON_CFGR0_LOCKUPEN, (SYSCON_CFGR0_KEY << SYSCON_CFGR0_KEY_Pos)); \
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SYSCON_REGWR_LOCK(); \
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} while (0)
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#define SYSCON_DEEPSLEEP_PADINT_AUTO() \
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do { \
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SYSCON_REGWR_UNLOCK(); \
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CLEAR_WPBIT(SYSCON->PORTINTCR, SYSCON_PORTINTCR_PADDLSPCON, (SYSCON_UNLOCK_KEY << SYSCON_PORTINTCR_KEY_Pos)); \
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SYSCON_REGWR_LOCK(); \
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} while (0)
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#define SYSCON_DEEPSLEEP_PADINT_ACTIVE() \
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do { \
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SYSCON_REGWR_UNLOCK(); \
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SET_BIT(SYSCON->PORTINTCR, SYSCON_PORTINTCR_PADDLSPCON | (SYSCON_UNLOCK_KEY << SYSCON_PORTINTCR_KEY_Pos)); \
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CLEAR_WPBIT(SYSCON->PORTINTCR, SYSCON_PORTINTCR_PADINTSEL, (SYSCON_UNLOCK_KEY << SYSCON_PORTINTCR_KEY_Pos)); \
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SYSCON_REGWR_LOCK(); \
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} while (0)
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#define SYSCON_LPTIM_GATE(SOURCE) \
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do { \
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SYSCON_REGWR_UNLOCK(); \
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MODIFY_REG(SYSCON->PORTCR, SYSCON_PORTCR_LPTIM_GATE_SEL, ((SOURCE) << SYSCON_PORTCR_LPTIM_GATE_SEL_Pos)); \
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SYSCON_REGWR_UNLOCK(); \
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} while (0)
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#define SYSCON_TIM11_GATE(SOURCE) \
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do { \
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SYSCON_REGWR_UNLOCK(); \
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MODIFY_REG(SYSCON->PORTCR, SYSCON_PORTCR_TIM11_GATE_SEL, ((SOURCE) << SYSCON_PORTCR_TIM11_GATE_SEL_Pos)); \
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SYSCON_REGWR_LOCK(); \
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} while (0)
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#define SYSCON_TIM10_GATE(SOURCE) \
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do { \
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SYSCON_REGWR_UNLOCK(); \
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MODIFY_REG(SYSCON->PORTCR, SYSCON_PORTCR_TIM10_GATE_SEL, ((SOURCE) << SYSCON_PORTCR_TIM10_GATE_SEL_Pos)); \
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SYSCON_REGWR_LOCK(); \
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} while (0)
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#define SYSCON_SPINCS(SOURCE) \
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do { \
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SYSCON_REGWR_UNLOCK(); \
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MODIFY_REG(SYSCON->PORTCR, SYSCON_PORTCR_SPINCS_SEL, (SOURCE)); \
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SYSCON_REGWR_LOCK(); \
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} while (0)
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#define SYSCON_PCA_CAP4(SOURCE) \
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do { \
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SYSCON_REGWR_UNLOCK(); \
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MODIFY_REG(SYSCON->PCACR, SYSCON_PCACR_PCA_CAP4_SEL, ((SOURCE) << SYSCON_PCACR_PCA_CAP4_SEL_Pos)); \
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SYSCON_REGWR_LOCK(); \
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} while (0)
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#define SYSCON_PCA_CAP3(SOURCE) \
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do { \
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SYSCON_REGWR_UNLOCK(); \
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MODIFY_REG(SYSCON->PCACR, SYSCON_PCACR_PCA_CAP3_SEL, ((SOURCE) << SYSCON_PCACR_PCA_CAP3_SEL_Pos)); \
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SYSCON_REGWR_LOCK(); \
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} while (0)
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#define SYSCON_PCA_CAP2(SOURCE) \
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do { \
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SYSCON_REGWR_UNLOCK(); \
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MODIFY_REG(SYSCON->PCACR, SYSCON_PCACR_PCA_CAP2_SEL, ((SOURCE) << SYSCON_PCACR_PCA_CAP2_SEL_Pos)); \
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SYSCON_REGWR_LOCK(); \
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} while (0)
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#define SYSCON_PCA_CAP1(SOURCE) \
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do { \
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SYSCON_REGWR_UNLOCK(); \
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MODIFY_REG(SYSCON->PCACR, SYSCON_PCACR_PCA_CAP1_SEL, ((SOURCE) << SYSCON_PCACR_PCA_CAP1_SEL_Pos)); \
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SYSCON_REGWR_LOCK(); \
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} while (0)
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#define SYSCON_PCA_CAP0(SOURCE) \
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do { \
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SYSCON_REGWR_UNLOCK(); \
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MODIFY_REG(SYSCON->PCACR, SYSCON_PCACR_PCA_CAP0_SEL, ((SOURCE) << SYSCON_PCACR_PCA_CAP0_SEL_Pos)); \
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SYSCON_REGWR_LOCK(); \
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} while (0)
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#define SYSCON_TIM1_BREAKIN_SEL(SOURCE) \
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do { \
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SYSCON_REGWR_UNLOCK(); \
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MODIFY_REG(SYSCON->TIM1CR, SYSCON_TIM1CR_CLKFAILBRKEN | SYSCON_TIM1CR_DSLPBRKEN, (SOURCE)); \
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SYSCON_REGWR_LOCK(); \
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} while (0)
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#define SYSCON_TIM1_BREAKOUT_CFG(CONFIG) \
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do { \
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SYSCON_REGWR_UNLOCK(); \
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MODIFY_REG(SYSCON->TIM1CR, SYSCON_TIM1CR_TIM1BRKOUTCFG, (CONFIG)); \
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SYSCON_REGWR_LOCK(); \
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} while (0)
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#define SYSCON_TIM1ETR_SEL(SOURCE) \
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do { \
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SYSCON_REGWR_UNLOCK(); \
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MODIFY_REG(SYSCON->TIM1CR, SYSCON_TIM1CR_TIM1ETR_SEL, (SOURCE)); \
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SYSCON_REGWR_LOCK(); \
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} while (0)
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#define SYSCON_TIM1CH4IN_SEL(SOURCE) \
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do { \
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SYSCON_REGWR_UNLOCK(); \
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MODIFY_REG(SYSCON->TIM1CR, SYSCON_TIM1CR_TIM1CH4IN_SEL, ((SOURCE) << SYSCON_TIM1CR_TIM1CH4IN_SEL_Pos)); \
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SYSCON_REGWR_LOCK(); \
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} while (0)
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#define SYSCON_TIM1CH3IN_SEL(SOURCE) \
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do { \
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SYSCON_REGWR_UNLOCK(); \
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MODIFY_REG(SYSCON->TIM1CR, SYSCON_TIM1CR_TIM1CH3IN_SEL, ((SOURCE) << SYSCON_TIM1CR_TIM1CH3IN_SEL_Pos)); \
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SYSCON_REGWR_LOCK(); \
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} while (0)
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#define SYSCON_TIM1CH2IN_SEL(SOURCE) \
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do { \
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SYSCON_REGWR_UNLOCK(); \
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MODIFY_REG(SYSCON->TIM1CR, SYSCON_TIM1CR_TIM1CH2IN_SEL, ((SOURCE) << SYSCON_TIM1CR_TIM1CH2IN_SEL_Pos)); \
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SYSCON_REGWR_LOCK(); \
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} while (0)
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#define SYSCON_TIM1CH1IN_SEL(SOURCE) \
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do { \
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SYSCON_REGWR_UNLOCK(); \
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MODIFY_REG(SYSCON->TIM1CR, SYSCON_TIM1CR_TIM1CH1IN_SEL, ((SOURCE) << SYSCON_TIM1CR_TIM1CH1IN_SEL_Pos)); \
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SYSCON_REGWR_LOCK(); \
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} while (0)
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#define SYSCON_TIM2ETR_SEL(SOURCE) \
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do { \
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SYSCON_REGWR_UNLOCK(); \
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MODIFY_REG(SYSCON->TIM2CR, SYSCON_TIM2CR_TIM2ETR_SEL, (SOURCE)); \
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SYSCON_REGWR_LOCK(); \
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} while (0)
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#define SYSCON_TIM2CH4IN_SEL(SOURCE) \
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do { \
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SYSCON_REGWR_UNLOCK(); \
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MODIFY_REG(SYSCON->TIM2CR, SYSCON_TIM2CR_TIM2CH4IN_SEL, ((SOURCE) << SYSCON_TIM2CR_TIM2CH4IN_SEL_Pos)); \
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SYSCON_REGWR_LOCK(); \
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} while (0)
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#define SYSCON_TIM2CH3IN_SEL(SOURCE) \
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do { \
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SYSCON_REGWR_UNLOCK(); \
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MODIFY_REG(SYSCON->TIM2CR, SYSCON_TIM2CR_TIM2CH3IN_SEL, ((SOURCE) << SYSCON_TIM2CR_TIM2CH3IN_SEL_Pos)); \
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SYSCON_REGWR_LOCK(); \
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} while (0)
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#define SYSCON_TIM2CH2IN_SEL(SOURCE) \
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do { \
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SYSCON_REGWR_UNLOCK(); \
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MODIFY_REG(SYSCON->TIM2CR, SYSCON_TIM2CR_TIM2CH2IN_SEL, ((SOURCE) << SYSCON_TIM2CR_TIM2CH2IN_SEL_Pos)); \
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SYSCON_REGWR_LOCK(); \
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} while (0)
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#define SYSCON_TIM2CH1IN_SEL(SOURCE) \
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do { \
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SYSCON_REGWR_UNLOCK(); \
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MODIFY_REG(SYSCON->TIM2CR, SYSCON_TIM2CR_TIM2CH1IN_SEL, ((SOURCE) << SYSCON_TIM2CR_TIM2CH1IN_SEL_Pos)); \
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SYSCON_REGWR_LOCK(); \
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} while (0)
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/* Exported functions --------------------------------------------------------*/
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#ifdef __cplusplus
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}
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#endif
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#endif
/*__MG32L003_SYSCON_H */
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