/**
 ******************************************************************************
 *
 * @file        MG32_URT.h
 *
 * @brief       MG32 URT Register Definitions Header File
 *
 * @par         Project
 *              MG32
 * @version     V0.95 (Register File Date : 2025_1031)
 * @date        2026/07/03 15:02 (H File Generated Date)
 * @author      HeadCodeGen V1.61
 * @copyright   Copyright (c) 2024 Megawin Technology Co., Ltd.
 *              All rights reserved.
 *
 * Important!   This file is generated by code generator. Do not edit!
 *
 ******************************************************************************
 */

#ifndef _MG32_URT_H
#define _MG32_URT_H
#define _MG32_URT_H_VER                             95      /*!< File Version */

#include "MG32.h"

#if !(_MG32_H_VER == _MG32_URT_H_VER)
    #error "_MG32_URT_H - Main/Module Version Mismatch !"
#endif

/**
 ******************************************************************************
 *
 * @struct      URT_Struct
 *              URT  [Module Structure Typedef]
 *
 ******************************************************************************
 */
typedef struct
{
    union
    {
        __IO  uint32_t  W;
        __IO  uint16_t  H[2];
        __IO  uint8_t   B[4];
        struct
        {
            __I  uint8_t                :1;     //[0] 
            __IO uint8_t  UGF           :1;     //[1] UART general event flag
                                        //0 = Normal (No event occurred)
                                        //1 = Happened (Event happened)
            __IO uint8_t  TCF           :1;     //[2] UART transmission complete flag
                                        //0 = Normal (No event occurred)
                                        //1 = Happened (Event happened)
            __IO uint8_t  ERRF          :1;     //[3] UART error interrupt flag for parity error, frame error, overrun error, receive time 
                                        //0 = Normal (No event occurred)
                                        //1 = Happened (Event happened)
            __I  uint8_t                :1;     //[4] 
            __I  uint8_t                :1;     //[5] 
            __IO uint8_t  RXF           :1;     //[6] UART receive data register not empty
                                        //0 = Normal (No event occurred)
                                        //1 = Happened (Event happened)
            __IO uint8_t  TXF           :1;     //[7] UART transmit data register empty
                                        //0 = Normal (No event occurred)
                                        //1 = Happened (Event happened)
            __I  uint8_t                :1;     //[8] 
            __I  uint8_t                :1;     //[9] 
            __I  uint8_t                :1;     //[10] 
            __IO uint8_t  BRTF          :1;     //[11] UART baud-rate generator timer timeout flag
                                        //0 = Normal (No event occurred)
                                        //1 = Happened (Event happened)
            __I  uint8_t                :1;     //[12] 
            __I  uint8_t                :1;     //[13] 
            __I  uint8_t                :1;     //[14] 
            __I  uint8_t                :1;     //[15] 
            __I  uint8_t                :1;     //[16] 
            __I  uint8_t                :1;     //[17] 
            __I  uint8_t                :1;     //[18] 
            __I  uint8_t                :1;     //[19] 
            __IO uint8_t  PEF           :1;     //[20] UART parity error flag
                                        //0 = Normal (No event occurred)
                                        //1 = Happened (Event happened)
            __IO uint8_t  FEF           :1;     //[21] UART frame error flag.  (set by hardware and clear by software writing 1)
                                        //0 = Normal (No event occurred)
                                        //1 = Happened (Event happened)
            __I  uint8_t                :1;     //[22] 
            __IO uint8_t  ROVRF         :1;     //[23] UART receive overrun error flag
                                        //0 = Normal (No event occurred)
                                        //1 = Happened (Event happened)
            __I  uint8_t                :1;     //[24] 
            __I  uint8_t                :2;     //[26..25] 
            __I  uint8_t                :1;     //[27] 
            __I  uint8_t                :1;     //[28] 
            __I  uint8_t                :1;     //[29] 
            __I  uint8_t                :1;     //[30] 
            __I  uint8_t                :1;     //[31] 
        }MBIT;
    }STA;                               /*!< STA        ~ Offset[0x00]  URT status register 1 */

    union
    {
        __IO  uint32_t  W;
        __IO  uint16_t  H[2];
        __IO  uint8_t   B[4];
        struct
        {
            __IO uint8_t  IEA           :1;     //[0] UART interrupt all enable
                                        //0 = Disable
                                        //1 = Enable
            __IO uint8_t  UG_IE         :1;     //[1] UART general event interrupt enable for URTx_SADRF , URTx_TF , URTx_RCNTF or URTx_TCN
                                        //0 = Disable
                                        //1 = Enable
            __IO uint8_t  TC_IE         :1;     //[2] UART transmission complete interrupt enable
                                        //0 = Disable
                                        //1 = Enable
            __IO uint8_t  ERR_IE        :1;     //[3] UART error interrupt enable for parity error, frame error, overrun error, receive tim
                                        //0 = Disable
                                        //1 = Enable
            __I  uint8_t                :1;     //[4] 
            __I  uint8_t                :1;     //[5] 
            __IO uint8_t  RX_IE         :1;     //[6] UART receive data register not empty interrupt enable
                                        //0 = Disable
                                        //1 = Enable
            __IO uint8_t  TX_IE         :1;     //[7] UART transmit data register empty interrupt enable. Refer to URTx_TXF for the detail.
                                        //0 = Disable
                                        //1 = Enable
            __I  uint8_t                :1;     //[8] 
            __I  uint8_t                :1;     //[9] 
            __I  uint8_t                :1;     //[10] 
            __IO uint8_t  BRT_IE        :1;     //[11] UART baud-rate generator timer timeout interrupt enable.
                                        //0 = Disable
                                        //1 = Enable
            __I  uint8_t                :1;     //[12] 
            __I  uint8_t                :1;     //[13] 
            __I  uint8_t                :2;     //[15..14] 
            __I  uint8_t                :1;     //[16] 
            __I  uint8_t                :1;     //[17] 
            __I  uint8_t                :1;     //[18] 
            __I  uint8_t                :1;     //[19] 
            __IO uint8_t  PE_IE         :1;     //[20] UART parity error interrupt enable.
                                        //0 = Disable
                                        //1 = Enable
            __IO uint8_t  FE_IE         :1;     //[21] UART frame error interrupt enable.
                                        //0 = Disable
                                        //1 = Enable
            __I  uint8_t                :1;     //[22] 
            __IO uint8_t  ROVR_IE       :1;     //[23] UART receive overrun error interrupt enable. Refer to URTx_ROVRF for the detail.
                                        //0 = Disable
                                        //1 = Enable
            __I  uint8_t                :1;     //[24] 
            __I  uint8_t                :2;     //[26..25] 
            __I  uint8_t                :1;     //[27] 
            __I  uint8_t                :1;     //[28] 
            __I  uint8_t                :1;     //[29] 
            __I  uint8_t                :1;     //[30] 
            __I  uint8_t                :1;     //[31] 
        }MBIT;
    }INT;                               /*!< INT        ~ Offset[0x04]  URT interrupt enable register */

    union
    {
        __IO  uint32_t  W;
        __IO  uint16_t  H[2];
        __IO  uint8_t   B[4];
        struct
        {
            __I  uint8_t                :1;     //[0] 
            __IO uint8_t  CK_SEL        :2;     //[2..1] UART internal clock CK_URTx source select.
                                        //0x0 = PROC : CK_URTx_PR process clock from CSC
                                        //0x1 = Reserved
                                        //0x2 = CK_LS
                                        //0x3 = TM00_TRGO
            __I  uint8_t                :2;     //[4..3] 
            __I  uint8_t                :1;     //[5] 
            __I  uint8_t                :1;     //[6] 
            __I  uint8_t                :1;     //[7] 
            __I  uint8_t                :8;     //[15..8] 
            __I  uint8_t                :2;     //[17..16] 
            __I  uint8_t                :2;     //[19..18] 
            __I  uint8_t                :2;     //[21..20] 
            __I  uint8_t                :2;     //[23..22] 
            __IO uint8_t  BR_EN         :1;     //[24] UART baud-rate timer enable. When enables, the baud-rate timer 
                                        //0 = Disable
                                        //1 = Enable
            __IO uint8_t  BR_MDS        :1;     //[25] UART baud-rate timer mode select
                                        //0 = Separated : Separated PSC and CNT counters for UART baud-rate generator
                                        //1 = Combined : Combine to a linear counter for general using timer
            __I  uint8_t                :1;     //[26] 
            __I  uint8_t                :1;     //[27] 
            __I  uint8_t                :1;     //[28] 
            __I  uint8_t                :1;     //[29] 
            __I  uint8_t                :1;     //[30] 
            __I  uint8_t                :1;     //[31] 
        }MBIT;
    }CLK;                               /*!< CLK        ~ Offset[0x08]  URT clock source register */

    union
    {
        __IO  uint32_t  W;
        __IO  uint16_t  H[2];
        __IO  uint8_t   B[4];
        struct
        {
            __I  uint8_t  BUSYF         :1;     //[0] UART RX busy flag
                                        //0 = Normal (No event occurred)
                                        //1 = Busy (Event happened)
            __I  uint8_t  PAR           :1;     //[1] UART data receive parity bit of shift buffer
            __I  uint8_t                :1;     //[2] 
            __I  uint8_t                :1;     //[3] 
            __I  uint8_t                :1;     //[4] 
            __I  uint8_t                :1;     //[5] 
            __I  uint8_t                :1;     //[6] 
            __I  uint8_t                :1;     //[7] 
            __I  uint8_t                :1;     //[8] 
            __I  uint8_t                :1;     //[9] 
            __I  uint8_t                :2;     //[11..10] 
            __I  uint8_t                :1;     //[12] 
            __I  uint8_t                :1;     //[13] 
            __I  uint8_t                :1;     //[14] 
            __I  uint8_t                :1;     //[15] 
            __I  uint8_t                :8;     //[23..16] 
            __I  uint8_t                :3;     //[26..24] 
            __I  uint8_t                :1;     //[27] 
            __I  uint8_t                :3;     //[30..28] 
            __I  uint8_t                :1;     //[31] 
        }MBIT;
    }STA2;                              /*!< STA2       ~ Offset[0x0C]  URT status register 2 */

    union
    {
        __IO  uint32_t  W;
        __IO  uint16_t  H[2];
        __IO  uint8_t   B[4];
        struct
        {
            __IO uint8_t  EN            :1;     //[0] UART function enable bit.
                                        //0 = Disable
                                        //1 = Enable
            __I  uint8_t                :1;     //[1] 
            __I  uint8_t                :1;     //[2] 
            __I  uint8_t                :1;     //[3] 
            __I  uint8_t                :3;     //[6..4] 
            __I  uint8_t                :1;     //[7] 
            __IO uint8_t  IO_SWP        :1;     //[8] URTx_RX/URTx_TX swap enable bit.
                                        //0 = Disable
                                        //1 = Enable
            __I  uint8_t                :1;     //[9] 
            __IO uint8_t  RX_INV        :1;     //[10] URTx_RX input signal inverse enable.
                                        //0 = Disable
                                        //1 = Enable
            __IO uint8_t  TX_INV        :1;     //[11] URTx_TX output signal inverse enable.
                                        //0 = Disable
                                        //1 = Enable
            __I  uint8_t                :1;     //[12] 
            __I  uint8_t                :1;     //[13] 
            __I  uint8_t                :2;     //[15..14] 
            __I  uint8_t                :2;     //[17..16] 
            __I  uint8_t                :2;     //[19..18] 
            __I  uint8_t                :1;     //[20] 
            __I  uint8_t                :1;     //[21] 
            __I  uint8_t                :1;     //[22] 
            __IO uint8_t  LBM_EN        :1;     //[23] UART loop back mode enable bit
                                        //0 = Disable
                                        //1 = Enable
            __I  uint8_t                :1;     //[24] 
            __I  uint8_t                :4;     //[28..25] 
            __I  uint8_t                :1;     //[29] 
            __I  uint8_t                :1;     //[30] 
            __I  uint8_t                :1;     //[31] 
        }MBIT;
    }CR0;                               /*!< CR0        ~ Offset[0x10]  URT control register 0 */

    union
    {
        __IO  uint32_t  W;
        __IO  uint16_t  H[2];
        __IO  uint8_t   B[4];
        struct
        {
            __I  uint8_t                :2;     //[1..0] 
            __I  uint8_t                :1;     //[2] 
            __IO uint8_t  RXPAR_POL     :1;     //[3] UART RX parity bit polarity. This bit is no effect for SYNC mods.
                                        //0x0 = Even
                                        //0x1 = Odd
            __IO uint8_t  RXPAR_STK     :1;     //[4] UART stuck parity bit input enable
                                        //0 = Disable
                                        //1 = Enable
            __I  uint8_t                :1;     //[5] 
            __I  uint8_t                :2;     //[7..6] 
            __I  uint8_t                :5;     //[12..8] 
            __I  uint8_t                :3;     //[15..13] 
            __IO uint8_t  TXDSIZE       :2;     //[17..16] UART TX data bit length
                                        //0x0 = 8bit
                                        //0x1 = 7bit
                                        //0x2 = Reserved
                                        //0x3 = Reserved
            __IO uint8_t  TXPAR_EN      :1;     //[18] UART TX parity bit enable
                                        //0 = Disable
                                        //1 = Enable
            __IO uint8_t  TXPAR_POL     :1;     //[19] UART TX parity bit polarity. This bit is no effect for SPI and SYNC mods.
                                        //0x0 = Even
                                        //0x1 = Odd
            __IO uint8_t  TXPAR_STK     :1;     //[20] UART stuck parity bit output enable
                                        //0 = Disable
                                        //1 = Enable
            __I  uint8_t                :1;     //[21] 
            __IO uint8_t  TXSTP_LEN     :2;     //[23..22] UART TX stop bit length select
                                        //0x0 = Reserved
                                        //0x1 = 1bit
                                        //0x2 = Reserved
                                        //0x3 = 2bit
            __IO uint8_t  TXOS_NUM      :5;     //[28..24] UART TX data oversampling samples select
            __I  uint8_t                :3;     //[31..29] 
        }MBIT;
    }CR1;                               /*!< CR1        ~ Offset[0x14]  URT control register 1 */

    union
    {
        __IO  uint32_t  W;
        __IO  uint16_t  H[2];
        __IO  uint8_t   B[4];
        struct
        {
            __I  uint8_t                :1;     //[0] 
            __I  uint8_t                :1;     //[1] 
            __IO uint8_t  RX_EN         :1;     //[2] UART receiver enable.
                                        //0 = Disable
                                        //1 = Enable
            __IO uint8_t  TX_EN         :1;     //[3] UART transmitter enable.
                                        //0 = Disable
                                        //1 = Enable
            __I  uint8_t                :1;     //[4] 
            __I  uint8_t                :3;     //[7..5] 
            __I  uint8_t                :8;     //[15..8] 
            __I  uint8_t                :1;     //[16] 
            __I  uint8_t                :1;     //[17] 
            __I  uint8_t                :6;     //[23..18] 
            __I  uint8_t                :1;     //[24] 
            __I  uint8_t                :1;     //[25] 
            __I  uint8_t                :1;     //[26] 
            __I  uint8_t                :1;     //[27] 
            __I  uint8_t                :1;     //[28] 
            __I  uint8_t                :1;     //[29] 
            __I  uint8_t                :2;     //[31..30] 
        }MBIT;
    }CR2;                               /*!< CR2        ~ Offset[0x18]  URT control register 2 */

    __I uint32_t  RESERVED0[2];         /*!< RESERVED0  ~ Offset[0x1C]  Reserved */

    union
    {
        __IO  uint32_t  W;
        __IO  uint16_t  H[2];
        __IO  uint8_t   B[4];
        struct
        {
            __IO uint8_t  RLR           :8;     //[7..0] UART baud-rate clock counter reload register
            __IO uint8_t  PSR           :6;     //[13..8] UART baud-rate clock prescaler reload register
            __I  uint8_t                :2;     //[15..14] 
            __I  uint16_t               :16;    //[31..16] 
        }MBIT;
    }RLR;                               /*!< RLR        ~ Offset[0x24]  URT baud-rate clock counter reload register */

    union
    {
        __IO  uint32_t  W;
        __IO  uint16_t  H[2];
        __IO  uint8_t   B[4];
        struct
        {
            __I  uint8_t  CNT           :8;     //[7..0] UART baud-rate clock counter value register.
            __I  uint8_t  PSC           :6;     //[13..8] UART baud-rate clock prescaler value register.
            __I  uint8_t                :2;     //[15..14] 
            __I  uint16_t               :16;    //[31..16] 
        }MBIT;
    }CNT;                               /*!< CNT        ~ Offset[0x28]  URT baud-rate clock counter register */

    __I uint32_t  RESERVED1;            /*!< RESERVED1  ~ Offset[0x2C]  Reserved */

    union
    {
        __IO  uint32_t  W;
        __IO  uint16_t  H[2];
        __IO  uint8_t   B[4];
        struct
        {
            __I  uint8_t  RDAT          :8;     //[7..0] UART received data register
            __I  uint8_t                :8;     //[15..8] 
            __I  uint16_t               :16;    //[31..16] 
        }MBIT;
    }RDAT;                              /*!< RDAT       ~ Offset[0x30]  URT RX data register */

    union
    {
        __IO  uint32_t  W;
        __IO  uint16_t  H[2];
        __IO  uint8_t   B[4];
        struct
        {
            __IO uint8_t  TDAT          :8;     //[7..0] UART transmitted data register
            __I  uint8_t                :8;     //[15..8] 
            __I  uint16_t               :16;    //[31..16] 
        }MBIT;
    }TDAT;                              /*!< TDAT       ~ Offset[0x34]  URT TX data register */

    __I uint32_t  RESERVED2;            /*!< RESERVED2  ~ Offset[0x38]  Reserved */

    union
    {
        __IO  uint32_t  W;
        __IO  uint16_t  H[2];
        __IO  uint8_t   B[4];
        struct
        {
            __I  uint8_t  RSBUF         :8;     //[7..0] UART RX data shift buffer register.
            __I  uint8_t  TSBUF         :8;     //[15..8] UART TX data shift buffer register.
            __I  uint16_t               :16;    //[31..16] 
        }MBIT;
    }SBUF;                              /*!< SBUF       ~ Offset[0x3C]  URT data shift buffer register */

} URT_Struct;

/**
 ******************************************************************************
 *
 * @name        URT  [Base Address/Type]
 *
 ******************************************************************************
 */
///@{
#define URT4_Base                       ((uint32_t)0x52040000)              /*!< UART Control Module-4 */
#define URT4                            ((URT_Struct*) URT4_Base)
///@}

/**
 ******************************************************************************
 *
 * @name        URT  [Register Definitions]
 *
 ******************************************************************************
 */
/**
 ******************************************************************************
 * @name        URT_STA  [register's definitions]
 *              Offset[0x00]  URT status register 1
 ******************************************************************************
 */
///@{
#define URT_STA_default                             ((uint32_t)0x00000000)  /*!< Reg Reset Default Value */

/* Bit fields of URT_STA */
#define URT_STA_ROVRF_mask_w                        ((uint32_t)0x00800000)  /*!< Bit Mask of 32bit */
#define URT_STA_ROVRF_mask_h1                       ((uint16_t)0x0080)      /*!< Bit Mask of 16bit */
#define URT_STA_ROVRF_mask_b2                       ((uint8_t )0x80)        /*!< Bit Mask of 8bit */
#define URT_STA_ROVRF_normal_w                      ((uint32_t)0x00000000)  /*!< Bit Value =(0):Normal of 32bit */
#define URT_STA_ROVRF_normal_h1                     ((uint16_t)0x0000)      /*!< Bit Value =(0):Normal of 16bit */
#define URT_STA_ROVRF_normal_b2                     ((uint8_t )0x00)        /*!< Bit Value =(0):Normal of 8bit */
#define URT_STA_ROVRF_happened_w                    ((uint32_t)0x00800000)  /*!< Bit Value =(1):Happened of 32bit */
#define URT_STA_ROVRF_happened_h1                   ((uint16_t)0x0080)      /*!< Bit Value =(1):Happened of 16bit */
#define URT_STA_ROVRF_happened_b2                   ((uint8_t )0x80)        /*!< Bit Value =(1):Happened of 8bit */

#define URT_STA_FEF_mask_w                          ((uint32_t)0x00200000)  /*!< Bit Mask of 32bit */
#define URT_STA_FEF_mask_h1                         ((uint16_t)0x0020)      /*!< Bit Mask of 16bit */
#define URT_STA_FEF_mask_b2                         ((uint8_t )0x20)        /*!< Bit Mask of 8bit */
#define URT_STA_FEF_normal_w                        ((uint32_t)0x00000000)  /*!< Bit Value =(0):Normal of 32bit */
#define URT_STA_FEF_normal_h1                       ((uint16_t)0x0000)      /*!< Bit Value =(0):Normal of 16bit */
#define URT_STA_FEF_normal_b2                       ((uint8_t )0x00)        /*!< Bit Value =(0):Normal of 8bit */
#define URT_STA_FEF_happened_w                      ((uint32_t)0x00200000)  /*!< Bit Value =(1):Happened of 32bit */
#define URT_STA_FEF_happened_h1                     ((uint16_t)0x0020)      /*!< Bit Value =(1):Happened of 16bit */
#define URT_STA_FEF_happened_b2                     ((uint8_t )0x20)        /*!< Bit Value =(1):Happened of 8bit */

#define URT_STA_PEF_mask_w                          ((uint32_t)0x00100000)  /*!< Bit Mask of 32bit */
#define URT_STA_PEF_mask_h1                         ((uint16_t)0x0010)      /*!< Bit Mask of 16bit */
#define URT_STA_PEF_mask_b2                         ((uint8_t )0x10)        /*!< Bit Mask of 8bit */
#define URT_STA_PEF_normal_w                        ((uint32_t)0x00000000)  /*!< Bit Value =(0):Normal of 32bit */
#define URT_STA_PEF_normal_h1                       ((uint16_t)0x0000)      /*!< Bit Value =(0):Normal of 16bit */
#define URT_STA_PEF_normal_b2                       ((uint8_t )0x00)        /*!< Bit Value =(0):Normal of 8bit */
#define URT_STA_PEF_happened_w                      ((uint32_t)0x00100000)  /*!< Bit Value =(1):Happened of 32bit */
#define URT_STA_PEF_happened_h1                     ((uint16_t)0x0010)      /*!< Bit Value =(1):Happened of 16bit */
#define URT_STA_PEF_happened_b2                     ((uint8_t )0x10)        /*!< Bit Value =(1):Happened of 8bit */

#define URT_STA_BRTF_mask_w                         ((uint32_t)0x00000800)  /*!< Bit Mask of 32bit */
#define URT_STA_BRTF_mask_h0                        ((uint16_t)0x0800)      /*!< Bit Mask of 16bit */
#define URT_STA_BRTF_mask_b1                        ((uint8_t )0x08)        /*!< Bit Mask of 8bit */
#define URT_STA_BRTF_normal_w                       ((uint32_t)0x00000000)  /*!< Bit Value =(0):Normal of 32bit */
#define URT_STA_BRTF_normal_h0                      ((uint16_t)0x0000)      /*!< Bit Value =(0):Normal of 16bit */
#define URT_STA_BRTF_normal_b1                      ((uint8_t )0x00)        /*!< Bit Value =(0):Normal of 8bit */
#define URT_STA_BRTF_happened_w                     ((uint32_t)0x00000800)  /*!< Bit Value =(1):Happened of 32bit */
#define URT_STA_BRTF_happened_h0                    ((uint16_t)0x0800)      /*!< Bit Value =(1):Happened of 16bit */
#define URT_STA_BRTF_happened_b1                    ((uint8_t )0x08)        /*!< Bit Value =(1):Happened of 8bit */

#define URT_STA_TXF_mask_w                          ((uint32_t)0x00000080)  /*!< Bit Mask of 32bit */
#define URT_STA_TXF_mask_h0                         ((uint16_t)0x0080)      /*!< Bit Mask of 16bit */
#define URT_STA_TXF_mask_b0                         ((uint8_t )0x80)        /*!< Bit Mask of 8bit */
#define URT_STA_TXF_normal_w                        ((uint32_t)0x00000000)  /*!< Bit Value =(0):Normal of 32bit */
#define URT_STA_TXF_normal_h0                       ((uint16_t)0x0000)      /*!< Bit Value =(0):Normal of 16bit */
#define URT_STA_TXF_normal_b0                       ((uint8_t )0x00)        /*!< Bit Value =(0):Normal of 8bit */
#define URT_STA_TXF_happened_w                      ((uint32_t)0x00000080)  /*!< Bit Value =(1):Happened of 32bit */
#define URT_STA_TXF_happened_h0                     ((uint16_t)0x0080)      /*!< Bit Value =(1):Happened of 16bit */
#define URT_STA_TXF_happened_b0                     ((uint8_t )0x80)        /*!< Bit Value =(1):Happened of 8bit */

#define URT_STA_RXF_mask_w                          ((uint32_t)0x00000040)  /*!< Bit Mask of 32bit */
#define URT_STA_RXF_mask_h0                         ((uint16_t)0x0040)      /*!< Bit Mask of 16bit */
#define URT_STA_RXF_mask_b0                         ((uint8_t )0x40)        /*!< Bit Mask of 8bit */
#define URT_STA_RXF_normal_w                        ((uint32_t)0x00000000)  /*!< Bit Value =(0):Normal of 32bit */
#define URT_STA_RXF_normal_h0                       ((uint16_t)0x0000)      /*!< Bit Value =(0):Normal of 16bit */
#define URT_STA_RXF_normal_b0                       ((uint8_t )0x00)        /*!< Bit Value =(0):Normal of 8bit */
#define URT_STA_RXF_happened_w                      ((uint32_t)0x00000040)  /*!< Bit Value =(1):Happened of 32bit */
#define URT_STA_RXF_happened_h0                     ((uint16_t)0x0040)      /*!< Bit Value =(1):Happened of 16bit */
#define URT_STA_RXF_happened_b0                     ((uint8_t )0x40)        /*!< Bit Value =(1):Happened of 8bit */

#define URT_STA_ERRF_mask_w                         ((uint32_t)0x00000008)  /*!< Bit Mask of 32bit */
#define URT_STA_ERRF_mask_h0                        ((uint16_t)0x0008)      /*!< Bit Mask of 16bit */
#define URT_STA_ERRF_mask_b0                        ((uint8_t )0x08)        /*!< Bit Mask of 8bit */
#define URT_STA_ERRF_normal_w                       ((uint32_t)0x00000000)  /*!< Bit Value =(0):Normal of 32bit */
#define URT_STA_ERRF_normal_h0                      ((uint16_t)0x0000)      /*!< Bit Value =(0):Normal of 16bit */
#define URT_STA_ERRF_normal_b0                      ((uint8_t )0x00)        /*!< Bit Value =(0):Normal of 8bit */
#define URT_STA_ERRF_happened_w                     ((uint32_t)0x00000008)  /*!< Bit Value =(1):Happened of 32bit */
#define URT_STA_ERRF_happened_h0                    ((uint16_t)0x0008)      /*!< Bit Value =(1):Happened of 16bit */
#define URT_STA_ERRF_happened_b0                    ((uint8_t )0x08)        /*!< Bit Value =(1):Happened of 8bit */

#define URT_STA_TCF_mask_w                          ((uint32_t)0x00000004)  /*!< Bit Mask of 32bit */
#define URT_STA_TCF_mask_h0                         ((uint16_t)0x0004)      /*!< Bit Mask of 16bit */
#define URT_STA_TCF_mask_b0                         ((uint8_t )0x04)        /*!< Bit Mask of 8bit */
#define URT_STA_TCF_normal_w                        ((uint32_t)0x00000000)  /*!< Bit Value =(0):Normal of 32bit */
#define URT_STA_TCF_normal_h0                       ((uint16_t)0x0000)      /*!< Bit Value =(0):Normal of 16bit */
#define URT_STA_TCF_normal_b0                       ((uint8_t )0x00)        /*!< Bit Value =(0):Normal of 8bit */
#define URT_STA_TCF_happened_w                      ((uint32_t)0x00000004)  /*!< Bit Value =(1):Happened of 32bit */
#define URT_STA_TCF_happened_h0                     ((uint16_t)0x0004)      /*!< Bit Value =(1):Happened of 16bit */
#define URT_STA_TCF_happened_b0                     ((uint8_t )0x04)        /*!< Bit Value =(1):Happened of 8bit */

#define URT_STA_UGF_mask_w                          ((uint32_t)0x00000002)  /*!< Bit Mask of 32bit */
#define URT_STA_UGF_mask_h0                         ((uint16_t)0x0002)      /*!< Bit Mask of 16bit */
#define URT_STA_UGF_mask_b0                         ((uint8_t )0x02)        /*!< Bit Mask of 8bit */
#define URT_STA_UGF_normal_w                        ((uint32_t)0x00000000)  /*!< Bit Value =(0):Normal of 32bit */
#define URT_STA_UGF_normal_h0                       ((uint16_t)0x0000)      /*!< Bit Value =(0):Normal of 16bit */
#define URT_STA_UGF_normal_b0                       ((uint8_t )0x00)        /*!< Bit Value =(0):Normal of 8bit */
#define URT_STA_UGF_happened_w                      ((uint32_t)0x00000002)  /*!< Bit Value =(1):Happened of 32bit */
#define URT_STA_UGF_happened_h0                     ((uint16_t)0x0002)      /*!< Bit Value =(1):Happened of 16bit */
#define URT_STA_UGF_happened_b0                     ((uint8_t )0x02)        /*!< Bit Value =(1):Happened of 8bit */

///@}
/**
 ******************************************************************************
 * @name        URT_INT  [register's definitions]
 *              Offset[0x04]  URT interrupt enable register
 ******************************************************************************
 */
///@{
#define URT_INT_default                             ((uint32_t)0x00000000)  /*!< Reg Reset Default Value */

/* Bit fields of URT_INT */
#define URT_INT_ROVR_IE_mask_w                      ((uint32_t)0x00800000)  /*!< Bit Mask of 32bit */
#define URT_INT_ROVR_IE_mask_h1                     ((uint16_t)0x0080)      /*!< Bit Mask of 16bit */
#define URT_INT_ROVR_IE_mask_b2                     ((uint8_t )0x80)        /*!< Bit Mask of 8bit */
#define URT_INT_ROVR_IE_disable_w                   ((uint32_t)0x00000000)  /*!< Bit Value =(0):Disable of 32bit */
#define URT_INT_ROVR_IE_disable_h1                  ((uint16_t)0x0000)      /*!< Bit Value =(0):Disable of 16bit */
#define URT_INT_ROVR_IE_disable_b2                  ((uint8_t )0x00)        /*!< Bit Value =(0):Disable of 8bit */
#define URT_INT_ROVR_IE_enable_w                    ((uint32_t)0x00800000)  /*!< Bit Value =(1):Enable of 32bit */
#define URT_INT_ROVR_IE_enable_h1                   ((uint16_t)0x0080)      /*!< Bit Value =(1):Enable of 16bit */
#define URT_INT_ROVR_IE_enable_b2                   ((uint8_t )0x80)        /*!< Bit Value =(1):Enable of 8bit */

#define URT_INT_FE_IE_mask_w                        ((uint32_t)0x00200000)  /*!< Bit Mask of 32bit */
#define URT_INT_FE_IE_mask_h1                       ((uint16_t)0x0020)      /*!< Bit Mask of 16bit */
#define URT_INT_FE_IE_mask_b2                       ((uint8_t )0x20)        /*!< Bit Mask of 8bit */
#define URT_INT_FE_IE_disable_w                     ((uint32_t)0x00000000)  /*!< Bit Value =(0):Disable of 32bit */
#define URT_INT_FE_IE_disable_h1                    ((uint16_t)0x0000)      /*!< Bit Value =(0):Disable of 16bit */
#define URT_INT_FE_IE_disable_b2                    ((uint8_t )0x00)        /*!< Bit Value =(0):Disable of 8bit */
#define URT_INT_FE_IE_enable_w                      ((uint32_t)0x00200000)  /*!< Bit Value =(1):Enable of 32bit */
#define URT_INT_FE_IE_enable_h1                     ((uint16_t)0x0020)      /*!< Bit Value =(1):Enable of 16bit */
#define URT_INT_FE_IE_enable_b2                     ((uint8_t )0x20)        /*!< Bit Value =(1):Enable of 8bit */

#define URT_INT_PE_IE_mask_w                        ((uint32_t)0x00100000)  /*!< Bit Mask of 32bit */
#define URT_INT_PE_IE_mask_h1                       ((uint16_t)0x0010)      /*!< Bit Mask of 16bit */
#define URT_INT_PE_IE_mask_b2                       ((uint8_t )0x10)        /*!< Bit Mask of 8bit */
#define URT_INT_PE_IE_disable_w                     ((uint32_t)0x00000000)  /*!< Bit Value =(0):Disable of 32bit */
#define URT_INT_PE_IE_disable_h1                    ((uint16_t)0x0000)      /*!< Bit Value =(0):Disable of 16bit */
#define URT_INT_PE_IE_disable_b2                    ((uint8_t )0x00)        /*!< Bit Value =(0):Disable of 8bit */
#define URT_INT_PE_IE_enable_w                      ((uint32_t)0x00100000)  /*!< Bit Value =(1):Enable of 32bit */
#define URT_INT_PE_IE_enable_h1                     ((uint16_t)0x0010)      /*!< Bit Value =(1):Enable of 16bit */
#define URT_INT_PE_IE_enable_b2                     ((uint8_t )0x10)        /*!< Bit Value =(1):Enable of 8bit */

#define URT_INT_BRT_IE_mask_w                       ((uint32_t)0x00000800)  /*!< Bit Mask of 32bit */
#define URT_INT_BRT_IE_mask_h0                      ((uint16_t)0x0800)      /*!< Bit Mask of 16bit */
#define URT_INT_BRT_IE_mask_b1                      ((uint8_t )0x08)        /*!< Bit Mask of 8bit */
#define URT_INT_BRT_IE_disable_w                    ((uint32_t)0x00000000)  /*!< Bit Value =(0):Disable of 32bit */
#define URT_INT_BRT_IE_disable_h0                   ((uint16_t)0x0000)      /*!< Bit Value =(0):Disable of 16bit */
#define URT_INT_BRT_IE_disable_b1                   ((uint8_t )0x00)        /*!< Bit Value =(0):Disable of 8bit */
#define URT_INT_BRT_IE_enable_w                     ((uint32_t)0x00000800)  /*!< Bit Value =(1):Enable of 32bit */
#define URT_INT_BRT_IE_enable_h0                    ((uint16_t)0x0800)      /*!< Bit Value =(1):Enable of 16bit */
#define URT_INT_BRT_IE_enable_b1                    ((uint8_t )0x08)        /*!< Bit Value =(1):Enable of 8bit */

#define URT_INT_TX_IE_mask_w                        ((uint32_t)0x00000080)  /*!< Bit Mask of 32bit */
#define URT_INT_TX_IE_mask_h0                       ((uint16_t)0x0080)      /*!< Bit Mask of 16bit */
#define URT_INT_TX_IE_mask_b0                       ((uint8_t )0x80)        /*!< Bit Mask of 8bit */
#define URT_INT_TX_IE_disable_w                     ((uint32_t)0x00000000)  /*!< Bit Value =(0):Disable of 32bit */
#define URT_INT_TX_IE_disable_h0                    ((uint16_t)0x0000)      /*!< Bit Value =(0):Disable of 16bit */
#define URT_INT_TX_IE_disable_b0                    ((uint8_t )0x00)        /*!< Bit Value =(0):Disable of 8bit */
#define URT_INT_TX_IE_enable_w                      ((uint32_t)0x00000080)  /*!< Bit Value =(1):Enable of 32bit */
#define URT_INT_TX_IE_enable_h0                     ((uint16_t)0x0080)      /*!< Bit Value =(1):Enable of 16bit */
#define URT_INT_TX_IE_enable_b0                     ((uint8_t )0x80)        /*!< Bit Value =(1):Enable of 8bit */

#define URT_INT_RX_IE_mask_w                        ((uint32_t)0x00000040)  /*!< Bit Mask of 32bit */
#define URT_INT_RX_IE_mask_h0                       ((uint16_t)0x0040)      /*!< Bit Mask of 16bit */
#define URT_INT_RX_IE_mask_b0                       ((uint8_t )0x40)        /*!< Bit Mask of 8bit */
#define URT_INT_RX_IE_disable_w                     ((uint32_t)0x00000000)  /*!< Bit Value =(0):Disable of 32bit */
#define URT_INT_RX_IE_disable_h0                    ((uint16_t)0x0000)      /*!< Bit Value =(0):Disable of 16bit */
#define URT_INT_RX_IE_disable_b0                    ((uint8_t )0x00)        /*!< Bit Value =(0):Disable of 8bit */
#define URT_INT_RX_IE_enable_w                      ((uint32_t)0x00000040)  /*!< Bit Value =(1):Enable of 32bit */
#define URT_INT_RX_IE_enable_h0                     ((uint16_t)0x0040)      /*!< Bit Value =(1):Enable of 16bit */
#define URT_INT_RX_IE_enable_b0                     ((uint8_t )0x40)        /*!< Bit Value =(1):Enable of 8bit */

#define URT_INT_ERR_IE_mask_w                       ((uint32_t)0x00000008)  /*!< Bit Mask of 32bit */
#define URT_INT_ERR_IE_mask_h0                      ((uint16_t)0x0008)      /*!< Bit Mask of 16bit */
#define URT_INT_ERR_IE_mask_b0                      ((uint8_t )0x08)        /*!< Bit Mask of 8bit */
#define URT_INT_ERR_IE_disable_w                    ((uint32_t)0x00000000)  /*!< Bit Value =(0):Disable of 32bit */
#define URT_INT_ERR_IE_disable_h0                   ((uint16_t)0x0000)      /*!< Bit Value =(0):Disable of 16bit */
#define URT_INT_ERR_IE_disable_b0                   ((uint8_t )0x00)        /*!< Bit Value =(0):Disable of 8bit */
#define URT_INT_ERR_IE_enable_w                     ((uint32_t)0x00000008)  /*!< Bit Value =(1):Enable of 32bit */
#define URT_INT_ERR_IE_enable_h0                    ((uint16_t)0x0008)      /*!< Bit Value =(1):Enable of 16bit */
#define URT_INT_ERR_IE_enable_b0                    ((uint8_t )0x08)        /*!< Bit Value =(1):Enable of 8bit */

#define URT_INT_TC_IE_mask_w                        ((uint32_t)0x00000004)  /*!< Bit Mask of 32bit */
#define URT_INT_TC_IE_mask_h0                       ((uint16_t)0x0004)      /*!< Bit Mask of 16bit */
#define URT_INT_TC_IE_mask_b0                       ((uint8_t )0x04)        /*!< Bit Mask of 8bit */
#define URT_INT_TC_IE_disable_w                     ((uint32_t)0x00000000)  /*!< Bit Value =(0):Disable of 32bit */
#define URT_INT_TC_IE_disable_h0                    ((uint16_t)0x0000)      /*!< Bit Value =(0):Disable of 16bit */
#define URT_INT_TC_IE_disable_b0                    ((uint8_t )0x00)        /*!< Bit Value =(0):Disable of 8bit */
#define URT_INT_TC_IE_enable_w                      ((uint32_t)0x00000004)  /*!< Bit Value =(1):Enable of 32bit */
#define URT_INT_TC_IE_enable_h0                     ((uint16_t)0x0004)      /*!< Bit Value =(1):Enable of 16bit */
#define URT_INT_TC_IE_enable_b0                     ((uint8_t )0x04)        /*!< Bit Value =(1):Enable of 8bit */

#define URT_INT_UG_IE_mask_w                        ((uint32_t)0x00000002)  /*!< Bit Mask of 32bit */
#define URT_INT_UG_IE_mask_h0                       ((uint16_t)0x0002)      /*!< Bit Mask of 16bit */
#define URT_INT_UG_IE_mask_b0                       ((uint8_t )0x02)        /*!< Bit Mask of 8bit */
#define URT_INT_UG_IE_disable_w                     ((uint32_t)0x00000000)  /*!< Bit Value =(0):Disable of 32bit */
#define URT_INT_UG_IE_disable_h0                    ((uint16_t)0x0000)      /*!< Bit Value =(0):Disable of 16bit */
#define URT_INT_UG_IE_disable_b0                    ((uint8_t )0x00)        /*!< Bit Value =(0):Disable of 8bit */
#define URT_INT_UG_IE_enable_w                      ((uint32_t)0x00000002)  /*!< Bit Value =(1):Enable of 32bit */
#define URT_INT_UG_IE_enable_h0                     ((uint16_t)0x0002)      /*!< Bit Value =(1):Enable of 16bit */
#define URT_INT_UG_IE_enable_b0                     ((uint8_t )0x02)        /*!< Bit Value =(1):Enable of 8bit */

#define URT_INT_IEA_mask_w                          ((uint32_t)0x00000001)  /*!< Bit Mask of 32bit */
#define URT_INT_IEA_mask_h0                         ((uint16_t)0x0001)      /*!< Bit Mask of 16bit */
#define URT_INT_IEA_mask_b0                         ((uint8_t )0x01)        /*!< Bit Mask of 8bit */
#define URT_INT_IEA_disable_w                       ((uint32_t)0x00000000)  /*!< Bit Value =(0):Disable of 32bit */
#define URT_INT_IEA_disable_h0                      ((uint16_t)0x0000)      /*!< Bit Value =(0):Disable of 16bit */
#define URT_INT_IEA_disable_b0                      ((uint8_t )0x00)        /*!< Bit Value =(0):Disable of 8bit */
#define URT_INT_IEA_enable_w                        ((uint32_t)0x00000001)  /*!< Bit Value =(1):Enable of 32bit */
#define URT_INT_IEA_enable_h0                       ((uint16_t)0x0001)      /*!< Bit Value =(1):Enable of 16bit */
#define URT_INT_IEA_enable_b0                       ((uint8_t )0x01)        /*!< Bit Value =(1):Enable of 8bit */

///@}
/**
 ******************************************************************************
 * @name        URT_CLK  [register's definitions]
 *              Offset[0x08]  URT clock source register
 ******************************************************************************
 */
///@{
#define URT_CLK_default                             ((uint32_t)0x00000000)  /*!< Reg Reset Default Value */

/* Bit fields of URT_CLK */
#define URT_CLK_BR_MDS_mask_w                       ((uint32_t)0x02000000)  /*!< Bit Mask of 32bit */
#define URT_CLK_BR_MDS_mask_h1                      ((uint16_t)0x0200)      /*!< Bit Mask of 16bit */
#define URT_CLK_BR_MDS_mask_b3                      ((uint8_t )0x02)        /*!< Bit Mask of 8bit */
#define URT_CLK_BR_MDS_separated_w                  ((uint32_t)0x00000000)  /*!< Bit Value =(0):Separated of 32bit */
#define URT_CLK_BR_MDS_separated_h1                 ((uint16_t)0x0000)      /*!< Bit Value =(0):Separated of 16bit */
#define URT_CLK_BR_MDS_separated_b3                 ((uint8_t )0x00)        /*!< Bit Value =(0):Separated of 8bit */
#define URT_CLK_BR_MDS_combined_w                   ((uint32_t)0x02000000)  /*!< Bit Value =(1):Combined of 32bit */
#define URT_CLK_BR_MDS_combined_h1                  ((uint16_t)0x0200)      /*!< Bit Value =(1):Combined of 16bit */
#define URT_CLK_BR_MDS_combined_b3                  ((uint8_t )0x02)        /*!< Bit Value =(1):Combined of 8bit */

#define URT_CLK_BR_EN_mask_w                        ((uint32_t)0x01000000)  /*!< Bit Mask of 32bit */
#define URT_CLK_BR_EN_mask_h1                       ((uint16_t)0x0100)      /*!< Bit Mask of 16bit */
#define URT_CLK_BR_EN_mask_b3                       ((uint8_t )0x01)        /*!< Bit Mask of 8bit */
#define URT_CLK_BR_EN_disable_w                     ((uint32_t)0x00000000)  /*!< Bit Value =(0):Disable of 32bit */
#define URT_CLK_BR_EN_disable_h1                    ((uint16_t)0x0000)      /*!< Bit Value =(0):Disable of 16bit */
#define URT_CLK_BR_EN_disable_b3                    ((uint8_t )0x00)        /*!< Bit Value =(0):Disable of 8bit */
#define URT_CLK_BR_EN_enable_w                      ((uint32_t)0x01000000)  /*!< Bit Value =(1):Enable of 32bit */
#define URT_CLK_BR_EN_enable_h1                     ((uint16_t)0x0100)      /*!< Bit Value =(1):Enable of 16bit */
#define URT_CLK_BR_EN_enable_b3                     ((uint8_t )0x01)        /*!< Bit Value =(1):Enable of 8bit */

#define URT_CLK_CK_SEL_mask_w                       ((uint32_t)0x00000006)  /*!< Bit Mask of 32bit */
#define URT_CLK_CK_SEL_mask_h0                      ((uint16_t)0x0006)      /*!< Bit Mask of 16bit */
#define URT_CLK_CK_SEL_mask_b0                      ((uint8_t )0x06)        /*!< Bit Mask of 8bit */
#define URT_CLK_CK_SEL_proc_w                       ((uint32_t)0x00000000)  /*!< Bit Value =(0x0):PROC of 32bit */
#define URT_CLK_CK_SEL_proc_h0                      ((uint16_t)0x0000)      /*!< Bit Value =(0x0):PROC of 16bit */
#define URT_CLK_CK_SEL_proc_b0                      ((uint8_t )0x00)        /*!< Bit Value =(0x0):PROC of 8bit */
#define URT_CLK_CK_SEL_ck_ls_w                      ((uint32_t)0x00000004)  /*!< Bit Value =(0x2):CK_LS of 32bit */
#define URT_CLK_CK_SEL_ck_ls_h0                     ((uint16_t)0x0004)      /*!< Bit Value =(0x2):CK_LS of 16bit */
#define URT_CLK_CK_SEL_ck_ls_b0                     ((uint8_t )0x04)        /*!< Bit Value =(0x2):CK_LS of 8bit */
#define URT_CLK_CK_SEL_tm00_trgo_w                  ((uint32_t)0x00000006)  /*!< Bit Value =(0x3):TM00_TRGO of 32bit */
#define URT_CLK_CK_SEL_tm00_trgo_h0                 ((uint16_t)0x0006)      /*!< Bit Value =(0x3):TM00_TRGO of 16bit */
#define URT_CLK_CK_SEL_tm00_trgo_b0                 ((uint8_t )0x06)        /*!< Bit Value =(0x3):TM00_TRGO of 8bit */

///@}
/**
 ******************************************************************************
 * @name        URT_STA2  [register's definitions]
 *              Offset[0x0C]  URT status register 2
 ******************************************************************************
 */
///@{
#define URT_STA2_default                            ((uint32_t)0x00000000)  /*!< Reg Reset Default Value */

/* Bit fields of URT_STA2 */
#define URT_STA2_PAR_mask_w                         ((uint32_t)0x00000002)  /*!< Bit Mask of 32bit */
#define URT_STA2_PAR_mask_h0                        ((uint16_t)0x0002)      /*!< Bit Mask of 16bit */
#define URT_STA2_PAR_mask_b0                        ((uint8_t )0x02)        /*!< Bit Mask of 8bit */
#define URT_STA2_PAR_shift_w                        (1)                     /*!< Bit Shift of 32bit */
#define URT_STA2_PAR_shift_h0                       (1)                     /*!< Bit Shift of 16bit */
#define URT_STA2_PAR_shift_b0                       (1)                     /*!< Bit Shift of 8bit */

#define URT_STA2_BUSYF_mask_w                       ((uint32_t)0x00000001)  /*!< Bit Mask of 32bit */
#define URT_STA2_BUSYF_mask_h0                      ((uint16_t)0x0001)      /*!< Bit Mask of 16bit */
#define URT_STA2_BUSYF_mask_b0                      ((uint8_t )0x01)        /*!< Bit Mask of 8bit */
#define URT_STA2_BUSYF_normal_w                     ((uint32_t)0x00000000)  /*!< Bit Value =(0):Normal of 32bit */
#define URT_STA2_BUSYF_normal_h0                    ((uint16_t)0x0000)      /*!< Bit Value =(0):Normal of 16bit */
#define URT_STA2_BUSYF_normal_b0                    ((uint8_t )0x00)        /*!< Bit Value =(0):Normal of 8bit */
#define URT_STA2_BUSYF_busy_w                       ((uint32_t)0x00000001)  /*!< Bit Value =(1):Busy of 32bit */
#define URT_STA2_BUSYF_busy_h0                      ((uint16_t)0x0001)      /*!< Bit Value =(1):Busy of 16bit */
#define URT_STA2_BUSYF_busy_b0                      ((uint8_t )0x01)        /*!< Bit Value =(1):Busy of 8bit */

///@}
/**
 ******************************************************************************
 * @name        URT_CR0  [register's definitions]
 *              Offset[0x10]  URT control register 0
 ******************************************************************************
 */
///@{
#define URT_CR0_default                             ((uint32_t)0x00000000)  /*!< Reg Reset Default Value */

/* Bit fields of URT_CR0 */
#define URT_CR0_LBM_EN_mask_w                       ((uint32_t)0x00800000)  /*!< Bit Mask of 32bit */
#define URT_CR0_LBM_EN_mask_h1                      ((uint16_t)0x0080)      /*!< Bit Mask of 16bit */
#define URT_CR0_LBM_EN_mask_b2                      ((uint8_t )0x80)        /*!< Bit Mask of 8bit */
#define URT_CR0_LBM_EN_disable_w                    ((uint32_t)0x00000000)  /*!< Bit Value =(0):Disable of 32bit */
#define URT_CR0_LBM_EN_disable_h1                   ((uint16_t)0x0000)      /*!< Bit Value =(0):Disable of 16bit */
#define URT_CR0_LBM_EN_disable_b2                   ((uint8_t )0x00)        /*!< Bit Value =(0):Disable of 8bit */
#define URT_CR0_LBM_EN_enable_w                     ((uint32_t)0x00800000)  /*!< Bit Value =(1):Enable of 32bit */
#define URT_CR0_LBM_EN_enable_h1                    ((uint16_t)0x0080)      /*!< Bit Value =(1):Enable of 16bit */
#define URT_CR0_LBM_EN_enable_b2                    ((uint8_t )0x80)        /*!< Bit Value =(1):Enable of 8bit */

#define URT_CR0_TX_INV_mask_w                       ((uint32_t)0x00000800)  /*!< Bit Mask of 32bit */
#define URT_CR0_TX_INV_mask_h0                      ((uint16_t)0x0800)      /*!< Bit Mask of 16bit */
#define URT_CR0_TX_INV_mask_b1                      ((uint8_t )0x08)        /*!< Bit Mask of 8bit */
#define URT_CR0_TX_INV_disable_w                    ((uint32_t)0x00000000)  /*!< Bit Value =(0):Disable of 32bit */
#define URT_CR0_TX_INV_disable_h0                   ((uint16_t)0x0000)      /*!< Bit Value =(0):Disable of 16bit */
#define URT_CR0_TX_INV_disable_b1                   ((uint8_t )0x00)        /*!< Bit Value =(0):Disable of 8bit */
#define URT_CR0_TX_INV_enable_w                     ((uint32_t)0x00000800)  /*!< Bit Value =(1):Enable of 32bit */
#define URT_CR0_TX_INV_enable_h0                    ((uint16_t)0x0800)      /*!< Bit Value =(1):Enable of 16bit */
#define URT_CR0_TX_INV_enable_b1                    ((uint8_t )0x08)        /*!< Bit Value =(1):Enable of 8bit */

#define URT_CR0_RX_INV_mask_w                       ((uint32_t)0x00000400)  /*!< Bit Mask of 32bit */
#define URT_CR0_RX_INV_mask_h0                      ((uint16_t)0x0400)      /*!< Bit Mask of 16bit */
#define URT_CR0_RX_INV_mask_b1                      ((uint8_t )0x04)        /*!< Bit Mask of 8bit */
#define URT_CR0_RX_INV_disable_w                    ((uint32_t)0x00000000)  /*!< Bit Value =(0):Disable of 32bit */
#define URT_CR0_RX_INV_disable_h0                   ((uint16_t)0x0000)      /*!< Bit Value =(0):Disable of 16bit */
#define URT_CR0_RX_INV_disable_b1                   ((uint8_t )0x00)        /*!< Bit Value =(0):Disable of 8bit */
#define URT_CR0_RX_INV_enable_w                     ((uint32_t)0x00000400)  /*!< Bit Value =(1):Enable of 32bit */
#define URT_CR0_RX_INV_enable_h0                    ((uint16_t)0x0400)      /*!< Bit Value =(1):Enable of 16bit */
#define URT_CR0_RX_INV_enable_b1                    ((uint8_t )0x04)        /*!< Bit Value =(1):Enable of 8bit */

#define URT_CR0_IO_SWP_mask_w                       ((uint32_t)0x00000100)  /*!< Bit Mask of 32bit */
#define URT_CR0_IO_SWP_mask_h0                      ((uint16_t)0x0100)      /*!< Bit Mask of 16bit */
#define URT_CR0_IO_SWP_mask_b1                      ((uint8_t )0x01)        /*!< Bit Mask of 8bit */
#define URT_CR0_IO_SWP_disable_w                    ((uint32_t)0x00000000)  /*!< Bit Value =(0):Disable of 32bit */
#define URT_CR0_IO_SWP_disable_h0                   ((uint16_t)0x0000)      /*!< Bit Value =(0):Disable of 16bit */
#define URT_CR0_IO_SWP_disable_b1                   ((uint8_t )0x00)        /*!< Bit Value =(0):Disable of 8bit */
#define URT_CR0_IO_SWP_enable_w                     ((uint32_t)0x00000100)  /*!< Bit Value =(1):Enable of 32bit */
#define URT_CR0_IO_SWP_enable_h0                    ((uint16_t)0x0100)      /*!< Bit Value =(1):Enable of 16bit */
#define URT_CR0_IO_SWP_enable_b1                    ((uint8_t )0x01)        /*!< Bit Value =(1):Enable of 8bit */

#define URT_CR0_EN_mask_w                           ((uint32_t)0x00000001)  /*!< Bit Mask of 32bit */
#define URT_CR0_EN_mask_h0                          ((uint16_t)0x0001)      /*!< Bit Mask of 16bit */
#define URT_CR0_EN_mask_b0                          ((uint8_t )0x01)        /*!< Bit Mask of 8bit */
#define URT_CR0_EN_disable_w                        ((uint32_t)0x00000000)  /*!< Bit Value =(0):Disable of 32bit */
#define URT_CR0_EN_disable_h0                       ((uint16_t)0x0000)      /*!< Bit Value =(0):Disable of 16bit */
#define URT_CR0_EN_disable_b0                       ((uint8_t )0x00)        /*!< Bit Value =(0):Disable of 8bit */
#define URT_CR0_EN_enable_w                         ((uint32_t)0x00000001)  /*!< Bit Value =(1):Enable of 32bit */
#define URT_CR0_EN_enable_h0                        ((uint16_t)0x0001)      /*!< Bit Value =(1):Enable of 16bit */
#define URT_CR0_EN_enable_b0                        ((uint8_t )0x01)        /*!< Bit Value =(1):Enable of 8bit */

///@}
/**
 ******************************************************************************
 * @name        URT_CR1  [register's definitions]
 *              Offset[0x14]  URT control register 1
 ******************************************************************************
 */
///@{
#define URT_CR1_default                             ((uint32_t)0x0F400000)  /*!< Reg Reset Default Value */

/* Bit fields of URT_CR1 */
#define URT_CR1_TXOS_NUM_mask_w                     ((uint32_t)0x1F000000)  /*!< Bit Mask of 32bit */
#define URT_CR1_TXOS_NUM_mask_h1                    ((uint16_t)0x1F00)      /*!< Bit Mask of 16bit */
#define URT_CR1_TXOS_NUM_mask_b3                    ((uint8_t )0x1F)        /*!< Bit Mask of 8bit */
#define URT_CR1_TXOS_NUM_shift_w                    (24)                    /*!< Bit Shift of 32bit */
#define URT_CR1_TXOS_NUM_shift_h1                   (8)                     /*!< Bit Shift of 16bit */
#define URT_CR1_TXOS_NUM_shift_b3                   (0)                     /*!< Bit Shift of 8bit */

#define URT_CR1_TXSTP_LEN_mask_w                    ((uint32_t)0x00C00000)  /*!< Bit Mask of 32bit */
#define URT_CR1_TXSTP_LEN_mask_h1                   ((uint16_t)0x00C0)      /*!< Bit Mask of 16bit */
#define URT_CR1_TXSTP_LEN_mask_b2                   ((uint8_t )0xC0)        /*!< Bit Mask of 8bit */
#define URT_CR1_TXSTP_LEN_1bit_w                    ((uint32_t)0x00400000)  /*!< Bit Value =(0x1):1bit of 32bit */
#define URT_CR1_TXSTP_LEN_1bit_h1                   ((uint16_t)0x0040)      /*!< Bit Value =(0x1):1bit of 16bit */
#define URT_CR1_TXSTP_LEN_1bit_b2                   ((uint8_t )0x40)        /*!< Bit Value =(0x1):1bit of 8bit */
#define URT_CR1_TXSTP_LEN_2bit_w                    ((uint32_t)0x00C00000)  /*!< Bit Value =(0x3):2bit of 32bit */
#define URT_CR1_TXSTP_LEN_2bit_h1                   ((uint16_t)0x00C0)      /*!< Bit Value =(0x3):2bit of 16bit */
#define URT_CR1_TXSTP_LEN_2bit_b2                   ((uint8_t )0xC0)        /*!< Bit Value =(0x3):2bit of 8bit */

#define URT_CR1_TXPAR_STK_mask_w                    ((uint32_t)0x00100000)  /*!< Bit Mask of 32bit */
#define URT_CR1_TXPAR_STK_mask_h1                   ((uint16_t)0x0010)      /*!< Bit Mask of 16bit */
#define URT_CR1_TXPAR_STK_mask_b2                   ((uint8_t )0x10)        /*!< Bit Mask of 8bit */
#define URT_CR1_TXPAR_STK_disable_w                 ((uint32_t)0x00000000)  /*!< Bit Value =(0):Disable of 32bit */
#define URT_CR1_TXPAR_STK_disable_h1                ((uint16_t)0x0000)      /*!< Bit Value =(0):Disable of 16bit */
#define URT_CR1_TXPAR_STK_disable_b2                ((uint8_t )0x00)        /*!< Bit Value =(0):Disable of 8bit */
#define URT_CR1_TXPAR_STK_enable_w                  ((uint32_t)0x00100000)  /*!< Bit Value =(1):Enable of 32bit */
#define URT_CR1_TXPAR_STK_enable_h1                 ((uint16_t)0x0010)      /*!< Bit Value =(1):Enable of 16bit */
#define URT_CR1_TXPAR_STK_enable_b2                 ((uint8_t )0x10)        /*!< Bit Value =(1):Enable of 8bit */

#define URT_CR1_TXPAR_POL_mask_w                    ((uint32_t)0x00080000)  /*!< Bit Mask of 32bit */
#define URT_CR1_TXPAR_POL_mask_h1                   ((uint16_t)0x0008)      /*!< Bit Mask of 16bit */
#define URT_CR1_TXPAR_POL_mask_b2                   ((uint8_t )0x08)        /*!< Bit Mask of 8bit */
#define URT_CR1_TXPAR_POL_even_w                    ((uint32_t)0x00000000)  /*!< Bit Value =(0x0):Even of 32bit */
#define URT_CR1_TXPAR_POL_even_h1                   ((uint16_t)0x0000)      /*!< Bit Value =(0x0):Even of 16bit */
#define URT_CR1_TXPAR_POL_even_b2                   ((uint8_t )0x00)        /*!< Bit Value =(0x0):Even of 8bit */
#define URT_CR1_TXPAR_POL_odd_w                     ((uint32_t)0x00080000)  /*!< Bit Value =(0x1):Odd of 32bit */
#define URT_CR1_TXPAR_POL_odd_h1                    ((uint16_t)0x0008)      /*!< Bit Value =(0x1):Odd of 16bit */
#define URT_CR1_TXPAR_POL_odd_b2                    ((uint8_t )0x08)        /*!< Bit Value =(0x1):Odd of 8bit */

#define URT_CR1_TXPAR_EN_mask_w                     ((uint32_t)0x00040000)  /*!< Bit Mask of 32bit */
#define URT_CR1_TXPAR_EN_mask_h1                    ((uint16_t)0x0004)      /*!< Bit Mask of 16bit */
#define URT_CR1_TXPAR_EN_mask_b2                    ((uint8_t )0x04)        /*!< Bit Mask of 8bit */
#define URT_CR1_TXPAR_EN_disable_w                  ((uint32_t)0x00000000)  /*!< Bit Value =(0):Disable of 32bit */
#define URT_CR1_TXPAR_EN_disable_h1                 ((uint16_t)0x0000)      /*!< Bit Value =(0):Disable of 16bit */
#define URT_CR1_TXPAR_EN_disable_b2                 ((uint8_t )0x00)        /*!< Bit Value =(0):Disable of 8bit */
#define URT_CR1_TXPAR_EN_enable_w                   ((uint32_t)0x00040000)  /*!< Bit Value =(1):Enable of 32bit */
#define URT_CR1_TXPAR_EN_enable_h1                  ((uint16_t)0x0004)      /*!< Bit Value =(1):Enable of 16bit */
#define URT_CR1_TXPAR_EN_enable_b2                  ((uint8_t )0x04)        /*!< Bit Value =(1):Enable of 8bit */

#define URT_CR1_TXDSIZE_mask_w                      ((uint32_t)0x00030000)  /*!< Bit Mask of 32bit */
#define URT_CR1_TXDSIZE_mask_h1                     ((uint16_t)0x0003)      /*!< Bit Mask of 16bit */
#define URT_CR1_TXDSIZE_mask_b2                     ((uint8_t )0x03)        /*!< Bit Mask of 8bit */
#define URT_CR1_TXDSIZE_8bit_w                      ((uint32_t)0x00000000)  /*!< Bit Value =(0x0):8bit of 32bit */
#define URT_CR1_TXDSIZE_8bit_h1                     ((uint16_t)0x0000)      /*!< Bit Value =(0x0):8bit of 16bit */
#define URT_CR1_TXDSIZE_8bit_b2                     ((uint8_t )0x00)        /*!< Bit Value =(0x0):8bit of 8bit */
#define URT_CR1_TXDSIZE_7bit_w                      ((uint32_t)0x00010000)  /*!< Bit Value =(0x1):7bit of 32bit */
#define URT_CR1_TXDSIZE_7bit_h1                     ((uint16_t)0x0001)      /*!< Bit Value =(0x1):7bit of 16bit */
#define URT_CR1_TXDSIZE_7bit_b2                     ((uint8_t )0x01)        /*!< Bit Value =(0x1):7bit of 8bit */

#define URT_CR1_RXPAR_STK_mask_w                    ((uint32_t)0x00000010)  /*!< Bit Mask of 32bit */
#define URT_CR1_RXPAR_STK_mask_h0                   ((uint16_t)0x0010)      /*!< Bit Mask of 16bit */
#define URT_CR1_RXPAR_STK_mask_b0                   ((uint8_t )0x10)        /*!< Bit Mask of 8bit */
#define URT_CR1_RXPAR_STK_disable_w                 ((uint32_t)0x00000000)  /*!< Bit Value =(0):Disable of 32bit */
#define URT_CR1_RXPAR_STK_disable_h0                ((uint16_t)0x0000)      /*!< Bit Value =(0):Disable of 16bit */
#define URT_CR1_RXPAR_STK_disable_b0                ((uint8_t )0x00)        /*!< Bit Value =(0):Disable of 8bit */
#define URT_CR1_RXPAR_STK_enable_w                  ((uint32_t)0x00000010)  /*!< Bit Value =(1):Enable of 32bit */
#define URT_CR1_RXPAR_STK_enable_h0                 ((uint16_t)0x0010)      /*!< Bit Value =(1):Enable of 16bit */
#define URT_CR1_RXPAR_STK_enable_b0                 ((uint8_t )0x10)        /*!< Bit Value =(1):Enable of 8bit */

#define URT_CR1_RXPAR_POL_mask_w                    ((uint32_t)0x00000008)  /*!< Bit Mask of 32bit */
#define URT_CR1_RXPAR_POL_mask_h0                   ((uint16_t)0x0008)      /*!< Bit Mask of 16bit */
#define URT_CR1_RXPAR_POL_mask_b0                   ((uint8_t )0x08)        /*!< Bit Mask of 8bit */
#define URT_CR1_RXPAR_POL_even_w                    ((uint32_t)0x00000000)  /*!< Bit Value =(0x0):Even of 32bit */
#define URT_CR1_RXPAR_POL_even_h0                   ((uint16_t)0x0000)      /*!< Bit Value =(0x0):Even of 16bit */
#define URT_CR1_RXPAR_POL_even_b0                   ((uint8_t )0x00)        /*!< Bit Value =(0x0):Even of 8bit */
#define URT_CR1_RXPAR_POL_odd_w                     ((uint32_t)0x00000008)  /*!< Bit Value =(0x1):Odd of 32bit */
#define URT_CR1_RXPAR_POL_odd_h0                    ((uint16_t)0x0008)      /*!< Bit Value =(0x1):Odd of 16bit */
#define URT_CR1_RXPAR_POL_odd_b0                    ((uint8_t )0x08)        /*!< Bit Value =(0x1):Odd of 8bit */

///@}
/**
 ******************************************************************************
 * @name        URT_CR2  [register's definitions]
 *              Offset[0x18]  URT control register 2
 ******************************************************************************
 */
///@{
#define URT_CR2_default                             ((uint32_t)0x00000000)  /*!< Reg Reset Default Value */

/* Bit fields of URT_CR2 */
#define URT_CR2_TX_EN_mask_w                        ((uint32_t)0x00000008)  /*!< Bit Mask of 32bit */
#define URT_CR2_TX_EN_mask_h0                       ((uint16_t)0x0008)      /*!< Bit Mask of 16bit */
#define URT_CR2_TX_EN_mask_b0                       ((uint8_t )0x08)        /*!< Bit Mask of 8bit */
#define URT_CR2_TX_EN_disable_w                     ((uint32_t)0x00000000)  /*!< Bit Value =(0):Disable of 32bit */
#define URT_CR2_TX_EN_disable_h0                    ((uint16_t)0x0000)      /*!< Bit Value =(0):Disable of 16bit */
#define URT_CR2_TX_EN_disable_b0                    ((uint8_t )0x00)        /*!< Bit Value =(0):Disable of 8bit */
#define URT_CR2_TX_EN_enable_w                      ((uint32_t)0x00000008)  /*!< Bit Value =(1):Enable of 32bit */
#define URT_CR2_TX_EN_enable_h0                     ((uint16_t)0x0008)      /*!< Bit Value =(1):Enable of 16bit */
#define URT_CR2_TX_EN_enable_b0                     ((uint8_t )0x08)        /*!< Bit Value =(1):Enable of 8bit */

#define URT_CR2_RX_EN_mask_w                        ((uint32_t)0x00000004)  /*!< Bit Mask of 32bit */
#define URT_CR2_RX_EN_mask_h0                       ((uint16_t)0x0004)      /*!< Bit Mask of 16bit */
#define URT_CR2_RX_EN_mask_b0                       ((uint8_t )0x04)        /*!< Bit Mask of 8bit */
#define URT_CR2_RX_EN_disable_w                     ((uint32_t)0x00000000)  /*!< Bit Value =(0):Disable of 32bit */
#define URT_CR2_RX_EN_disable_h0                    ((uint16_t)0x0000)      /*!< Bit Value =(0):Disable of 16bit */
#define URT_CR2_RX_EN_disable_b0                    ((uint8_t )0x00)        /*!< Bit Value =(0):Disable of 8bit */
#define URT_CR2_RX_EN_enable_w                      ((uint32_t)0x00000004)  /*!< Bit Value =(1):Enable of 32bit */
#define URT_CR2_RX_EN_enable_h0                     ((uint16_t)0x0004)      /*!< Bit Value =(1):Enable of 16bit */
#define URT_CR2_RX_EN_enable_b0                     ((uint8_t )0x04)        /*!< Bit Value =(1):Enable of 8bit */

///@}
/**
 ******************************************************************************
 * @name        URT_RLR  [register's definitions]
 *              Offset[0x24]  URT baud-rate clock counter reload register
 ******************************************************************************
 */
///@{
#define URT_RLR_default                             ((uint32_t)0x00000000)  /*!< Reg Reset Default Value */

/* Bit fields of URT_RLR */
#define URT_RLR_PSR_mask_w                          ((uint32_t)0x00003F00)  /*!< Bit Mask of 32bit */
#define URT_RLR_PSR_mask_h0                         ((uint16_t)0x3F00)      /*!< Bit Mask of 16bit */
#define URT_RLR_PSR_mask_b1                         ((uint8_t )0x3F)        /*!< Bit Mask of 8bit */
#define URT_RLR_PSR_shift_w                         (8)                     /*!< Bit Shift of 32bit */
#define URT_RLR_PSR_shift_h0                        (8)                     /*!< Bit Shift of 16bit */
#define URT_RLR_PSR_shift_b1                        (0)                     /*!< Bit Shift of 8bit */

#define URT_RLR_RLR_mask_w                          ((uint32_t)0x000000FF)  /*!< Bit Mask of 32bit */
#define URT_RLR_RLR_mask_h0                         ((uint16_t)0x00FF)      /*!< Bit Mask of 16bit */
#define URT_RLR_RLR_mask_b0                         ((uint8_t )0xFF)        /*!< Bit Mask of 8bit */
#define URT_RLR_RLR_shift_w                         (0)                     /*!< Bit Shift of 32bit */
#define URT_RLR_RLR_shift_h0                        (0)                     /*!< Bit Shift of 16bit */
#define URT_RLR_RLR_shift_b0                        (0)                     /*!< Bit Shift of 8bit */

///@}
/**
 ******************************************************************************
 * @name        URT_CNT  [register's definitions]
 *              Offset[0x28]  URT baud-rate clock counter register
 ******************************************************************************
 */
///@{
#define URT_CNT_default                             ((uint32_t)0x00000000)  /*!< Reg Reset Default Value */

/* Bit fields of URT_CNT */
#define URT_CNT_PSC_mask_w                          ((uint32_t)0x00003F00)  /*!< Bit Mask of 32bit */
#define URT_CNT_PSC_mask_h0                         ((uint16_t)0x3F00)      /*!< Bit Mask of 16bit */
#define URT_CNT_PSC_mask_b1                         ((uint8_t )0x3F)        /*!< Bit Mask of 8bit */
#define URT_CNT_PSC_shift_w                         (8)                     /*!< Bit Shift of 32bit */
#define URT_CNT_PSC_shift_h0                        (8)                     /*!< Bit Shift of 16bit */
#define URT_CNT_PSC_shift_b1                        (0)                     /*!< Bit Shift of 8bit */

#define URT_CNT_CNT_mask_w                          ((uint32_t)0x000000FF)  /*!< Bit Mask of 32bit */
#define URT_CNT_CNT_mask_h0                         ((uint16_t)0x00FF)      /*!< Bit Mask of 16bit */
#define URT_CNT_CNT_mask_b0                         ((uint8_t )0xFF)        /*!< Bit Mask of 8bit */
#define URT_CNT_CNT_shift_w                         (0)                     /*!< Bit Shift of 32bit */
#define URT_CNT_CNT_shift_h0                        (0)                     /*!< Bit Shift of 16bit */
#define URT_CNT_CNT_shift_b0                        (0)                     /*!< Bit Shift of 8bit */

///@}
/**
 ******************************************************************************
 * @name        URT_RDAT  [register's definitions]
 *              Offset[0x30]  URT RX data register
 ******************************************************************************
 */
///@{
#define URT_RDAT_default                            ((uint32_t)0x00000000)  /*!< Reg Reset Default Value */

/* Bit fields of URT_RDAT */
#define URT_RDAT_RDAT_mask_w                        ((uint32_t)0x000000FF)  /*!< Bit Mask of 32bit */
#define URT_RDAT_RDAT_mask_h0                       ((uint16_t)0x00FF)      /*!< Bit Mask of 16bit */
#define URT_RDAT_RDAT_mask_b0                       ((uint8_t )0xFF)        /*!< Bit Mask of 8bit */
#define URT_RDAT_RDAT_shift_w                       (0)                     /*!< Bit Shift of 32bit */
#define URT_RDAT_RDAT_shift_h0                      (0)                     /*!< Bit Shift of 16bit */
#define URT_RDAT_RDAT_shift_b0                      (0)                     /*!< Bit Shift of 8bit */

///@}
/**
 ******************************************************************************
 * @name        URT_TDAT  [register's definitions]
 *              Offset[0x34]  URT TX data register
 ******************************************************************************
 */
///@{
#define URT_TDAT_default                            ((uint32_t)0x00000000)  /*!< Reg Reset Default Value */

/* Bit fields of URT_TDAT */
#define URT_TDAT_TDAT_mask_w                        ((uint32_t)0x000000FF)  /*!< Bit Mask of 32bit */
#define URT_TDAT_TDAT_mask_h0                       ((uint16_t)0x00FF)      /*!< Bit Mask of 16bit */
#define URT_TDAT_TDAT_mask_b0                       ((uint8_t )0xFF)        /*!< Bit Mask of 8bit */
#define URT_TDAT_TDAT_shift_w                       (0)                     /*!< Bit Shift of 32bit */
#define URT_TDAT_TDAT_shift_h0                      (0)                     /*!< Bit Shift of 16bit */
#define URT_TDAT_TDAT_shift_b0                      (0)                     /*!< Bit Shift of 8bit */

///@}
/**
 ******************************************************************************
 * @name        URT_SBUF  [register's definitions]
 *              Offset[0x3C]  URT data shift buffer register
 ******************************************************************************
 */
///@{
#define URT_SBUF_default                            ((uint32_t)0x00000000)  /*!< Reg Reset Default Value */

/* Bit fields of URT_SBUF */
#define URT_SBUF_TSBUF_mask_w                       ((uint32_t)0x0000FF00)  /*!< Bit Mask of 32bit */
#define URT_SBUF_TSBUF_mask_h0                      ((uint16_t)0xFF00)      /*!< Bit Mask of 16bit */
#define URT_SBUF_TSBUF_mask_b1                      ((uint8_t )0xFF)        /*!< Bit Mask of 8bit */
#define URT_SBUF_TSBUF_shift_w                      (8)                     /*!< Bit Shift of 32bit */
#define URT_SBUF_TSBUF_shift_h0                     (8)                     /*!< Bit Shift of 16bit */
#define URT_SBUF_TSBUF_shift_b1                     (0)                     /*!< Bit Shift of 8bit */

#define URT_SBUF_RSBUF_mask_w                       ((uint32_t)0x000000FF)  /*!< Bit Mask of 32bit */
#define URT_SBUF_RSBUF_mask_h0                      ((uint16_t)0x00FF)      /*!< Bit Mask of 16bit */
#define URT_SBUF_RSBUF_mask_b0                      ((uint8_t )0xFF)        /*!< Bit Mask of 8bit */
#define URT_SBUF_RSBUF_shift_w                      (0)                     /*!< Bit Shift of 32bit */
#define URT_SBUF_RSBUF_shift_h0                     (0)                     /*!< Bit Shift of 16bit */
#define URT_SBUF_RSBUF_shift_b0                     (0)                     /*!< Bit Shift of 8bit */

///@}

#endif  // _MG32_URT_H

/*----------------------------------------------------------------------------*/
/*                           End of file MG32_URT.h                           */
/*----------------------------------------------------------------------------*/
