/**
 ******************************************************************************
 *
 * @file        MG32_APX_CCL_Init.h
 *
 * @brief       This file is to configure APB CCL0 output setting.
 *              Device : MG32F02U128
 * @par         Project
 *              MG32 
 * @version     V1.01
 * @date        2026/01/27
 * @author      MG32CoGen: 2.0.0.32 , 2026/2/9 上午 10:17 
 * @copyright   Copyright (c) 2022 MegaWin Technology Co., Ltd.
 *              All rights reserved.
 *
 ******************************************************************************
 * @par     Disclaimer 
 *    The Demo software is provided "AS IS"  without any warranty, either 
 *    expressed or implied, including, but not limited to, the implied warranties 
 *    of merchantability and fitness for a particular purpose.  The author will 
 *    not be liable for any special, incidental, consequential or indirect 
 *    damages due to loss of data or any other reason. 
 *    These statements agree with the world wide and local dictated laws about 
 *    authorship and violence against these laws. 
 *******************************************************************************
 *******************************************************************************
 */

#ifndef _MG32_APX_CCLx_INIT_H
/*!< _MG32_APX_CCLx_INIT_H */ 
#define _MG32_APX_CCLx_INIT_H

#include "MG32_APX_DRV.h"

// <<< Use Configuration Wizard in Context Menu >>>
//<e0> Configure CCL0 Module
    #define CONF_CCL0_MODE                            0
//  <h> CCL0 (input path)
//    <o0.0..3> CCL0 IN0 input Mux select. 
//          <0x0=> Disable : Mask input
//          <0x1=> IN01 : Feedback from CCLn_SEQ signal
//          <0x2=> IN02 : Link from CCLn_AO signal
//          <0x3=> IN03 : PB11
//          <0x4=> IN04 : PA8
//          <0x5=> IN05 : PB0
//          <0x6=> IN06 : PB8
//          <0x7=> IN07 : PE0
//          <0x8=> IN08 : CMP0_OUT
//          <0x9=> IN09 : URT0_TX
//          <0xA=> IN0A : SPI0_MOSI (output)
//          <0xB=> IN0B : TM36_OC00
//          <0xC=> IN0C : TM26_OC00
//          <0xD=> IN0D : SDT_I0
//          <0xE=> IN0E : OBM_P0
      #define CONF_APX_CCL01_CCL0_MUX0                0x00000000
//    <o0.4..7> CCL0 IN1 input Mux select. 
//          <0x0=> Disable : Mask input
//          <0x1=> IN01 : Feedback from CCLn_SEQ signal
//          <0x2=> IN02 : Link from CCLn_AO signal
//          <0x3=> IN03 : PB3
//          <0x4=> IN04 : PA9
//          <0x5=> IN05 : PB1
//          <0x6=> IN06 : PB9
//          <0x7=> IN07 : PE1
//          <0x8=> IN08 : CMP1_OUT
//          <0x9=> IN09 : URT1_TX
//          <0xA=> IN0A : SPI0_MISO (output)
//          <0xB=> IN0B : TM36_OC10
//          <0xC=> IN0C : TM26_OC10
//          <0xD=> IN0D : SDT_I1
//          <0xE=> IN0E : OBM_I0
      #define CONF_APX_CCL01_CCL0_MUX1                0x00000000
//    <o0.8..11> CCL0 IN2 input Mux select. 
//          <0x0=> Disable : Mask input
//          <0x1=> IN01 : feedback from ccln_seq signal
//          <0x2=> IN02 : link from ccln_ao signal
//          <0x3=> IN03 : PC1
//          <0x4=> IN04 : PA10
//          <0x5=> IN05 : PB2
//          <0x6=> IN06 : PB10
//          <0x7=> IN07 : PE2
//          <0x8=> IN08 : ADC0_OUT
//          <0x9=> IN09 : URT4_TX
//          <0xa=> IN0A : SPI0_CLK
//          <0xb=> IN0B : TM36_OC2
//          <0xc=> IN0C : TM20_OC00
//          <0xd=> IN0D : SDT_P0
//          <0xe=> IN0E : OBM_I1
      #define CONF_APX_CCL01_CCL0_MUX2                0x00000000
//  </h>   
//  <h> CCL0 (CCL0 truth table configuration)

//    <o0.16..23> 1. CCL0 truth table output value <0-0xFF>
      #define CONF_APX_CCL00_CCL0_TRUTH               0x00000000

//    <o0.4..5> 2. CCL0 filter select. 
//          <0=> Disable 
//          <1=> SYNC : Synchronizer enable 
//          <2=> FILTER : Filter enable 
      #define CONF_APX_CCL00_CCL0_FTSEL               0x00000000

//    <o0.6..7> 3. CCL0 edge detector mode select 
//          <0=> Disable 
//          <0x1=> Rising 
//          <0x2=> Falling 
//          <0x3=> Dual-edge
      #define CONF_APX_CCL00_CCL0_EDSEL               0x00000000

//    <o0.8..10> 4. CCL0 sequential logic mode select 
//          <0=> Disable 
//          <0x1=> DFF : D flip flop 
//          <0x2=> JK : JK flip flop 
//          <0x3=> DLH : D latch 
//          <0x4=> RS : RS latch
      #define CONF_APX_CCL00_CCL0_SQSEL               0x00000000

//    <o0.24..25> 5. CCL0 sequential logic input CCL_S0 select 
//          <0=> 0 
//          <1=> 1 
//          <2=> CCL_S1 (apply for CCL1 active)
      #define CONF_APX_CCL00_CCL0_SQIN                0x00000000

//    <o0.11> 6. CCL0 output inverse enable bit <0=> Disable <1=> Enable
      #define CONF_APX_CCL00_CCL0_INV                 0x00000000

//  </h>

//  <o0.12..13> CCL0 internal clock input divider 
//          <0x0=> DIV1 : divided by 1 
//          <0x1=> DIV2 : divided by 2 
//          <0x2=> DIV4 : divided by 4 
//          <0x3=> DIV8 : divided by 8
      #define CONF_APX_CCL00_CCL0_DIV                 0x00000000

//  <h> APX_CCL0 interrupt enable 
//    <q0.16> CCL-0 output low-to-high detect interrupt enable. (CCL0_IE)
      #define CONF_INT_CC0_IE                         0x00000000
//  </h>
//</e>
//<e0> Configure CCL1 Module
    #define CONF_CCL1_MODE                            0
//  <h> CCL1 (input path)
//    <o0.0..3> CCL1  IN0 input Mux select. 
//          <0x0=> Disable : Mask input
//          <0x1=> IN01 : Feedback from CCLn_SEQ signal
//          <0x2=> IN02 : Link from CCLn_AO signal
//          <0x3=> IN03 : PB11
//          <0x4=> IN04 : PA8
//          <0x5=> IN05 : PB0
//          <0x6=> IN06 : PB8
//          <0x7=> IN07 : PE0
//          <0x8=> IN08 : CMP0_OUT
//          <0x9=> IN09 : URT0_TX
//          <0xA=> IN0A : SPI0_MOSI (output)
//          <0xB=> IN0B : TM36_OC00
//          <0xC=> IN0C : TM26_OC00
//          <0xD=> IN0D : SDT_I0
//          <0xE=> IN0E : OBM_P0
      #define CONF_APX_CCL11_CCL1_MUX0                0x00000000
//    <o0.4..7> CCL1  IN1 input Mux select. 
//          <0x0=> Disable : Mask input
//          <0x1=> IN01 : Feedback from CCLn_SEQ signal
//          <0x2=> IN02 : Link from CCLn_AO signal
//          <0x3=> IN03 : PB3
//          <0x4=> IN04 : PA9
//          <0x5=> IN05 : PB1
//          <0x6=> IN06 : PB9
//          <0x7=> IN07 : PE1
//          <0x8=> IN08 : CMP1_OUT
//          <0x9=> IN09 : URT1_TX
//          <0xA=> IN0A : SPI0_MISO (output)
//          <0xB=> IN0B : TM36_OC10
//          <0xC=> IN0C : TM26_OC10
//          <0xD=> IN0D : SDT_I1
//          <0xE=> IN0E : OBM_I0
      #define CONF_APX_CCL11_CCL1_MUX1                0x00000000
//    <o0.8..11> CCL1  IN2 input Mux select. 
//          <0x0=> Disable : Mask input
//          <0x1=> IN01 : feedback from ccln_seq signal
//          <0x2=> IN02 : link from ccln_ao signal
//          <0x3=> IN03 : PC1
//          <0x4=> IN04 : PA10
//          <0x5=> IN05 : PB2
//          <0x6=> IN06 : PB10
//          <0x7=> IN07 : PE2
//          <0x8=> IN08 : ADC0_OUT
//          <0x9=> IN09 : URT4_TX
//          <0xa=> IN0A : SPI0_CLK
//          <0xb=> IN0B : TM36_OC2
//          <0xc=> IN0C : TM20_OC00
//          <0xd=> IN0D : SDT_P0
//          <0xe=> IN0E : OBM_I1
      #define CONF_APX_CCL11_CCL1_MUX2                0x00000000
//  </h>   
//  <h> CCL1 (CCL1 truth table configuration)

//    <o0.16..23> 1. CCL1 truth table output value <0-0xFF>
      #define CONF_APX_CCL10_CCL1_TRUTH               0x00000000

//    <o0.4..5> 2. CCL1  filter select. 
//          <0=> Disable 
//          <1=> SYNC : Synchronizer enable 
//          <2=> FILTER : Filter enable 
      #define CONF_APX_CCL10_CCL1_FTSEL               0x00000000

//    <o0.6..7> 3. CCL1  edge detector mode select 
//          <0=> Disable 
//          <0x1=> Rising 
//          <0x2=> Falling 
//          <0x3=> Dual-edge
      #define CONF_APX_CCL10_CCL1_EDSEL               0x00000000

//    <o0.8..10> 4. CCL1  sequential logic mode select 
//          <0=> Disable 
//          <0x1=> DFF : D flip flop 
//          <0x2=> JK : JK flip flop 
//          <0x3=> DLH : D latch 
//          <0x4=> RS : RS latch
      #define CONF_APX_CCL10_CCL1_SQSEL               0x00000000

//    <o0.24..25> 5. CCL1  sequential logic input CCL_S0 select 
//          <0=> 0 
//          <1=> 1 
      #define CONF_APX_CCL10_CCL1_SQIN                0x00000000

//    <o0.11> 6. CCL1  output inverse enable bit <0=> Disable <1=> Enable
      #define CONF_APX_CCL10_CCL1_INV                 0x00000000

//  </h>

//  <o0.12..13> CCL1  internal clock input divider 
//          <0x0=> DIV1 : divided by 1 
//          <0x1=> DIV2 : divided by 2 
//          <0x2=> DIV4 : divided by 4 
//          <0x3=> DIV8 : divided by 8
      #define CONF_APX_CCL10_CCL1_DIV                 0x00000000

//  <h> APX_CCL1 interrupt enable 
//    <q0.17> CCL-1 output low-to-high detect interrupt enable. (CCL1_IE)
      #define CONF_INT_CC1_IE                         0x00000000
//  </h>

//</e>
// <<< end of Configuration section >>>

// --------------------------------------------------------------------
// APX CCL0 Module
// --------------------------------------------------------------------

// ----------------------------------------------
#define CONF_APX_CCL00  CONF_APX_CCL00_CCL0_TRUTH   |\
                        CONF_APX_CCL00_CCL0_FTSEL   |\
                        CONF_APX_CCL00_CCL0_EDSEL   |\
                        CONF_APX_CCL00_CCL0_SQSEL   |\
                        CONF_APX_CCL00_CCL0_SQIN    |\
                        CONF_APX_CCL00_CCL0_INV     |\
                        CONF_APX_CCL00_CCL0_DIV     |\
                        APX_CCL00_CCL0_TEN_enable_w

#define CONF_APX_CCL01  CONF_APX_CCL01_CCL0_MUX0    |\
                        CONF_APX_CCL01_CCL0_MUX1    |\
                        CONF_APX_CCL01_CCL0_MUX2
                        
                        
#if CONF_INT_CC0_IE != 0
    #define CONF_CCL0_INT   (CONF_INT_CC0_IE | APX_INT_IEA_enable_w)
#else
    #define CONF_CCL0_INT   (CONF_INT_CC0_IE | APX_INT_IEA_enable_w)
#endif
// --------------------------------------------------------------------
// APX CCL1 Module
// --------------------------------------------------------------------

// ----------------------------------------------
#define CONF_APX_CCL10  CONF_APX_CCL10_CCL1_TRUTH   |\
                        CONF_APX_CCL10_CCL1_FTSEL   |\
                        CONF_APX_CCL10_CCL1_EDSEL   |\
                        CONF_APX_CCL10_CCL1_SQSEL   |\
                        CONF_APX_CCL10_CCL1_SQIN    |\
                        CONF_APX_CCL10_CCL1_INV     |\
                        CONF_APX_CCL10_CCL1_DIV     |\
                        APX_CCL10_CCL1_TEN_enable_w

#define CONF_APX_CCL11  CONF_APX_CCL11_CCL1_MUX0    |\
                        CONF_APX_CCL11_CCL1_MUX1    |\
                        CONF_APX_CCL11_CCL1_MUX2
                        
                        
#if CONF_INT_CC1_IE != 0
    #define CONF_CCL1_INT   (CONF_INT_CC1_IE | APX_INT_IEA_enable_w)
#else
    #define CONF_CCL1_INT   (CONF_INT_CC1_IE | APX_INT_IEA_enable_w)
#endif
    
    
/**
 * @name  Function announce
 *      
 */
///@{ 
void APX_CCL_Init(void);

///@}
#endif  // _MG32_APX_CCL0_INIT_H

