/**
 ******************************************************************************
 *
 * @file        MG32_DAC_Init.H
 *
 * @brief       This file is to configure DAC baudrate setting.
 *              Device : MG32F02D032
 * @par         Project
 *              MG32 
 * @version     V1.03
 * @date        2026/04/16
 * @author      MG32CoGen
 * @copyright   Copyright (c) 2022 MegaWin Technology Co., Ltd.
 *              All rights reserved.
 *
 ******************************************************************************
 * @par     Disclaimer 
 *    The Demo software is provided "AS IS"  without any warranty, either 
 *    expressed or implied, including, but not limited to, the implied warranties 
 *    of merchantability and fitness for a particular purpose.  The author will 
 *    not be liable for any special, incidental, consequential or indirect 
 *    damages due to loss of data or any other reason. 
 *    These statements agree with the world wide and local dictated laws about 
 *    authorship and violence against these laws. 
 *******************************************************************************
 *******************************************************************************
 */

#ifndef _MG32_DAC_INIT_H
 
#define _MG32_DAC_INIT_H

#include "MG32_DAC_DRV.h"
#if defined(IRQHandler_Middleware_Level_)       
    #include "MG32_DAC_MID.h"
#endif

// <<< Use Configuration Wizard in Context Menu >>>

//<e0.0> Module - Mode Active
    #define CONF_DAC_MODE                                   0x00000000
//  <e.0> DAC_P0 Config
    #define CONF_DAC_CR0_EN                                 0x00000000
//      <i> MG32F02D032 builds in one DAC module which embeds one 12-bit current mode DAC (digital-to-analog converter).
//      <i> The digital-to-analog conversion can be performed and start trigger by data register written, events (external pin input or internal events).
//      <i> The DAC can output a full-scale voltage from 0.2 volt to VDD-0.2 volt under the conversion rate up to 1MHz when DAC output buffer is on.
//      <q0.1> DAC output buffer enable 
        #define CONF_DAC_CR0_BUF0_EN                        0x00000000
//      <h> DAC start trigger control 
//          <o0.8..10> Trigger source <0=> WDAT : DAC_DAT0 register written
//                                    <1=> PIN : DAC_TRG external trigger pin 
//                                    <3=> TM00 : TM00_TRGO
//                                    <4=> TM01 : TM01_TRGO 
//                                    <6=> ITR6 : APB_ITR6
//                                    <7=> ITR7 : APB_ITR7
//              <i> DAC start trigger control source select.
        #define CONF_DAC_CR0_START0_SEL                     0x00000000
//          <o0.12..13> start trigger selection
//                                    <0=> Disable    
//                                    <1=> Rising edge
//                                    <2=> Falling edge
//                                    <3=> Dual-edge  
//              <i> DAC-0 start trigger selection. When selects Disable, the edge trigger detection is disabled and no start trigger signal output. 
//              <i> When DAC_START0_SEL = WDAT (DAC_DAT0 register written), this register is no effect.
        #define CONF_DAC_CR0_TRG0_SEL                       0x00000000
//      </h>
//      <o0.0..15> Output code (ratio:x/4096) <0-4095>
//      <i> DAC: Voltage output / input range 0~4095 (for 12-bit mode)  
        #define CONF_DAC_DAT0                               0x00000000
//  </e>
//  <e.0> DAC_P1 Config
    #define CONF_DAC_CR1_EN                                 0x00000000
//      <i> MG32F02D032 builds in one DAC module which embeds one 12-bit current mode DAC (digital-to-analog converter).
//      <i> The digital-to-analog conversion can be performed and start trigger by data register written, events (external pin input or internal events).
//      <i> The DAC can output a full-scale voltage from 0.2 volt to VDD-0.2 volt under the conversion rate up to 1MHz when DAC output buffer is on.
//      <q0.1> DAC output buffer enable 
        #define CONF_DAC_CR1_BUF1_EN                        0x00000000
//      <h> DAC start trigger control 
//          <o0.8..10> Trigger source <0=> WDAT : DAC_DAT0 register written
//                                    <1=> PIN : DAC_TRG external trigger pin 
//                                    <3=> TM00 : TM00_TRGO
//                                    <4=> TM01 : TM01_TRGO 
//                                    <6=> ITR6 : APB_ITR6
//                                    <7=> ITR7 : APB_ITR7
//              <i> DAC start trigger control source select.
        #define CONF_DAC_CR1_START1_SEL                     0x00000000
//          <o0.12..13> start trigger selection
//                                    <0=> Disable    
//                                    <1=> Rising edge
//                                    <2=> Falling edge
//                                    <3=> Dual-edge  
//              <i> DAC-0 start trigger selection. When selects Disable, the edge trigger detection is disabled and no start trigger signal output. 
//              <i> When DAC_START0_SEL = WDAT (DAC_DAT0 register written), this register is no effect.
        #define CONF_DAC_CR1_TRG1_SEL                       0x00000000
//      </h>
//      <o0.0..15> Output code (ratio:x/4096) <0-4095>
//      <i> DAC: Voltage output / input range 0~4095 (for 12-bit mode)  
        #define CONF_DAC_DAT1                               0x00000000
//  </e>
//</e>

//<e0.0> DAC interrupt all enable (DAC_IEA)
        #define CONF_DAC_INT_IEA                            0x00000000
//    <q0.1> DAC-0 ready to update new data to data register interrupt (RDY0_IE)
        #define CONF_DAC_INT_RDY0_IE                        0x00000000
//    <q0.7> DAC-0 conversion underrun event interrupt (UDR0_IE)
        #define CONF_DAC_INT_UDR0_IE          	            0x00000000
//    <q0.9> DAC-1 ready to update new data to data register interrupt (RDY1_IE)
        #define CONF_DAC_INT_RDY1_IE                        0x00000000
//    <q0.15> DAC-1 conversion underrun event interrupt (UDR1_IE)
        #define CONF_DAC_INT_UDR1_IE          	            0x00000000
//</e>
// <<< end of Configuration section >>>

    // ----------------------------------------------
    // Combined with DAC_INT register bit function
    #define CONF_DAC_INT    (CONF_DAC_INT_IEA       |\
                             CONF_DAC_INT_RDY0_IE   |\
                             CONF_DAC_INT_UDR0_IE   |\
                             CONF_DAC_INT_RDY1_IE   |\
                             CONF_DAC_INT_UDR1_IE   )
                             
    // ----------------------------------------------
    // Combined with DAC_CR0 register bit function
    #define CONF_DAC_CR0    (CONF_DAC_CR0_BUF0_EN   |\
                             CONF_DAC_CR0_START0_SEL|\
                             CONF_DAC_CR0_TRG0_SEL  |\
                             CONF_DAC_CR0_EN        )
                                                  
    // ----------------------------------------------
    // Combined with DAC_CR1 register bit function
    #define CONF_DAC_CR1    (CONF_DAC_CR1_BUF1_EN   |\
                             CONF_DAC_CR1_START1_SEL|\
                             CONF_DAC_CR1_TRG1_SEL  |\
                             CONF_DAC_CR1_EN        )

    
    // ------------------------------------------------------------------------
    // Assemble mADC structure within Middleware level
    // ------------------------------------------------------------------------

    // ------------------------------------------------------------------------
    // DAC Trigger Converion Source Select
    #define mDAC_TriggerConverionSrc_Select         CONF_DAC_CR0_START0_SEL

    // ------------------------------------------------------------------------
    // DAC Trigger Converion Edge Select
    #define mDAC_TriggerConverionEdge_Select        CONF_DAC_CR0_TRG0_SEL

    // ------------------------------------------------------------------------
    // DAC Interrupt Mode Select
    #define DAC_InterruptMode_Select                (CONF_DAC_INT_RDY0_IE   |\
                                                     CONF_DAC_INT_UDR0_IE   |\
                                                     CONF_DAC_INT_RDY1_IE   |\
                                                     CONF_DAC_INT_UDR1_IE   )



/**
 * @name  Function announce
 *      
 */
///@{ 
void DAC_Init(void);

///@}
#endif  // _MG32_DAC_INIT_H

