/**
 ******************************************************************************
 *
 * @file        MG32_APB_OBM_Init.h
 *
 * @brief       This file is to configure APB OBM0/1 setting.
 *              Device : MG32F02U128
 * @par         Project
 *              MG32 
 * @version     V1.01
 * @date        2026/01/27
 * @author      MG32CoGen: 2.0.0.32 , 2026/2/9 上午 10:17 
 * @copyright   Copyright (c) 2022 MegaWin Technology Co., Ltd.
 *              All rights reserved.
 *
 ******************************************************************************
 * @par     Disclaimer 
 *    The Demo software is provided "AS IS"  without any warranty, either 
 *    expressed or implied, including, but not limited to, the implied warranties 
 *    of merchantability and fitness for a particular purpose.  The author will 
 *    not be liable for any special, incidental, consequential or indirect 
 *    damages due to loss of data or any other reason. 
 *    These statements agree with the world wide and local dictated laws about 
 *    authorship and violence against these laws. 
 *******************************************************************************
 *******************************************************************************
 */

#ifndef _MG32_APB_OBM_INIT_H
/*!< _MG32_APB_OBM_INIT_H */ 
#define _MG32_APB_OBM_INIT_H

#include "MG32_APB_DRV.h"

// <<< Use Configuration Wizard in Context Menu >>>
//<e0> Configure OBM0 Module
    #define CONF_OBM0_MODE                            0
//  <h> OBM0 break signal source channel-0.
//      <o0.16..19> OBM0 break signal source channel-0 select.
//                  <0=> BKS0 Logic 1 <1=> BKS0 INT PA <2=> BKS0 INT PC <3=> BKS0 ADC0 OUT
//                  <4=> BKS0 TM00 TRGO <5=> BKS0 TM10 TRGO <6=> BKS0 TM20 TRGO <7=> BKS0 CCL P0
//                  <8=> BKS0 TM20 OC00 <9=> BKS0 TM36 OC2 <10=> BKS0 CMP0 OUT <12=> BKS0 URT0 TX
//                  <13=> BKS0 URT2 TX <14=> BKS0 URT0 RX <15=> BKS0 URT2 RX
        #define CONF_OBM00_BKS0_SEL                   0x00000000
//      <q0.8> OBM0 break source-0 signal inverse enable bit <0=> Disable <1=> Enable
        #define CONF_OBM00_BKN0_EN                    0x00000000
//  </h>
//  <h> OBM0 break signal source channel-1.
//      <o0.20..23> OBM0 break signal source channel-1 select.
//                  <0=> BKS1 Logic 1 <1=> BKS1 INT PB <2=> BKS1 INT PD <3=> BKS1 INT BOD1
//                  <4=> BKS1 TM01 TRGO <5=> BKS1 TM16 TRGO <6=> BKS1 TM26 TRGO <7=>BKS1 CCL P1
//                  <8=> BKS1 TM20 OC10 <9=> BKS1 TM36 OC3 <10=> BKS1 CMP1 OUT
//                  <12=> BKS1 URT1 TX <14=> BKS1 URT1 RX
        #define CONF_OBM00_BKS1_SEL                   0x00000000
//      <q0.9> OBM0 break source-1 signal inverse enable bit <0=> Disable <1=> Enable
        #define CONF_OBM00_BKN1_EN                    0x00000000
//  </h>
//  <h> OBM0 break signal source channel-2.
//      <o0.24..27> OBM0 break signal source channel-2 select.
//                  <0=> BKS1 Logic 1 <1=> BKS2 INT PE <3=> BKS2 SPI0 MOSI
//                  <6=> BKS2 TM36 TRGO <12=> BKS2 URT2 BRO <13=> BKS2 URT2 TMO
        #define CONF_OBM00_BKS2_SEL                   0x00000000
//      <q0.10> OBM0 break source-2 signal inverse enable bit <0=> Disable <1=> Enable
        #define CONF_OBM00_BKN2_EN                    0x00000000
//  </h>
//  <h> OBM0 output source channel-0 signal
//      <o0.16..19> OBM0 output source channel-0 signal select.
//                  <0=> OBM0CH0 Logic 0 <1=> OBM0CH0 INT PA <2=> OBM0CH0 INT PC <3=> OBM0CH0 INT PE
//                  <4=> OBM0CH0 TM00 CKO <5=> OBM0CH0 TM10 CKO <6=> OBM0CH0 TM20 CKO 
//                  <7=> OBM0CH0 TM36 CKO <8=> OBM0CH0 TM20 OC00 <9=> OBM0CH0 TM36 OC00
//                  <10=> OBM0CH0 TM36 OC2 <12=> OBM0CH0 OBM I0 <13=> OBM0CH0 ITR6
        #define CONF_OBM01_MUX0_SEL                   0x00000000
//      <q0.0> OBM0 source channel-0 signal inverse. <0=> Disable <1=> Enable
        #define CONF_OBM01_INV0_EN                    0x00000000
//  </h>
//  <h> OBM0 output source channel-1 signal
//      <o0.20..23> OBM0 output source channel-1 signal select.
//                  <0=> OBM0CH1 Logic 0 <1=> OBM0CH1 INT PB <2=> OBM0CH1 INT PD
//                  <4=> OBM0CH1 TM01 CKO <5=> OBM0CH1 TM16 CKO <6=> OBM0CH1 TM26 CKO
//                  <8=> OBM0CH1 TM20 OC01 <9=> OBM0CH1 TM36 OC01 <10=> OBM0CH1 TM36 OC3
//                  <12=> OBM0CH1 OBM I1 <13=> OBM0CH1 ITR7 <14=> OBM0CH1 ICKO INT
        #define CONF_OBM01_MUX1_SEL                   0x00000000
//      <q0.1> OBM0 source channel-0 signal inverse. <0=> Disable <1=> Enable
        #define CONF_OBM01_INV1_EN                    0x00000000
//  </h>
//  <h> OBM0 Output control and operation mode
//      <o0.4..5> OBM0 output deglitch filter clock source select.
//                <0=> Disable <1=> APB : CLK_APB <2=> APB_DIV8 : CLK_APB divide by 8 <3=> TM00_TRGO
        #define CONF_OBM01_FCKS_SEL                   0x00000000
//      <o0.2> OBM0 output signal inverse enable bit. <0=> Disable <1=> Enable
        #define CONF_OBM01_POL_EN                     0x00000000
//      <o0.0..1> OBM0 break operation mode select.
//                <0=> AND <1=> CLR <2=> SET <3=> TOGGLE
        #define CONF_OBM00_MDS_SEL                    0x00000000
//      <o0.4..5> OBM0 break switching signal initial state. <2=> 0 (Output 0) <3=> 1 (Output 1)
        #define CONF_OBM00_STA_SET                    0x00000020
//  </h>
//  <h> APB_OBM0 interrupt enable 
//      <q0.8> OBM0 break trigger event detect interrupt enable. <0=> Disable <1=> Enable
        #define CONF_OBM0_INT_IE                      0x00000000
//  </h>
//</e>
//<e0> Configure OBM1 Module
    #define CONF_OBM1_MODE                            0
//  <h> OBM1 break signal source channel-0.
//      <o0.16..19> OBM1 break signal source channel-0 select.
//                  <0=> BKS0 Logic 1 <1=> BKS0 INT PA <2=> BKS0 INT PC <3=> BKS0 ADC0 OUT
//                  <4=> BKS0 TM00 TRGO <5=> BKS0 TM10 TRGO <6=> BKS0 TM20 TRGO <7=> BKS0 CCL P0
//                  <8=> BKS0 TM20 OC00 <9=> BKS0 TM36 OC2 <10=> BKS0 CMP0 OUT <12=> BKS0 URT0 TX
//                  <13=> BKS0 URT2 TX <14=> BKS0 URT0 RX <15=> BKS0 URT2 RX
        #define CONF_OBM10_BKS0_SEL                   0x00000000
//      <q0.8> OBM1 break source-0 signal inverse enable bit <0=> Disable <1=> Enable
        #define CONF_OBM10_BKN0_EN                    0x00000000
//  </h>
//  <h> OBM1 break signal source channel-1.
//      <o0.20..23> OBM1 break signal source channel-1 select.
//                  <0=> BKS1 Logic 1 <1=> BKS1 INT PB <2=> BKS1 INT PD <3=> BKS1 INT BOD1
//                  <4=> BKS1 TM01 TRGO <5=> BKS1 TM16 TRGO <6=> BKS1 TM26 TRGO <7=>BKS1 CCL P1
//                  <8=> BKS1 TM20 OC10 <9=> BKS1 TM36 OC3 <10=> BKS1 CMP1 OUT
//                  <12=> BKS1 URT1 TX <14=> BKS1 URT1 RX
        #define CONF_OBM10_BKS1_SEL                   0x00000000
//      <q0.9> OBM1 break source-1 signal inverse enable bit <0=> Disable <1=> Enable
        #define CONF_OBM10_BKN1_EN                    0x00000000
//  </h>
//  <h> OBM1 break signal source channel-2.
//      <o0.24..27> OBM1 break signal source channel-2 select.
//                  <0=> BKS1 Logic 1 <1=> BKS2 INT PE <3=> BKS2 SPI0 MOSI
//                  <6=> BKS2 TM36 TRGO <12=> BKS2 URT2 BRO <13=> BKS2 URT2 TMO
        #define CONF_OBM10_BKS2_SEL                   0x00000000
//      <q0.10> OBM1 break source-2 signal inverse enable bit <0=> Disable <1=> Enable
        #define CONF_OBM10_BKN2_EN                    0x00000000
//  </h>
//  <h> OBM1 output source channel-0 signal
//      <o0.16..19> OBM1 output source channel-0 signal select.
//                  <0=> OBM0CH0 Logic 0 <1=> OBM0CH0 INT PA <2=> OBM0CH0 INT PC <3=> OBM0CH0 INT PE
//                  <4=> OBM0CH0 TM00 CKO <5=> OBM0CH0 TM10 CKO <6=> OBM0CH0 TM20 CKO 
//                  <7=> OBM0CH0 TM36 CKO <8=> OBM0CH0 TM20 OC00 <9=> OBM0CH0 TM36 OC00
//                  <10=> OBM0CH0 TM36 OC2 <12=> OBM0CH0 OBM I0 <13=> OBM0CH0 ITR6
        #define CONF_OBM11_MUX0_SEL                   0x00000000
//      <q0.0> OBM1 source channel-0 signal inverse. <0=> Disable <1=> Enable
        #define CONF_OBM11_INV0_EN                    0x00000000
//  </h>
//  <h> OBM1 output source channel-1 signal
//      <o0.20..23> OBM1 output source channel-1 signal select.
//                  <0=> OBM0CH1 Logic 0 <1=> OBM0CH1 INT PB <2=> OBM0CH1 INT PD
//                  <4=> OBM0CH1 TM01 CKO <5=> OBM0CH1 TM16 CKO <6=> OBM0CH1 TM26 CKO
//                  <8=> OBM0CH1 TM20 OC01 <9=> OBM0CH1 TM36 OC01 <10=> OBM0CH1 TM36 OC3
//                  <12=> OBM0CH1 OBM I1 <13=> OBM0CH1 ITR7 <14=> OBM0CH1 ICKO INT
        #define CONF_OBM11_MUX1_SEL                   0x00000000
//      <q0.1> OBM1 source channel-0 signal inverse. <0=> Disable <1=> Enable
        #define CONF_OBM11_INV1_EN                    0x00000000
//  </h>
//  <h> OBM1 Output control and operation mode
//      <o0.4..5> OBM1 output deglitch filter clock source select.
//                <0=> Disable <1=> APB : CLK_APB <2=> APB_DIV8 : CLK_APB divide by 8 <3=> TM00_TRGO
        #define CONF_OBM11_FCKS_SEL                   0x00000000
//      <o0.2> OBM1 output signal inverse enable bit. <0=> Disable <1=> Enable
        #define CONF_OBM11_POL_EN                     0x00000000
//      <o0.0..1> OBM1 break operation mode select.
//                <0=> AND <1=> CLR <2=> SET <3=> TOGGLE
        #define CONF_OBM10_MDS_SEL                    0x00000000
//      <o0.4..5> OBM1 break switching signal initial state. <2=> 0 (Output 0) <3=> 1 (Output 1)
        #define CONF_OBM10_STA_SET                    0x00000020
//  </h>
//  <h> APB_OBM1 interrupt enable 
//      <q0.9> OBM1 break trigger event detect interrupt enable. <0=> Disable <1=> Enable
        #define CONF_OBM1_INT_IE                      0x00000000
//  </h>
//</e>
// <<< end of Configuration section >>>

// Combined with APB_OBMx register bit function
// --------------------------------------------------------------------
// APB OBM0 Module
// --------------------------------------------------------------------

// ----------------------------------------------
#define CONF_OBM00_REG  CONF_OBM00_BKS0_SEL     |\
                        CONF_OBM00_BKN0_EN      |\
                        CONF_OBM00_BKS1_SEL     |\
                        CONF_OBM00_BKN1_EN      |\
                        CONF_OBM00_BKS2_SEL     |\
                        CONF_OBM00_BKN2_EN      |\
                        CONF_OBM00_MDS_SEL      |\
                        CONF_OBM00_STA_SET
                        
#define CONF_OBM01_REG  CONF_OBM01_MUX0_SEL     |\
                        CONF_OBM01_INV0_EN      |\
                        CONF_OBM01_MUX1_SEL     |\
                        CONF_OBM01_INV1_EN      |\
                        CONF_OBM01_FCKS_SEL     |\
                        CONF_OBM01_POL_EN

#if CONF_OBM0_INT_IE != 0
    #define CONF_OBM0_INT   (CONF_OBM0_INT_IE | APB_INT_IEA_enable_w)
#else
    #define CONF_OBM0_INT   (0)
#endif
    

// --------------------------------------------------------------------
// APB OBM1 Module
// --------------------------------------------------------------------

// ----------------------------------------------
#define CONF_OBM10_REG  CONF_OBM10_BKS0_SEL     |\
                        CONF_OBM10_BKN0_EN      |\
                        CONF_OBM10_BKS1_SEL     |\
                        CONF_OBM10_BKN1_EN      |\
                        CONF_OBM10_BKS2_SEL     |\
                        CONF_OBM10_BKN2_EN      |\
                        CONF_OBM10_MDS_SEL      |\
                        CONF_OBM10_STA_SET
                        
#define CONF_OBM11_REG  CONF_OBM11_MUX0_SEL     |\
                        CONF_OBM11_INV0_EN      |\
                        CONF_OBM11_MUX1_SEL     |\
                        CONF_OBM11_INV1_EN      |\
                        CONF_OBM11_FCKS_SEL     |\
                        CONF_OBM11_POL_EN
                        
#if CONF_OBM1_INT_IE != 0
    #define CONF_OBM1_INT   (CONF_OBM1_INT_IE | APB_INT_IEA_enable_w)
#else
    #define CONF_OBM1_INT   (0)
#endif
    
    
#endif  // _MG32_APB_OBM_INIT_H

