/**
 ******************************************************************************
 *
 * @file        MG32_APX_ASB_Init.h
 *
 * @brief       This file is to configure ASB of APX.
 *              Device : MG32F02N128
 * @par         Project
 *              MG32 
 * @version     V1.00   
 * @date        2025/06/26
 * @author      MG32CoGen: 2.0.0.32 , 2026/2/9 上午 11:15 
 * @copyright   Copyright (c) 2022 MegaWin Technology Co., Ltd.
 *              All rights reserved.
 *
 ******************************************************************************
 * @par 		Disclaimer 
 *		The Demo software is provided "AS IS"  without any warranty, either 
 *		expressed or implied, including, but not limited to, the implied warranties 
 *		of merchantability and fitness for a particular purpose.  The author will 
 *		not be liable for any special, incidental, consequential or indirect 
 *		damages due to loss of data or any other reason. 
 *		These statements agree with the world wide and local dictated laws about 
 *		authorship and violence against these laws. 
 *******************************************************************************
 *******************************************************************************
 */

/* Includes ------------------------------------------------------------------*/
#include "MG32_APX.h"
#include "RTE_Components.h"
#if defined(IRQHandler_Middleware_Level_)
    #include "MG32_APX_MID.h"
#endif  


// <<< Use Configuration Wizard in Context Menu >>>
//<e0> ASB Configure
#define CONF_APX_ASB_INIT_EN             1
    //<h> Signal Control Related Configure
        //<o0> Idle State Level <0=> Low <1=> High
        #define CONF_ASB_IDLE            0
        //<o0> RESET Code level <0=> Low <1=> High
        #define CONF_ASB_RST             0
        //<o0> ASB_CKn Signal Inverse <0=> Disable <1=> Enable
        //<i> The signal is only for shift mode
        #define CONF_ASB_CINV            0
        //<e0> Enable RESET Code Synchronous Mode
        //<i> If enabling the function all channels that enable that automatically insert a RESET Code function will output RESET code at the same time.
        #define CONF_ASB_SYEN            0
            //<o0> SYNC Code <0=> Code0 <1=> Code1
            #define CONF_ASB_SYNC        0    
        //</e>
    //</h>
    //<h> Data Transfer Time Configure
        //<o0> Clock Source Prescaler (1~8) <1-8>
        #define CONF_ASB_PSC             1
        //<o0> Bit Time Counter (2~32)<2-32>
        //<i> Code 0 (T0H + T0L) and Code 1 (T1H + T1L) Counter.
        //<i> Bit Time = ( <Prescaler> * <Bit Time Counter>) / ASB clock source frequency.
        #define CONF_ASB_CNT             15    
        //<o0> Code 0 High Level Counter (1~32)<1-32>
        //<i> *. If Bit Time Counter less than or equal to Code 0 High Counter the Code0 bit is always high level.
        //<i> *. T0H Time = ( <Prescaler> * <Code 0 High Level Counter>) / ASB clock source frequency.
        #define CONF_ASB_T0H             5
        //<o0> Code 1 High Level Counter (1~32)<1-32> 
        //<i> *. If Bit Time Counter less than or equal to Code 1 High Counter the Code1 bit is always high level.
        //<i> *. T1H Time = ( <Prescaler> * <Code 1 High Level Counter> ) / ASB clock source frequency.
        #define CONF_ASB_T1H             10    
        //<o0> RESET Code Length (1~256) Bits<1-256>
        //<i> RESET Time = ( <RESET Code Length> * <Prescaler> * <Bit Time Counter>) / ASB clock source frequency.
        #define CONF_ASB_TRST            50
    //</h>
    //<e0> ASB Channel 0 Enable
    #define CONF_ASB0_EN                 0
        //<o0> Mode  <0=> ARGB mode <1=> Shift mode
        #define CONF_ASB0_MDS            0
        //<o0> Data Order <0=> LSB  <1=> MSB
        #define CONF_ASB0_MSB            1
        //<o0> Data Bit Inverse <0=> Disable <1=> Enable
        #define CONF_ASB0_DINV           0
        //<o0> Signal Inverse <0=> Disable <1=> Enable
        #define CONF_ASB0_INV            0
        //<o0> FIFO Low Threshold <0=> 0 Byte (Empty) <1=> 2 Bytes (Half)
        #define CONF_ASB0_TXTH           1
        //<e0> Enable Automatically Insert A RESET Code
        //<i> If enabling "RESET code synchronous" mode, all channels that enable the function will output RESET code at the same time.
        //<i> Within channel wait to output RESET code the channel will output SYNC Code.
        #define CONF_ASB0_PCNT_EN        0
            //<o0> How Many Pixels To Automatically Insert A RESET Code (1 ~ 255)<1-255>
            #define CONF_ASB0_PCNT       1
            //<o0> A Pixel Length <0=> 3 Bytes <1=> 4 Bytes
            #define CONF_ASB0_PLEN       0
        //</e>
    //</e>
    //<e0> ASB Channel 1 Enable
    #define CONF_ASB1_EN                 0
        //<o0> Mode  <0=> ARGB mode <1=> Shift mode
        #define CONF_ASB1_MDS            0
        //<o0> Data order <0=> LSB  <1=> MSB
        #define CONF_ASB1_MSB            1
        //<o0> Data bit inverse <0=> Disable <1=> Enable
        #define CONF_ASB1_DINV           0
        //<o0> Signal inverse <0=> Disable <1=> Enable
        #define CONF_ASB1_INV            0
        //<o0> FIFO low threshold <0=> 0 Byte (Empty) <1=> 2 Bytes (Half)
        #define CONF_ASB1_TXTH           1
        //<e0> Enable Automatically Insert a RESET Code
        //<i> If enabling "RESET code synchronous" mode, all channels that enable the function will output RESET code at the same time.
        //<i> Within channel wait to output RESET code the channel will output SYNC Code.
        #define CONF_ASB1_PCNT_EN        0
            //<o0> How Many Pixels To Automatically Insert a RESET Code (1 ~ 255)<1-255>
            #define CONF_ASB1_PCNT       1
            //<o0> A Pixel Length <0=> 3 Bytes <1=> 4 Bytes
            #define CONF_ASB1_PLEN       0            
        //</e>
    //</e>
    //<e0> ASB Channel 2 Enable
    //<i> The channel only has ARGB mode
    #define CONF_ASB2_EN                 0
        //<o0> Data order <0=> LSB  <1=> MSB
        #define CONF_ASB2_MSB            1
        //<o0> Data bit inverse <0=> Disable <1=> Enable
        #define CONF_ASB2_DINV           0
        //<o0> Signal inverse <0=> Disable <1=> Enable
        #define CONF_ASB2_INV            0
        //<o0> FIFO low threshold <0=> 0 Byte (Empty) <1=> 2 Bytes (Half)
        #define CONF_ASB2_TXTH           1
        //<e0> Enable Automatically Insert a RESET Code
        //<i> If enabling "RESET code synchronous" mode, all channels that enable the function will output RESET code at the same time.
        //<i> Within channel wait to output RESET code the channel will output SYNC Code.
        #define CONF_ASB2_PCNT_EN        0
            //<o0> How Many Pixels To Automatically Insert a RESET Code (1 ~ 255)<1-255>
            #define CONF_ASB2_PCNT       1
            //<o0> A Pixel Length <0=> 3 Bytes <1=> 4 Bytes
            #define CONF_ASB2_PLEN       0
        //</e>
    //</e>
    //<e0> ASB Channel 3 Enable
    //<i> The channel only has ARGB mode
    #define CONF_ASB3_EN                 0
        //<o0> Data order <0=> LSB  <1=> MSB
        #define CONF_ASB3_MSB            1
        //<o0> Data bit inverse <0=> Disable <1=> Enable
        #define CONF_ASB3_DINV           0
        //<o0> Signal inverse <0=> Disable <1=> Enable
        #define CONF_ASB3_INV            0
        //<o0> FIFO low threshold <0=> 0 Byte (Empty) <1=> 2 Bytes (Half)
        #define CONF_ASB3_TXTH           1
        //<e0> Enable Automatically Insert a RESET Code
        //<i> If enabling "RESET code synchronous" mode, all channels that enable the function will output RESET code at the same time.
        //<i> Within channel wait to output RESET code the channel will output SYNC Code.
        #define CONF_ASB3_PCNT_EN        0
            //<o0> How Many Pixels To Automatically Insert a RESET Code (1 ~ 255)<1-255>
            #define CONF_ASB3_PCNT       1
            //<o0> A Pixel Length <0=> 3 Bytes <1=> 4 Bytes
            #define CONF_ASB3_PLEN       0
        //</e>
    //</e>
    //<h> Interrupt Related Configure
        //<q0> ASB Channel 0 Transmission Data Threshold Low Interrupt (ASB0_TIE)
        #define CONF_ASB0_TIE            0
        //<q0> ASB Channel 0 Transmission Complete Interrupt (ASB0_TCIE)
        #define CONF_ASB0_TCIE           0
        //<q0> ASB Channel 1 Transmission Data Threshold Low Interrupt (ASB1_TIE)
        #define CONF_ASB1_TIE            0
        //<q0> ASB Channel 1 Transmission Complete Interrupt (ASB1_TCIE)
        #define CONF_ASB1_TCIE           0
        //<q0> ASB Channel 2 Transmission Data Threshold Low Interrupt (ASB2_TIE)
        #define CONF_ASB2_TIE            0
        //<q0> ASB Channel 2 Transmission Complete Interrupt (ASB2_TCIE)
        #define CONF_ASB2_TCIE           0
        //<q0> ASB Channel 3 Transmission Data Threshold Low Interrupt (ASB3_TIE)
        #define CONF_ASB3_TIE            0
        //<q0> ASB Channel 3 Transmission Complete Interrupt (ASB3_TCIE)
        #define CONF_ASB3_TCIE           0
    //</h>
//</e>
// <<< end of Configuration section >>>
    
/* Define ---------------------------------------------------------------------*/  

#define CONF_APX_ASB_STA_MASK  (( APX_STA_ASB0_TCF_mask_w | APX_STA_ASB0_TXF_mask_w) | \
                                ( APX_STA_ASB1_TCF_mask_w | APX_STA_ASB1_TXF_mask_w) | \
                                ( APX_STA_ASB2_TCF_mask_w | APX_STA_ASB2_TXF_mask_w) | \
                                ( APX_STA_ASB3_TCF_mask_w | APX_STA_ASB3_TXF_mask_w))


#define CONF_APX_ASB_INT_MASK  (( APX_INT_ASB0_TCIE_mask_w | APX_INT_ASB0_TIE_mask_w) | \
                                ( APX_INT_ASB1_TCIE_mask_w | APX_INT_ASB1_TIE_mask_w) | \
                                ( APX_INT_ASB2_TCIE_mask_w | APX_INT_ASB2_TIE_mask_w) | \
                                ( APX_INT_ASB3_TCIE_mask_w | APX_INT_ASB3_TIE_mask_w))


#define CONF_APX_ASB_INT       ((( APX_INT_ASB0_TCIE_mask_w * CONF_ASB0_TCIE) | (APX_INT_ASB0_TIE_mask_w * CONF_ASB0_TIE)) | \
                                (( APX_INT_ASB1_TCIE_mask_w * CONF_ASB1_TCIE) | (APX_INT_ASB1_TIE_mask_w * CONF_ASB1_TIE)) | \
                                (( APX_INT_ASB2_TCIE_mask_w * CONF_ASB2_TCIE) | (APX_INT_ASB2_TIE_mask_w * CONF_ASB2_TIE)) | \
                                (( APX_INT_ASB3_TCIE_mask_w * CONF_ASB3_TCIE) | (APX_INT_ASB3_TIE_mask_w * CONF_ASB3_TIE)))

#define CONF_APX_ASB_MASK      (APX_CR0_ASB_SYNC_mask_w | \
                                APX_CR0_ASB_IDLE_mask_w | \
                                APX_CR0_ASB_RST_mask_w  | \
                                APX_CR0_ASB_SYEN_mask_w | \
                                APX_CR0_ASB_CINV_mask_w)
                             
#define CONF_APX_ASB_CR0       ((APX_CR0_ASB_SYNC_mask_w * CONF_ASB_SYNC) | \
                                (APX_CR0_ASB_IDLE_mask_w * CONF_ASB_IDLE) | \
                                (APX_CR0_ASB_RST_mask_w  * CONF_ASB_RST ) | \
                                (APX_CR0_ASB_SYEN_mask_w * CONF_ASB_SYEN) | \
                                (APX_CR0_ASB_CINV_mask_w * CONF_ASB_CINV))


#define CONF_APX_ASB_CR1       ((((uint32_t)(CONF_ASB_CNT  - 1) << 27) & APX_CR1_ASB_CNT_mask_w ) | \
                                          (((CONF_ASB_PSC  - 1) << 24) & APX_CR1_ASB_PSC_mask_w ) | \
                                          (((CONF_ASB_TRST - 1) << 16) & APX_CR1_ASB_TRST_mask_w) | \
                                          (((CONF_ASB_T1H  - 1) << 8 ) & APX_CR1_ASB_T1H_mask_w ) | \
                                          (((CONF_ASB_T0H  - 1) << 0 ) & APX_CR1_ASB_T0H_mask_w ))                         

#define CONF_APX_ASB00         ((APX_ASB00_ASB0_TXTH_mask_w  * CONF_ASB0_TXTH) | \
                                (APX_ASB00_ASB0_PLEN_mask_w  * CONF_ASB0_PLEN) | \
                                (APX_ASB00_ASB0_INV_mask_w   * CONF_ASB0_INV)  | \
                                (APX_ASB00_ASB0_DINV_mask_w  * CONF_ASB0_DINV) | \
                                (APX_ASB00_ASB0_MSBEN_mask_w * CONF_ASB0_MSB)  | \
                                (APX_ASB00_ASB0_MDS_mask_w   * CONF_ASB0_MDS)  | \
                                (APX_ASB00_ASB0_EN_mask_w    * CONF_ASB0_EN))
                                
#define CONF_APX_ASB01         (((CONF_ASB0_PCNT * CONF_ASB0_PCNT_EN) << APX_ASB01_ASB0_PCNT_shift_w) & APX_ASB01_ASB0_PCNT_mask_w)
                               
#define CONF_APX_ASB10         ((APX_ASB10_ASB1_TXTH_mask_w  * CONF_ASB1_TXTH) | \
                                (APX_ASB10_ASB1_PLEN_mask_w  * CONF_ASB1_PLEN) | \
                                (APX_ASB10_ASB1_INV_mask_w   * CONF_ASB1_INV)  | \
                                (APX_ASB10_ASB1_DINV_mask_w  * CONF_ASB1_DINV) | \
                                (APX_ASB10_ASB1_MSBEN_mask_w * CONF_ASB1_MSB)  | \
                                (APX_ASB10_ASB1_MDS_mask_w   * CONF_ASB1_MDS)  | \
                                (APX_ASB10_ASB1_EN_mask_w    * CONF_ASB1_EN))
                                
#define CONF_APX_ASB11         (((CONF_ASB1_PCNT * CONF_ASB1_PCNT_EN) << APX_ASB11_ASB1_PCNT_shift_w) & APX_ASB11_ASB1_PCNT_mask_w)
                               
#define CONF_APX_ASB20         ((APX_ASB20_ASB2_TXTH_mask_w  * CONF_ASB2_TXTH) | \
                                (APX_ASB20_ASB2_PLEN_mask_w  * CONF_ASB2_PLEN) | \
                                (APX_ASB20_ASB2_INV_mask_w   * CONF_ASB2_INV)  | \
                                (APX_ASB20_ASB2_DINV_mask_w  * CONF_ASB2_DINV) | \
                                (APX_ASB20_ASB2_MSBEN_mask_w * CONF_ASB2_MSB)  | \
                                (APX_ASB20_ASB2_EN_mask_w    * CONF_ASB2_EN))
                               
#define CONF_APX_ASB21         (((CONF_ASB2_PCNT * CONF_ASB2_PCNT_EN) << APX_ASB21_ASB2_PCNT_shift_w) & APX_ASB21_ASB2_PCNT_mask_w)
                               
#define CONF_APX_ASB30         ((APX_ASB30_ASB3_TXTH_mask_w  * CONF_ASB3_TXTH) | \
                                (APX_ASB30_ASB3_PLEN_mask_w  * CONF_ASB3_PLEN) | \
                                (APX_ASB30_ASB3_INV_mask_w   * CONF_ASB3_INV)  | \
                                (APX_ASB30_ASB3_DINV_mask_w  * CONF_ASB3_DINV) | \
                                (APX_ASB30_ASB3_MSBEN_mask_w * CONF_ASB3_MSB)  | \
                                (APX_ASB30_ASB3_EN_mask_w    * CONF_ASB3_EN))
                                
#define CONF_APX_ASB31         (((CONF_ASB3_PCNT * CONF_ASB3_PCNT_EN) << APX_ASB31_ASB3_PCNT_shift_w) & APX_ASB31_ASB3_PCNT_mask_w)

#if defined(APX_ASB00_ASB0_EN_mask_w) || \
    defined(APX_ASB10_ASB1_EN_mask_w) || \
    defined(APX_ASB20_ASB2_EN_mask_w) || \
    defined(APX_ASB30_ASB3_EN_mask_w)
#define ModuleExist_ASB
#endif

/* Exported variables --------------------------------------------------------*/     
/* Exported functions --------------------------------------------------------*/ 
void APX_ASB_Init(void);
void APX_ASB_InitCallback(void);

