/**
 ******************************************************************************
 *
 * @file        MG32_APB_NCO_Init.h
 *
 * @brief       This file is to configure APB NCO output setting.
 *              Device : MG32F02U128
 * @par         Project
 *              MG32 
 * @version     V1.01
 * @date        2026/01/27
 * @author      MG32CoGen: 2.0.0.32 , 2026/2/9 上午 10:17 
 * @copyright   Copyright (c) 2022 MegaWin Technology Co., Ltd.
 *              All rights reserved.
 *
 ******************************************************************************
 * @par     Disclaimer 
 *    The Demo software is provided "AS IS"  without any warranty, either 
 *    expressed or implied, including, but not limited to, the implied warranties 
 *    of merchantability and fitness for a particular purpose.  The author will 
 *    not be liable for any special, incidental, consequential or indirect 
 *    damages due to loss of data or any other reason. 
 *    These statements agree with the world wide and local dictated laws about 
 *    authorship and violence against these laws. 
 *******************************************************************************
 *******************************************************************************
 */

#ifndef _MG32_APB_NCO_INIT_H
/*!< _MG32_APB_NCO_INIT_H */ 
#define _MG32_APB_NCO_INIT_H

#include "MG32_APB_DRV.h"

// <<< Use Configuration Wizard in Context Menu >>>
//<e0.0> Configure NCO Module
    #define CONF_NCO_MODE                      0x00000000
//  <h> NCO (NCO recipe)
//    <o0.26> INCO Output mode select 
//          <0=> FDC : fixed duty cycle mode
//          <1=> PFM : pulse frequency mode
      #define CONF_APB_NCO00_NCO0_MDS                 0x00000000
//    <o0.28..30> NCO input clock source select 
//          <0=> APB NCO IHRCO
//          <1=> APB NCO CK PLL
//          <2=> APB NCO APB
//          <3=> APB NCO CK LS
//          <4=> APB NCO TM00 TRGO
//          <5=> APB NCO CK0
      #define CONF_APB_NCO00_NCO0_CKS                 0x00000000
//    <q0.25> NCO output inverse enable. <0=> Disable <1=> Enable
      #define CONF_APB_NCO00_NCO0_MDS                 0x00000000
//    <o0.0..19> NCO adder increment value. <1-524287>
//      <i> (PFM) The NCO output frequency needs to be smaller than 1/4 APB clock frequency.
//      <i> (FDC) The NCO output frequency needs to be smaller than 1/2 APB clock frequency.
      #define CONF_APB_NCO00_NCO0_INC                 128
//  </h>
//  <h> NCO (NCO PFM mode Recipe)
//    <o0.24..26> NCO PFM mode output pulse width select.
//          <0=> CK1 : 1 CK_NCOn clock period
//          <1=> CK2 : 2 CK_NCOn clock period
//          <2=> CK4 : 4 CK_NCOn clock period
//          <3=> CK8 : 8 CK_NCOn clock period
//          <4=> CK16 : 16 CK_NCOn clock period
//          <5=> CK32 : 32 CK_NCOn clock period
//          <6=> CK64 : 64 CK_NCOn clock period
//          <7=> CK128 : 128 CK_NCOn clock period
//      <i> NCO PFM mode output pulse width must smaller than NCO cycle.
      #define CONF_APB_NCO01_NCO0_PWS                 0x00000000
//  </h>
//  <h> APB_NCO interrupt enable 
//      <q0.12> NCO-0 adder overflow event detect interrupt enable. <0=> Disable <1=> Enable
        #define CONF_NCO0_INT_IE                      0x00000000
//  </h>
//</e>
// <<< end of Configuration section >>>

// Combined with APB_CRO register bit function
// --------------------------------------------------------------------
// APB NCO Module
// --------------------------------------------------------------------

// ----------------------------------------------
#define CONF_APB_NCO00  CONF_APB_NCO00_NCO0_MDS |\
                        CONF_APB_NCO00_NCO0_CKS |\
                        CONF_APB_NCO00_NCO0_MDS |\
                        CONF_APB_NCO00_NCO0_INC

#define CONF_APB_NCO01  CONF_APB_NCO01_NCO0_PWS

#if CONF_NCO0_INT_IE != 0
    #define CONF_NCO_INT    (CONF_NCO0_INT_IE | APB_INT_IEA_enable_w)
#else
    #define CONF_NCO_INT    (0)
#endif

    
#endif  // _MG32_APB_NCO_INIT_H

