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MG32L003 Standard Peripherals Firmware Library
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Modules | |
| IWDG_IT | |
Macros | |
| #define | IWDG_UNLOCK_KEY ((uint32_t)0x55AA6699) |
| IWDG Key Register value. More... | |
| #define | IWDG_LOCK_KEY ((uint32_t)0x55AA6698) |
| #define | IWDG_START_ENABLE ((uint32_t)0x00000055) |
| #define | IWDG_RELOAD_REFRESH ((uint32_t)0x000000AA) |
| #define | IWDG_MODE_RESET ((uint32_t)0x00000000) |
| #define | IWDG_MODE_INT ((uint32_t)0x00000010) |
| #define | IWDG_MODE_MASK ((uint32_t)0x00000010) |
| #define | IWDG_IT_DISABLE ((uint32_t)0x00000000) |
| #define | IWDG_IT_ENABLE ((uint32_t)0x00000100) |
| #define | IWDG_IT_MASK ((uint32_t)0x00000100) |
| #define | IWDG_RLR_MAX IWDG_RLOAD_IWDGRLOAD |
| #define IWDG_IT_DISABLE ((uint32_t)0x00000000) |
IWDG interrupt disable
| #define IWDG_IT_ENABLE ((uint32_t)0x00000100) |
IWDG interrupt enable
| #define IWDG_IT_MASK ((uint32_t)0x00000100) |
IWDG interrupt mask
| #define IWDG_LOCK_KEY ((uint32_t)0x55AA6698) |
IWDG REG Write Access LOCK
| #define IWDG_MODE_INT ((uint32_t)0x00000010) |
IWDG interrupt mode
| #define IWDG_MODE_MASK ((uint32_t)0x00000010) |
IWDG mode mask
| #define IWDG_MODE_RESET ((uint32_t)0x00000000) |
IWDG reset mode
| #define IWDG_RELOAD_REFRESH ((uint32_t)0x000000AA) |
IWDG Peripheral Enable
| #define IWDG_RLR_MAX IWDG_RLOAD_IWDGRLOAD |
Watchdog counter reload max value
| #define IWDG_START_ENABLE ((uint32_t)0x00000055) |
IWDG Enable
| #define IWDG_UNLOCK_KEY ((uint32_t)0x55AA6699) |
IWDG Key Register value.
IWDG REG Write Access UNLOCK