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MG32L003 Standard Peripherals Firmware Library
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Type definitions for the System Control Block Registers. More...
Data Structures | |
| struct | SCB_Type |
| Structure type to access the System Control Block (SCB). More... | |
Macros | |
| #define | SCB_CPUID_IMPLEMENTER_Pos 24U |
| #define | SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
| #define | SCB_CPUID_VARIANT_Pos 20U |
| #define | SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
| #define | SCB_CPUID_ARCHITECTURE_Pos 16U |
| #define | SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
| #define | SCB_CPUID_PARTNO_Pos 4U |
| #define | SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
| #define | SCB_CPUID_REVISION_Pos 0U |
| #define | SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
| #define | SCB_ICSR_NMIPENDSET_Pos 31U |
| #define | SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
| #define | SCB_ICSR_PENDSVSET_Pos 28U |
| #define | SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
| #define | SCB_ICSR_PENDSVCLR_Pos 27U |
| #define | SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
| #define | SCB_ICSR_PENDSTSET_Pos 26U |
| #define | SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
| #define | SCB_ICSR_PENDSTCLR_Pos 25U |
| #define | SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
| #define | SCB_ICSR_ISRPREEMPT_Pos 23U |
| #define | SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
| #define | SCB_ICSR_ISRPENDING_Pos 22U |
| #define | SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
| #define | SCB_ICSR_VECTPENDING_Pos 12U |
| #define | SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
| #define | SCB_ICSR_VECTACTIVE_Pos 0U |
| #define | SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
| #define | SCB_AIRCR_VECTKEY_Pos 16U |
| #define | SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
| #define | SCB_AIRCR_VECTKEYSTAT_Pos 16U |
| #define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
| #define | SCB_AIRCR_ENDIANESS_Pos 15U |
| #define | SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
| #define | SCB_AIRCR_SYSRESETREQ_Pos 2U |
| #define | SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
| #define | SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
| #define | SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
| #define | SCB_SCR_SEVONPEND_Pos 4U |
| #define | SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
| #define | SCB_SCR_SLEEPDEEP_Pos 2U |
| #define | SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
| #define | SCB_SCR_SLEEPONEXIT_Pos 1U |
| #define | SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
| #define | SCB_CCR_STKALIGN_Pos 9U |
| #define | SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
| #define | SCB_CCR_UNALIGN_TRP_Pos 3U |
| #define | SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
| #define | SCB_SHCSR_SVCALLPENDED_Pos 15U |
| #define | SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
Type definitions for the System Control Block Registers.
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
SCB CCR: STKALIGN Mask
| #define SCB_CCR_STKALIGN_Pos 9U |
SCB CCR: STKALIGN Position
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
| #define SCB_ICSR_NMIPENDSET_Pos 31U |
SCB ICSR: NMIPENDSET Position
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position