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MG32L003 Standard Peripherals Firmware Library
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Macros | |
| #define | ADC_CLOCK_PCLK_DIV1 (0x00000000U) |
| #define | ADC_CLOCK_PCLK_DIV2 (ADC_CR0_CLKSEL_0) |
| #define | ADC_CLOCK_PCLK_DIV4 (ADC_CR0_CLKSEL_1) |
| #define | ADC_CLOCK_PCLK_DIV8 (ADC_CR0_CLKSEL_1 | ADC_CR0_CLKSEL_0) |
| #define | ADC_CLOCK_PCLK_DIV16 (ADC_CR0_CLKSEL_2) |
| #define | ADC_CLOCK_PCLK_DIV32 (ADC_CR0_CLKSEL_2 | ADC_CR0_CLKSEL_0) |
| #define | ADC_CLOCK_PCLK_DIV64 (ADC_CR0_CLKSEL_2 | ADC_CR0_CLKSEL_1) |
| #define | ADC_CLOCK_PCLK_DIV128 (ADC_CR0_CLKSEL_2 | ADC_CR0_CLKSEL_1 | ADC_CR0_CLKSEL_0) |
| #define | IS_ADC_CLOCK_PCLK_DIV(CLOCK) |
| #define ADC_CLOCK_PCLK_DIV1 (0x00000000U) |
Select ADC clock PCLK
| #define ADC_CLOCK_PCLK_DIV128 (ADC_CR0_CLKSEL_2 | ADC_CR0_CLKSEL_1 | ADC_CR0_CLKSEL_0) |
Select ADC clock PCLK/128
| #define ADC_CLOCK_PCLK_DIV16 (ADC_CR0_CLKSEL_2) |
Select ADC clock PCLK/16
| #define ADC_CLOCK_PCLK_DIV2 (ADC_CR0_CLKSEL_0) |
Select ADC clock PCLK/2
| #define ADC_CLOCK_PCLK_DIV32 (ADC_CR0_CLKSEL_2 | ADC_CR0_CLKSEL_0) |
Select ADC clock PCLK/32
| #define ADC_CLOCK_PCLK_DIV4 (ADC_CR0_CLKSEL_1) |
Select ADC clock PCLK/4
| #define ADC_CLOCK_PCLK_DIV64 (ADC_CR0_CLKSEL_2 | ADC_CR0_CLKSEL_1) |
Select ADC clock PCLK/64
| #define ADC_CLOCK_PCLK_DIV8 (ADC_CR0_CLKSEL_1 | ADC_CR0_CLKSEL_0) |
Select ADC clock PCLK/8
| #define IS_ADC_CLOCK_PCLK_DIV | ( | CLOCK | ) |