MG32F10x Standard Peripherals Firmware Library
Data Fields
SPI_TypeDef Struct Reference

Data Fields

__IOM uint32_t CR0
 
__IOM uint32_t CR1
 
__IOM uint32_t SPIENR
 
__IOM uint32_t MWCR
 
__IOM uint32_t SER
 
__IOM uint32_t BAUDR
 
__IOM uint32_t TXFTLR
 
__IOM uint32_t RXFTLR
 
__IM uint32_t TXFLR
 
__IM uint32_t RXFLR
 
__IM uint32_t SR
 
__IOM uint32_t IER
 
__IM uint32_t ISR
 
__IM uint32_t RISR
 
__IM uint32_t TXOICR
 
__IM uint32_t RXOICR
 
__IM uint32_t RXUICR
 
__IM uint32_t MSTICR
 
__IM uint32_t ICR
 
__IOM uint32_t DMACR
 
__IOM uint32_t DMATDLR
 
__IOM uint32_t DMARDLR
 
uint32_t RESERVED0 [2]
 
__IOM uint32_t DR
 
uint32_t RESERVED1 [35]
 
__IOM uint32_t RX_SAMPLE_DLY
 
__IOM uint32_t ESPICR
 

Field Documentation

◆ BAUDR

__IOM uint32_t BAUDR

Baud Rate Select, Address offset: 0x014

◆ CR0

__IOM uint32_t CR0

Control Register 0, Address offset: 0x000

◆ CR1

__IOM uint32_t CR1

Control Register 1, Address offset: 0x004

◆ DMACR

__IOM uint32_t DMACR

DMA Control Register, Address offset: 0x04C

◆ DMARDLR

__IOM uint32_t DMARDLR

DMA Receive Data Level, Address offset: 0x054

◆ DMATDLR

__IOM uint32_t DMATDLR

DMA Transmit Data Level, Address offset: 0x050

◆ DR

__IOM uint32_t DR

Data Register, Address offset: 0x060

◆ ESPICR

__IOM uint32_t ESPICR

Enhanced SPI Control Register, Address offset: 0x0F4

◆ ICR

__IM uint32_t ICR

Interrupt Clear Register, Address offset: 0x048

◆ IER

__IOM uint32_t IER

Interrupt Enable Register, Address offset: 0x02C

◆ ISR

__IM uint32_t ISR

Interrupt Status Register, Address offset: 0x030

◆ MSTICR

__IM uint32_t MSTICR

Multi-Master Interrupt Clear Register, Address offset: 0x044

◆ MWCR

__IOM uint32_t MWCR

Microwire Control Register, Address offset: 0x00C

◆ RESERVED0

uint32_t RESERVED0[2]

Reserved, 0x058 - 0x05C

◆ RESERVED1

uint32_t RESERVED1[35]

Reserved, 0x064 - 0x0EC

◆ RISR

__IM uint32_t RISR

Raw Interrupt Status Register, Address offset: 0x034

◆ RX_SAMPLE_DLY

__IOM uint32_t RX_SAMPLE_DLY

RX Sample Delay Register, Address offset: 0x0F0

◆ RXFLR

__IM uint32_t RXFLR

Receive FIFO Level Register, Address offset: 0x024

◆ RXFTLR

__IOM uint32_t RXFTLR

Receive FIFO Threshold Level, Address offset: 0x01C

◆ RXOICR

__IM uint32_t RXOICR

Receive FIFO Overflow Interrupt Clear Register, Address offset: 0x03C

◆ RXUICR

__IM uint32_t RXUICR

Receive FIFO Underflow Interrupt Clear Register, Address offset: 0x040

◆ SER

__IOM uint32_t SER

Slave Enable Register, Address offset: 0x010

◆ SPIENR

__IOM uint32_t SPIENR

SPI Enable Register, Address offset: 0x008

◆ SR

__IM uint32_t SR

Status Register, Address offset: 0x028

◆ TXFLR

__IM uint32_t TXFLR

Transmit FIFO Level Register, Address offset: 0x020

◆ TXFTLR

__IOM uint32_t TXFTLR

Transmit FIFO Threshold Level, Address offset: 0x018

◆ TXOICR

__IM uint32_t TXOICR

Transmit FIFO Overflow Interrupt Clear Register, Address offset: 0x038


The documentation for this struct was generated from the following file: