MG32F10x Standard Peripherals Firmware Library
Data Fields
ADC_TypeDef Struct Reference

Data Fields

__IOM uint32_t SR
 
__IOM uint32_t CR1
 
__IOM uint32_t CR2
 
__IOM uint32_t SMPR1
 
__IOM uint32_t SMPR2
 
__IOM uint32_t JOFR1
 
__IOM uint32_t JOFR2
 
__IOM uint32_t JOFR3
 
__IOM uint32_t JOFR4
 
__IOM uint32_t HTR
 
__IOM uint32_t LTR
 
__IOM uint32_t SQR1
 
__IOM uint32_t SQR2
 
__IOM uint32_t SQR3
 
__IOM uint32_t JSQR
 
__IOM uint32_t JDR1
 
__IOM uint32_t JDR2
 
__IOM uint32_t JDR3
 
__IOM uint32_t JDR4
 
__IOM uint32_t DR
 
__IOM uint32_t HS
 
__IOM uint32_t CR3
 
__IOM uint32_t JDMAR
 

Field Documentation

◆ CR1

__IOM uint32_t CR1

ADC control register 1, Address offset: 0x004

◆ CR2

__IOM uint32_t CR2

ADC control register 2, Address offset: 0x008

◆ CR3

__IOM uint32_t CR3

ADC control register 3, Address offset: 0x054

◆ DR

__IOM uint32_t DR

ADC regular data register, Address offset: 0x04C

◆ HS

__IOM uint32_t HS

ADC hold&sample control register, Address offset: 0x050

◆ HTR

__IOM uint32_t HTR

ADC watchdog high threshold register, Address offset: 0x024

◆ JDMAR

__IOM uint32_t JDMAR

Used for Injection channel DMA transfer, Address offset: 0x058

◆ JDR1

__IOM uint32_t JDR1

ADC injected data register 1, Address offset: 0x03C

◆ JDR2

__IOM uint32_t JDR2

ADC injected data register 2, Address offset: 0x040

◆ JDR3

__IOM uint32_t JDR3

ADC injected data register 3, Address offset: 0x044

◆ JDR4

__IOM uint32_t JDR4

ADC injected data register 4, Address offset: 0x048

◆ JOFR1

__IOM uint32_t JOFR1

ADC injected channel data offset register 1, Address offset: 0x014

◆ JOFR2

__IOM uint32_t JOFR2

ADC injected channel data offset register 2, Address offset: 0x018

◆ JOFR3

__IOM uint32_t JOFR3

ADC injected channel data offset register 3, Address offset: 0x01C

◆ JOFR4

__IOM uint32_t JOFR4

ADC injected channel data offset register 4, Address offset: 0x020

◆ JSQR

__IOM uint32_t JSQR

ADC injected sequence register, Address offset: 0x038

◆ LTR

__IOM uint32_t LTR

ADC watchdog low threshold register, Address offset: 0x028

◆ SMPR1

__IOM uint32_t SMPR1

ADC sample time register 1, Address offset: 0x00C

◆ SMPR2

__IOM uint32_t SMPR2

ADC sample time register 2, Address offset: 0x010

◆ SQR1

__IOM uint32_t SQR1

ADC regular sequence register 1, Address offset: 0x02C

◆ SQR2

__IOM uint32_t SQR2

ADC regular sequence register 2, Address offset: 0x030

◆ SQR3

__IOM uint32_t SQR3

ADC regular sequence register 3, Address offset: 0x034

◆ SR

__IOM uint32_t SR

ADC status register, Address offset: 0x000


The documentation for this struct was generated from the following file: