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__IOM uint32_t | CR1 |
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__IOM uint32_t | CR2 |
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__IOM uint32_t | SMCR |
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__IOM uint32_t | DIER |
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__IOM uint32_t | SR |
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__OM uint32_t | EGR |
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__IOM uint32_t | CCMR1 |
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__IOM uint32_t | CCMR2 |
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__IOM uint32_t | CCER |
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__IOM uint32_t | CNT |
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__IOM uint32_t | PSC |
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__IOM uint32_t | ARR |
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__IOM uint32_t | RCR |
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__IOM uint32_t | CCR1 |
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__IOM uint32_t | CCR2 |
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__IOM uint32_t | CCR3 |
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__IOM uint32_t | CCR4 |
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__IOM uint32_t | BDTR |
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◆ ARR
Auto-reload register, Address offset: 0x02C
◆ BDTR
Break and dead-time register, Address offset: 0x044
◆ CCER
Capture/compare enable register, Address offset: 0x020
◆ CCMR1
Capture/compare mode register 1, Address offset: 0x018
◆ CCMR2
Capture/compare mode register 2, Address offset: 0x01C
◆ CCR1
Capture/compare register 1, Address offset: 0x034
◆ CCR2
Capture/compare register 2, Address offset: 0x038
◆ CCR3
Capture/compare register 3, Address offset: 0x03C
◆ CCR4
Capture/compare register 4, Address offset: 0x040
◆ CNT
Counter, Address offset: 0x024
◆ CR1
Control register 1, Address offset: 0x000
◆ CR2
Control register 2, Address offset: 0x004
◆ DIER
DMA/interrupt enable register, Address offset: 0x00C
◆ EGR
Event generation register, Address offset: 0x014
◆ PSC
Prescaler, Address offset: 0x028
◆ RCR
Repetition counter register, Address offset: 0x030
◆ SMCR
Slave mode control register, Address offset: 0x008
◆ SR
Status register, Address offset: 0x010
The documentation for this struct was generated from the following file: