11 #ifndef __MG32F10x_DMAC_H 12 #define __MG32F10x_DMAC_H 36 FunctionalState DMAC_SourceGather;
37 uint32_t DMAC_SourceGatherCount;
38 uint32_t DMAC_SourceGatherInterval;
46 FunctionalState DMAC_DestinationScatter;
47 uint32_t DMAC_DestinationScatterCount;
48 uint32_t DMAC_DestinationScatterInterval;
156 #define DMAC_Interrupt_Enable ((uint32_t)0x00000001) 157 #define DMAC_Interrupt_Disable ((uint32_t)0x00000000) 166 #define DMAC_SourceTransferWidth_8b DMAC_CTLL_SRC_TR_WIDTH_8 167 #define DMAC_SourceTransferWidth_16b DMAC_CTLL_SRC_TR_WIDTH_16 168 #define DMAC_SourceTransferWidth_32b DMAC_CTLL_SRC_TR_WIDTH_32 177 #define DMAC_DestinationTransferWidth_8b DMAC_CTLL_DST_TR_WIDTH_8 178 #define DMAC_DestinationTransferWidth_16b DMAC_CTLL_DST_TR_WIDTH_16 179 #define DMAC_DestinationTransferWidth_32b DMAC_CTLL_DST_TR_WIDTH_32 188 #define DMAC_SourceAddrInc_Increment DMAC_CTLL_SINC_INC 189 #define DMAC_SourceAddrInc_Decrement DMAC_CTLL_SINC_DEC 190 #define DMAC_SourceAddrInc_NoChange DMAC_CTLL_SINC_NO 199 #define DMAC_DestinationAddrInc_Increment DMAC_CTLL_DINC_INC 200 #define DMAC_DestinationAddrInc_Decrement DMAC_CTLL_DINC_DEC 201 #define DMAC_DestinationAddrInc_NoChange DMAC_CTLL_DINC_NO 210 #define DMAC_SourceTransactionLength_1 DMAC_CTLL_SRC_MSIZE_1 211 #define DMAC_SourceTransactionLength_4 DMAC_CTLL_SRC_MSIZE_4 212 #define DMAC_SourceTransactionLength_8 DMAC_CTLL_SRC_MSIZE_8 221 #define DMAC_DestinationTransactionLength_1 DMAC_CTLL_DEST_MSIZE_1 222 #define DMAC_DestinationTransactionLength_4 DMAC_CTLL_DEST_MSIZE_4 223 #define DMAC_DestinationTransactionLength_8 DMAC_CTLL_DEST_MSIZE_8 232 #define DMAC_TransferTypeAndFlowControl_MemoryToMemory_DMAC DMAC_CTLL_TT_FC_M2M_DMAC 233 #define DMAC_TransferTypeAndFlowControl_MemoryToPeripheral_DMAC DMAC_CTLL_TT_FC_M2P_DMAC 234 #define DMAC_TransferTypeAndFlowControl_PeripheralToMemory_DMAC DMAC_CTLL_TT_FC_P2M_DMAC 235 #define DMAC_TransferTypeAndFlowControl_PeripheralToPeripheral_DMAC DMAC_CTLL_TT_FC_P2P_DMAC 237 #define DMAC_TransferTypeAndFlowControl_PeripheralToMemory_Peripheral DMAC_CTLL_TT_FC_P2M_PERIPH 238 #define DMAC_TransferTypeAndFlowControl_PeripheralToPeripheral_SourcePeripheral DMAC_CTLL_TT_FC_P2P_SRC_PERIPH 239 #define DMAC_TransferTypeAndFlowControl_MemoryToPeripheral_Peripheral DMAC_CTLL_TT_FC_M2P_PERIPH 240 #define DMAC_TransferTypeAndFlowControl_PeripheralToPeripheral_DestinationPeripheral DMAC_CTLL_TT_FC_P2P_DST_PERIPH 249 #define DMAC_SourceMasterInterface_APB (0x0U << 25) 250 #define DMAC_SourceMasterInterface_AHB (0x1U << 25) 259 #define DMAC_DestinationMasterInterface_APB (0x0U << 23) 260 #define DMAC_DestinationMasterInterface_AHB (0x1U << 23) 269 #define DMAC_SourceHandshakingInterfaceSelect_Hardware (0x0U << 11) 270 #define DMAC_SourceHandshakingInterfaceSelect_Software (0x1U << 11) 279 #define DMAC_DestinationHandshakingInterfaceSelect_Hardware (0x0U << 10) 280 #define DMAC_DestinationHandshakingInterfaceSelect_Software (0x1U << 10) 289 #define DMAC_SourceHandshakingInterfacePolarity_High (0x0U << 19) 290 #define DMAC_SourceHandshakingInterfacePolarity_Low (0x1U << 19) 299 #define DMAC_DestinationHandshakingInterfacePolarity_High (0x0U << 18) 300 #define DMAC_DestinationHandshakingInterfacePolarity_Low (0x1U << 18) 309 #define DMAC_AutomaticSourceReload_Enable (DMAC_CFGL_RELOAD_SRC) 310 #define DMAC_AutomaticSourceReload_Disable ((uint32_t)0x00000000) 319 #define DMAC_AutomaticDestinationReload_Enable (DMAC_CFGL_RELOAD_DST) 320 #define DMAC_AutomaticDestinationReload_Disable ((uint32_t)0x00000000) 329 #define DMAC_FlowControlMode_0 (0x0 << 0) 330 #define DMAC_FlowControlMode_1 (0x1 << 0) 339 #define DMAC_FIFOMode_0 (0x0 << 1) 340 #define DMAC_FIFOMode_1 (0x1 << 1) 350 #define DMAC_HardwareHandshakingInterface_TIM1_CH1__TIM2_UP__TIM3_CH3 0 351 #define DMAC_HardwareHandshakingInterface_TIM1_CH4__TIM1_TRIG__TIM1_COM__TIM4_CH2 1 352 #define DMAC_HardwareHandshakingInterface_TIM1_UP__TIM2_CH1__TIM4_CH3 2 353 #define DMAC_HardwareHandshakingInterface_TIM1_CH3__TIM3_CH1__TIM3_TRIG 3 354 #define DMAC_HardwareHandshakingInterface_TIM2_CH3__TIM4_CH1 4 355 #define DMAC_HardwareHandshakingInterface_TIM2_CH2__TIM2_CH4__TIM4_UP 5 356 #define DMAC_HardwareHandshakingInterface_TIM3_CH4__TIM3_UP__TIM1_CH2 6 357 #define DMAC_HardwareHandshakingInterface_QSPI_RX 7 358 #define DMAC_HardwareHandshakingInterface_QSPI_TX 8 359 #define DMAC_HardwareHandshakingInterface_SPIS1_RX 9 360 #define DMAC_HardwareHandshakingInterface_SPIS1_TX 10 361 #define DMAC_HardwareHandshakingInterface_UART1_RX 11 362 #define DMAC_HardwareHandshakingInterface_UART1_TX 12 363 #define DMAC_HardwareHandshakingInterface_ADC_Regular 13 364 #define DMAC_HardwareHandshakingInterface_ADC_Injected 14 367 #define DMAC_HardwareHandshakingInterface_SPIM2_RX 0 368 #define DMAC_HardwareHandshakingInterface_SPIM2_TX 1 369 #define DMAC_HardwareHandshakingInterface_SPIS2_RX 2 370 #define DMAC_HardwareHandshakingInterface_SPIS2_TX 3 371 #define DMAC_HardwareHandshakingInterface_UART2_RX 4 372 #define DMAC_HardwareHandshakingInterface_UART2_TX 5 373 #define DMAC_HardwareHandshakingInterface_UART3_RX 6 374 #define DMAC_HardwareHandshakingInterface_UART3_TX 7 375 #define DMAC_HardwareHandshakingInterface_I2C1_RX 8 376 #define DMAC_HardwareHandshakingInterface_I2C1_TX 9 377 #define DMAC_HardwareHandshakingInterface_I2C2_RX 10 378 #define DMAC_HardwareHandshakingInterface_I2C2_TX 11 387 #define DMAC_Channel_0 ((uint8_t)0x00) 388 #define DMAC_Channel_1 ((uint8_t)0x01) 389 #define DMAC_Channel_2 ((uint8_t)0x02) 398 #define DMAC_IT_TFR ((uint16_t)0x0000) 399 #define DMAC_IT_BLOCK ((uint16_t)0x0008) 400 #define DMAC_IT_SRCTRAN ((uint16_t)0x0010) 401 #define DMAC_IT_DSTTRAN ((uint16_t)0x0018) 402 #define DMAC_IT_ERR ((uint16_t)0x0020) SignalState DMAC_SWHS_GetLstDstSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel)
Returns the state of LstDst signal for the corresponding channel.
Definition: mg32f10x_dmac.c:910
uint8_t DMAC_ProtectionControl
Definition: mg32f10x_dmac.h:128
SignalState DMAC_SWHS_GetSglReqDstSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel)
Returns the state of SglReqDst signal for the corresponding channel.
Definition: mg32f10x_dmac.c:854
DMAC Destination Scatter Structure definition.
Definition: mg32f10x_dmac.h:44
uint32_t DMAC_FIFOMode
Definition: mg32f10x_dmac.h:121
uint32_t DMAC_DestinationHandshakingInterfaceSelect
Definition: mg32f10x_dmac.h:100
void DMAC_ChannelCmd(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, FunctionalState NewState)
Enables or disables the specified DMACx Channely.
Definition: mg32f10x_dmac.c:391
uint32_t DMAC_Interrupt
Definition: mg32f10x_dmac.h:60
DMAC Channel Init Structure definition.
Definition: mg32f10x_dmac.h:54
DMAC Source Gather Structure definition.
Definition: mg32f10x_dmac.h:34
void DMAC_SWHS_SetReqDstSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, SignalState NewState)
Controls the state of ReqDst signal for the corresponding channels.
Definition: mg32f10x_dmac.c:640
void DMAC_DeInit(DMAC_TypeDef *DMACx)
Deinitializes the DMACx peripheral registers to their default reset values.
Definition: mg32f10x_dmac.c:40
uint32_t DMAC_SourceHandshakingInterfacePolarity
Definition: mg32f10x_dmac.h:104
uint32_t DMAC_SourceAddrInc
Definition: mg32f10x_dmac.h:69
uint8_t DMAC_ChannelPriority
Definition: mg32f10x_dmac.h:124
uint32_t DMAC_DestinationAddrInc
Definition: mg32f10x_dmac.h:72
void DMAC_Channel_StructInit(DMAC_Channel_InitTypeDef *DMAC_Channel_InitStruct)
Fills each DMAC_Channel_InitStruct member with its default value.
Definition: mg32f10x_dmac.c:109
uint32_t DMAC_SourceBaseAddr
Definition: mg32f10x_dmac.h:56
void DMAC_SWHS_SetReqSrcSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, SignalState NewState)
Controls the state of ReqSrc signal for the corresponding channels.
Definition: mg32f10x_dmac.c:614
void DMAC_Channel_SourceGatherConfig(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, DMAC_SourceGatherInitTypeDef *DMAC_SourceGatherInitStruct)
Initializes the source gather of DMACx Channely.
Definition: mg32f10x_dmac.c:165
void DMAC_Cmd(DMAC_TypeDef *DMACx, FunctionalState NewState)
Enables or disables the specified DMACx peripheral.
Definition: mg32f10x_dmac.c:345
uint8_t DMAC_DestinationHardwareHandshakingInterfaceAssign
Definition: mg32f10x_dmac.h:137
ITStatus DMAC_GetITStatus(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, uint16_t DMAC_IT)
Checks whether the specified DMACx Channely interrupt has occurred or not.
Definition: mg32f10x_dmac.c:524
uint16_t DMAC_MaximumAMBABurstLength
Definition: mg32f10x_dmac.h:141
void DMAC_Channel_SuspendCmd(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, FunctionalState NewState)
Forces or releases the current DMACx Channely transfer suspend.
Definition: mg32f10x_dmac.c:295
void DMAC_ITConfig(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, uint16_t DMAC_IT, FunctionalState NewState)
Enables or disables the specified DMACx Channely interrupts.
Definition: mg32f10x_dmac.c:452
void DMAC_ClearITPendingBit(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, uint16_t DMAC_IT)
Clears the DMACx's interrupt pending bits.
Definition: mg32f10x_dmac.c:590
uint16_t DMAC_Channel_GetBlockTransferSize(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel)
Returns the number of remaining data units in the current DMACx Channely block transfer.
Definition: mg32f10x_dmac.c:276
uint8_t DMAC_SourceHardwareHandshakingInterfaceAssign
Definition: mg32f10x_dmac.h:133
void DMAC_SWHS_SetSglReqSrcSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, SignalState NewState)
Controls the state of SglReqSrc signal for the corresponding channels.
Definition: mg32f10x_dmac.c:666
uint32_t DMAC_AutomaticSourceReload
Definition: mg32f10x_dmac.h:110
Definition: mg32f10x.h:521
uint32_t DMAC_AutomaticDestinationReload
Definition: mg32f10x_dmac.h:114
SignalState DMAC_SWHS_GetSglReqSrcSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel)
Returns the state of SglReqSrc signal for the corresponding channel.
Definition: mg32f10x_dmac.c:826
uint32_t DMAC_DestinationHandshakingInterfacePolarity
Definition: mg32f10x_dmac.h:107
void DMAC_Channel_SetDestinationAddress(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, uint32_t DestinationAddress)
Sets the destination address of the specified DMACx Channely.
Definition: mg32f10x_dmac.c:240
void DMAC_Channel_Init(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, DMAC_Channel_InitTypeDef *DMAC_Channel_InitStruct)
Initializes the DMACx Channely according to the specified parameters in the DMAC_Channel_InitStruct s...
Definition: mg32f10x_dmac.c:69
FlagStatus DMAC_Channel_IsFIFOEmpty(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel)
Checks whether the DMACx Channely FIFO is empty or not.
Definition: mg32f10x_dmac.c:317
void DMAC_Channel_SetSourceAddress(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, uint32_t SourceAddress)
Sets the source address of the specified DMACx Channely.
Definition: mg32f10x_dmac.c:222
SignalState DMAC_SWHS_GetLstSrcSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel)
Returns the state of LstSrc signal for the corresponding channel.
Definition: mg32f10x_dmac.c:882
FunctionalState DMAC_GetCmdStatus(DMAC_TypeDef *DMACx)
Returns the status of EN bit for the specified DMACx.
Definition: mg32f10x_dmac.c:362
ITStatus DMAC_GetCombinedITStatus(DMAC_TypeDef *DMACx, uint16_t DMAC_IT)
Checks whether the specified DMACx interrupt has occurred or not.
Definition: mg32f10x_dmac.c:555
void DMAC_SWHS_SetLstDstSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, SignalState NewState)
Controls the state of LstDst signal for the corresponding channels.
Definition: mg32f10x_dmac.c:744
FunctionalState DMAC_GetChannelCmdStatus(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel)
Returns the status of EN bit for the specified DMACx Channely.
Definition: mg32f10x_dmac.c:415
uint32_t DMAC_SourceTransactionLength
Definition: mg32f10x_dmac.h:75
void DMAC_Channel_SetBlockTransferSize(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, uint16_t DMAC_BlockTransferSize)
Sets the number of data units to be transferred on the block transfer.
Definition: mg32f10x_dmac.c:259
uint32_t DMAC_BlockTransferSize
Definition: mg32f10x_dmac.h:92
void DMAC_Channel_DestinationScatterConfig(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, DMAC_DestinationScatterInitTypeDef *DMAC_DestinationScatterInitStruct)
Initializes the destination scatter of DMACx Channely.
Definition: mg32f10x_dmac.c:194
SignalState DMAC_SWHS_GetReqDstSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel)
Returns the state of ReqDst signal for the corresponding channel.
Definition: mg32f10x_dmac.c:798
uint32_t DMAC_TransferTypeAndFlowControl
Definition: mg32f10x_dmac.h:83
uint32_t DMAC_DestinationTransferWidth
Definition: mg32f10x_dmac.h:66
void DMAC_SWHS_SetSglReqDstSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, SignalState NewState)
Controls the state of SglReqDst signal for the corresponding channels.
Definition: mg32f10x_dmac.c:692
SignalState DMAC_SWHS_GetReqSrcSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel)
Returns the state of ReqSrc signal for the corresponding channel.
Definition: mg32f10x_dmac.c:770
uint32_t DMAC_DestinationTransactionLength
Definition: mg32f10x_dmac.h:79
uint32_t DMAC_DestinationMasterInterface
Definition: mg32f10x_dmac.h:89
uint32_t DMAC_SourceHandshakingInterfaceSelect
Definition: mg32f10x_dmac.h:96
void DMAC_SWHS_SetLstSrcSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, SignalState NewState)
Controls the state of LstSrc signal for the corresponding channels.
Definition: mg32f10x_dmac.c:718
uint32_t DMAC_SourceTransferWidth
Definition: mg32f10x_dmac.h:63
uint32_t DMAC_DestinationBaseAddr
Definition: mg32f10x_dmac.h:58
ITStatus DMAC_GetRawITStatus(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, uint16_t DMAC_IT)
Checks whether the specified DMACx Channely raw interrupt status.
Definition: mg32f10x_dmac.c:488
uint32_t DMAC_SourceMasterInterface
Definition: mg32f10x_dmac.h:86
uint32_t DMAC_FlowControlMode
Definition: mg32f10x_dmac.h:118