|
#define | DMAC_HardwareHandshakingInterface_TIM1_CH1__TIM2_UP__TIM3_CH3 0 |
|
#define | DMAC_HardwareHandshakingInterface_TIM1_CH4__TIM1_TRIG__TIM1_COM__TIM4_CH2 1 |
|
#define | DMAC_HardwareHandshakingInterface_TIM1_UP__TIM2_CH1__TIM4_CH3 2 |
|
#define | DMAC_HardwareHandshakingInterface_TIM1_CH3__TIM3_CH1__TIM3_TRIG 3 |
|
#define | DMAC_HardwareHandshakingInterface_TIM2_CH3__TIM4_CH1 4 |
|
#define | DMAC_HardwareHandshakingInterface_TIM2_CH2__TIM2_CH4__TIM4_UP 5 |
|
#define | DMAC_HardwareHandshakingInterface_TIM3_CH4__TIM3_UP__TIM1_CH2 6 |
|
#define | DMAC_HardwareHandshakingInterface_QSPI_RX 7 |
|
#define | DMAC_HardwareHandshakingInterface_QSPI_TX 8 |
|
#define | DMAC_HardwareHandshakingInterface_SPIS1_RX 9 |
|
#define | DMAC_HardwareHandshakingInterface_SPIS1_TX 10 |
|
#define | DMAC_HardwareHandshakingInterface_UART1_RX 11 |
|
#define | DMAC_HardwareHandshakingInterface_UART1_TX 12 |
|
#define | DMAC_HardwareHandshakingInterface_ADC_Regular 13 |
|
#define | DMAC_HardwareHandshakingInterface_ADC_Injected 14 |
|
#define | DMAC_HardwareHandshakingInterface_SPIM2_RX 0 |
|
#define | DMAC_HardwareHandshakingInterface_SPIM2_TX 1 |
|
#define | DMAC_HardwareHandshakingInterface_SPIS2_RX 2 |
|
#define | DMAC_HardwareHandshakingInterface_SPIS2_TX 3 |
|
#define | DMAC_HardwareHandshakingInterface_UART2_RX 4 |
|
#define | DMAC_HardwareHandshakingInterface_UART2_TX 5 |
|
#define | DMAC_HardwareHandshakingInterface_UART3_RX 6 |
|
#define | DMAC_HardwareHandshakingInterface_UART3_TX 7 |
|
#define | DMAC_HardwareHandshakingInterface_I2C1_RX 8 |
|
#define | DMAC_HardwareHandshakingInterface_I2C1_TX 9 |
|
#define | DMAC_HardwareHandshakingInterface_I2C2_RX 10 |
|
#define | DMAC_HardwareHandshakingInterface_I2C2_TX 11 |
|