25 #if defined ( __ICCARM__ ) 26 #pragma system_include 27 #elif defined (__clang__) 28 #pragma clang system_header 31 #ifndef ARM_MPU_ARMV7_H 32 #define ARM_MPU_ARMV7_H 34 #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) 35 #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) 36 #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) 37 #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) 38 #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) 39 #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) 40 #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) 41 #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) 42 #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) 43 #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) 44 #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) 45 #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) 46 #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) 47 #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) 48 #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) 49 #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) 50 #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) 51 #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) 52 #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) 53 #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) 54 #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) 55 #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) 56 #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) 57 #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) 58 #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) 59 #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) 60 #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) 61 #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) 63 #define ARM_MPU_AP_NONE 0U 64 #define ARM_MPU_AP_PRIV 1U 65 #define ARM_MPU_AP_URO 2U 66 #define ARM_MPU_AP_FULL 3U 67 #define ARM_MPU_AP_PRO 5U 68 #define ARM_MPU_AP_RO 6U 75 #define ARM_MPU_RBAR(Region, BaseAddress) \ 76 (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ 77 ((Region) & MPU_RBAR_REGION_Msk) | \ 88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ 89 ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ 90 (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ 91 (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ 92 (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) 103 #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ 104 ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ 105 (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ 106 (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) 120 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ 121 ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) 130 #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) 141 #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) 154 #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) 159 #define ARM_MPU_CACHEP_NOCACHE 0U 164 #define ARM_MPU_CACHEP_WB_WRA 1U 169 #define ARM_MPU_CACHEP_WT_NWA 2U 174 #define ARM_MPU_CACHEP_WB_NWA 3U 188 __STATIC_INLINE
void ARM_MPU_Enable(uint32_t MPU_Control)
192 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
193 #ifdef SCB_SHCSR_MEMFAULTENA_Msk 200 __STATIC_INLINE
void ARM_MPU_Disable(
void)
204 #ifdef SCB_SHCSR_MEMFAULTENA_Msk 207 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
213 __STATIC_INLINE
void ARM_MPU_ClrRegion(uint32_t rnr)
223 __STATIC_INLINE
void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
234 __STATIC_INLINE
void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
246 __STATIC_INLINE
void orderedCpy(
volatile uint32_t* dst,
const uint32_t* __RESTRICT src, uint32_t len)
249 for (i = 0U; i < len; ++i)
259 __STATIC_INLINE
void ARM_MPU_Load(
ARM_MPU_Region_t const* table, uint32_t cnt)
262 while (cnt > MPU_TYPE_RALIASES) {
263 orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
264 table += MPU_TYPE_RALIASES;
265 cnt -= MPU_TYPE_RALIASES;
267 orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
Definition: mpu_armv7.h:180
uint32_t RASR
The region attribute and size register value (RASR) MPU_RASR.
Definition: mpu_armv7.h:182
uint32_t RBAR
The region base address register value (RBAR)
Definition: mpu_armv7.h:181
#define SCB_SHCSR_MEMFAULTENA_Msk
Definition: core_cm3.h:517
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: cmsis_gcc.h:877
#define SCB
Definition: core_cm3.h:1393
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: cmsis_gcc.h:866