◆ BGCR2
BandGap control register 2, Address offset: 0x01C
◆ CMPACR
CMPA control register, Address offset: 0x098
◆ CMPASR
CMPA status register, Address offset: 0x0AC
◆ CMPBCR
CMPB control register, Address offset: 0x09C
◆ CMPBSR
CMPB status register, Address offset: 0x0B0
◆ DCSSCR
DCSS control register, Address offset: 0x0B8
◆ DCSSENR
DCSS enable register, Address offset: 0x0B4
◆ FHSIENR
FHSI enable register, Address offset: 0x038
◆ FHSISR
FHSI status register, Address offset: 0x03C
◆ HSECR0
HSE control register 0, Address offset: 0x04C
◆ HSECR1
HSE control register 1, Address offset: 0x050
◆ HSESR
HSE status register, Address offset: 0x058
◆ ICR
Interrupt clear register, Address offset: 0x0A8
◆ IER
Interrupt enable register, Address offset: 0x0A4
◆ ISR
Interrupt status register, Address offset: 0x0A0
◆ LSIENR
LSI enable register, Address offset: 0x044
◆ LSISR
LSI status register, Address offset: 0x048
◆ MHSIENR
MHSI enable register, Address offset: 0x02C
◆ MHSISR
MHSI status register, Address offset: 0x030
◆ PLLCR
PLL control register, Address offset: 0x074
◆ PLLENR
PLl enable register, Address offset: 0x078
◆ PLLSR
PLL status register, Address offset: 0x07C
◆ PORCR
POR control register, Address offset: 0x094
◆ PVDCR
PVD control register, Address offset: 0x080
◆ PVDENR
PVD enable register, Address offset: 0x084
◆ RESERVED0
◆ RESERVED1
◆ RESERVED2
◆ RESERVED3
◆ RESERVED4
◆ RESERVED5
◆ RESERVED6
◆ SARENR
SAR ADC enable register, Address offset: 0x08C
◆ USBPCR
USB PHY control register, Address offset: 0x090
The documentation for this struct was generated from the following file: