MG32F10x Standard Peripherals Firmware Library
Data Fields
RTC_TypeDef Struct Reference

Data Fields

__IOM uint16_t CRH
 
uint16_t RESERVED0
 
__IOM uint16_t CRL
 
uint16_t RESERVED1
 
__OM uint16_t PRLH
 
uint16_t RESERVED2
 
union {
   __IM uint32_t   PRL
 
   __OM uint16_t   PRLL
 
}; 
 
__IM uint16_t DIVH
 
uint16_t RESERVED4
 
union {
   __IM uint32_t   DIV
 
   __IM uint16_t   DIVL
 
}; 
 
__IOM uint16_t CNTH
 
uint16_t RESERVED5
 
union {
   __IM uint32_t   CNT
 
   __IOM uint16_t   CNTL
 
}; 
 
__OM uint16_t ALRH
 
uint16_t RESERVED6
 
union {
   __IM uint32_t   ALR
 
   __OM uint16_t   ALRL
 
}; 
 

Field Documentation

◆ ALR

__IM uint32_t ALR

RTC alarm register (read only), Address offset: 0x024

◆ ALRH

__OM uint16_t ALRH

RTC alarm register high, Address offset: 0x020

◆ ALRL

__OM uint16_t ALRL

RTC alarm register low, Address offset: 0x024

◆ CNT

__IM uint32_t CNT

RTC counter register (read only), Address offset: 0x01C

◆ CNTH

__IOM uint16_t CNTH

RTC counter register high, Address offset: 0x018

◆ CNTL

__IOM uint16_t CNTL

RTC counter register low, Address offset: 0x01C

◆ CRH

__IOM uint16_t CRH

RTC control register high, Address offset: 0x000

◆ CRL

__IOM uint16_t CRL

RTC control register low, Address offset: 0x004

◆ DIV

__IM uint32_t DIV

RTC prescaler divider register, Address offset: 0x014

◆ DIVH

__IM uint16_t DIVH

RTC prescaler divider register high, Address offset: 0x010

◆ DIVL

__IM uint16_t DIVL

RTC prescaler divider register low, Address offset: 0x014

◆ PRL

__IM uint32_t PRL

RTC prescaler load register (read only), Address offset: 0x00C

◆ PRLH

__OM uint16_t PRLH

RTC prescaler load register high, Address offset: 0x008

◆ PRLL

__OM uint16_t PRLL

RTC prescaler load register low, Address offset: 0x00C


The documentation for this struct was generated from the following file: