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__IOM uint32_t | IER |
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__IOM uint32_t | IRER |
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__IOM uint32_t | ITER |
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__IOM uint32_t | CER |
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__IOM uint32_t | CCR |
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__OM uint32_t | RXFFR |
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__OM uint32_t | TXFFR |
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uint32_t | RESERVED0 |
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struct { |
union { |
__IM uint32_t LRBR |
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__OM uint32_t LTHR |
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} | |
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union { |
__IM uint32_t RRBR |
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__OM uint32_t RTHR |
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} | |
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__IOM uint32_t RER |
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__IOM uint32_t TER |
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__IOM uint32_t RCR |
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__IOM uint32_t TCR |
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__IM uint32_t ISR |
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__IOM uint32_t IMR |
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__IM uint32_t ROR |
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__IM uint32_t TOR |
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__IOM uint32_t RFCR |
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__IOM uint32_t TFCR |
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__OM uint32_t RFF |
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__OM uint32_t TFF |
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uint32_t RESERVED0 |
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uint32_t RESERVED1 |
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} | Ch [2] |
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__IM uint32_t | RXDMA |
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__OM uint32_t | RRXDMA |
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__OM uint32_t | TXDMA |
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__OM uint32_t | RTXDMA |
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◆ CCR
Clock Configuration Register, Address offset: 0x010
◆ CER
Clock Enable Register, Address offset: 0x00C
◆ IER
I2S Enable Register, Address offset: 0x000
◆ IMR
Interrupt Mask Register, Address offset: 0x03C, 0x07C
◆ IRER
I2S Receiver Block Enable Register, Address offset: 0x004
◆ ISR
Interrupt Status Register, Address offset: 0x038, 0x078
◆ ITER
I2S Transmitter Block Enable Register, Address offset: 0x008
◆ LRBR
Left Receive Buffer Register, Address offset: 0x020, 0x060
◆ LTHR
Left Transmit Holding Register, Address offset: 0x020, 0x060
◆ RCR
Receive Configuration Register, Address offset: 0x030, 0x070
◆ RER
Receive Enable Register, Address offset: 0x028, 0x068
◆ RESERVED0
◆ RESERVED1
◆ RFCR
Receive FIFO Configuration Register, Address offset: 0x048, 0x088
◆ RFF
Receive FIFO Flush Register, Address offset: 0x050, 0x090
◆ ROR
Receive Overrun Register, Address offset: 0x040, 0x080
◆ RRBR
Right Receive Buffer Register, Address offset: 0x024, 0x064
◆ RRXDMA
Reset Receiver Block DMA Register, Address offset: 0x1C4
◆ RTHR
Right Transmit Holding Register, Address offset: 0x024, 0x064
◆ RTXDMA
Reset Transmitter Block DMA Register, Address offset: 0x1CC
◆ RXDMA
Receiver Block DMA Register, Address offset: 0x1C0
◆ RXFFR
Receiver Block FIFO Reset Register, Address offset: 0x014
◆ TCR
Transmit Configuration Register, Address offset: 0x034, 0x074
◆ TER
Transmit Enable Register, Address offset: 0x02C, 0x06C
◆ TFCR
Transmit FIFO Configuration Register, Address offset: 0x04C, 0x08C
◆ TFF
Transmit FIFO Flush Register, Address offset: 0x054, 0x094
◆ TOR
Transmit Overrun Register, Address offset: 0x044, 0x084
◆ TXDMA
Transmitter Block DMA Register, Address offset: 0x1C8
◆ TXFFR
Transmitter Block FIFO Reset Register, Address offset: 0x018
The documentation for this struct was generated from the following file: