11 #ifndef __MG32F10x_I2C_H 12 #define __MG32F10x_I2C_H 39 #define I2C_TARGETADDRESS_GENERAL_CALL (I2C_TAR_SPECIAL) 40 #define I2C_TARGETADDRESS_START_BYTE (I2C_TAR_SPECIAL | I2C_TAR_GC_OR_START) 41 #define I2C_TARGETADDRESS_DEVICE_ID (I2C_TAR_SPECIAL | I2C_TAR_DEVICE_ID) 42 #define I2C_TARGETADDRESS_SMBUS_QUICK_CMD (I2C_TAR_SPECIAL | I2C_TAR_SMBUS_QUICK_CMD) 51 #define I2C_FLAG_ACTIVITY I2C_STATUS_ACTIVITY 52 #define I2C_FLAG_TFNF I2C_STATUS_TFNF 53 #define I2C_FLAG_TFE I2C_STATUS_TFE 54 #define I2C_FLAG_RFNE I2C_STATUS_RFNE 55 #define I2C_FLAG_RFF I2C_STATUS_RFF 56 #define I2C_FLAG_MST_ACTIVITY I2C_STATUS_MST_ACTIVITY 57 #define I2C_FLAG_SLV_ACTIVITY I2C_STATUS_SLV_ACTIVITY 58 #define I2C_FLAG_MST_HOLD_TX_FIFO_EMPTY I2C_STATUS_MST_HOLD_TX_FIFO_EMPTY 59 #define I2C_FLAG_MST_HOLD_RX_FIFO_FULL I2C_STATUS_MST_HOLD_RX_FIFO_FULL 60 #define I2C_FLAG_SLV_HOLD_TX_FIFO_EMPTY I2C_STATUS_SLV_HOLD_TX_FIFO_EMPTY 61 #define I2C_FLAG_SLV_HOLD_RX_FIFO_FULL I2C_STATUS_SLV_HOLD_RX_FIFO_FULL 62 #define I2C_FLAG_SDA_STUCK_NOT_RECOVERED I2C_STATUS_SDA_STUCK_NOT_RECOVERED 63 #define I2C_FLAG_SMBUS_QUICK_CMD_BIT I2C_STATUS_SMBUS_QUICK_CMD_BIT 64 #define I2C_FLAG_SMBUS_SLAVE_ADDR_VALID I2C_STATUS_SMBUS_SLAVE_ADDR_VALID 65 #define I2C_FLAG_SMBUS_SLAVE_ADDR_RESOLVED I2C_STATUS_SMBUS_SLAVE_ADDR_RESOLVED 66 #define I2C_FLAG_SMBUS_SUSPEND_STATUS I2C_STATUS_SMBUS_SUSPEND_STATUS 67 #define I2C_FLAG_SMBUS_ALERT_STATUS I2C_STATUS_SMBUS_ALERT_STATUS 76 #define I2C_IT_RX_UNDER I2C_INTR_RX_UNDER 77 #define I2C_IT_RX_OVER I2C_INTR_RX_OVER 78 #define I2C_IT_RX_FULL I2C_INTR_RX_FULL 79 #define I2C_IT_TX_OVER I2C_INTR_TX_OVER 80 #define I2C_IT_TX_EMPTY I2C_INTR_TX_EMPTY 81 #define I2C_IT_RD_REQ I2C_INTR_RD_REQ 82 #define I2C_IT_TX_ABRT I2C_INTR_TX_ABRT 83 #define I2C_IT_RX_DONE I2C_INTR_RX_DONE 84 #define I2C_IT_ACTIVITY I2C_INTR_ACTIVITY 85 #define I2C_IT_STOP_DET I2C_INTR_STOP_DET 86 #define I2C_IT_START_DET I2C_INTR_START_DET 87 #define I2C_IT_GEN_CALL I2C_INTR_GEN_CALL 88 #define I2C_IT_RESTART_DET I2C_INTR_RESTART_DET 89 #define I2C_IT_SCL_STUCK_AT_LOW I2C_INTR_SCL_STUCK_AT_LOW 98 #define I2C_SMBUS_IT_SLV_CLOCK_EXTND_TIMEOUT I2C_SMBUS_INTR_SLV_CLOCK_EXTND_TIMEOUT 99 #define I2C_SMBUS_IT_MST_CLOCK_EXTND_TIMEOUT I2C_SMBUS_INTR_MST_CLOCK_EXTND_TIMEOUT 100 #define I2C_SMBUS_IT_QUICK_CMD_DET I2C_SMBUS_INTR_QUICK_CMD_DET 101 #define I2C_SMBUS_IT_HOST_NTFY_MST_DET I2C_SMBUS_INTR_HOST_NTFY_MST_DET 102 #define I2C_SMBUS_IT_ARP_PREPARE_CMD_DET I2C_SMBUS_INTR_ARP_PREPARE_CMD_DET 103 #define I2C_SMBUS_IT_ARP_RST_CMD_DET I2C_SMBUS_INTR_ARP_RST_CMD_DET 104 #define I2C_SMBUS_IT_ARP_GET_UDID_CMD_DET I2C_SMBUS_INTR_ARP_GET_UDID_CMD_DET 105 #define I2C_SMBUS_IT_ARP_ASSGN_ADDR_CMD_DET I2C_SMBUS_INTR_ARP_ASSGN_ADDR_CMD_DET 106 #define I2C_SMBUS_IT_SLV_RX_PEC_NACK I2C_SMBUS_INTR_SLV_RX_PEC_NACK 107 #define I2C_SMBUS_IT_SMBUS_SUSPEND_DET I2C_SMBUS_INTR_SMBUS_SUSPEND_DET 108 #define I2C_SMBUS_IT_SMBUS_ALERT_DET I2C_SMBUS_INTR_SMBUS_ALERT_DET 117 #define I2C_DMAReq_Rx I2C_DMA_CR_RDMAE 118 #define I2C_DMAReq_Tx I2C_DMA_CR_TDMAE void I2C_Init(I2C_TypeDef *I2Cx, uint32_t I2C_CON)
Initializes the I2Cx peripheral according to the specified parameters in the I2C_InitStruct.
Definition: mg32f10x_i2c.c:64
void I2C_RxFIFOThresholdConfig(I2C_TypeDef *I2Cx, uint8_t Threshold)
Configures the Receive FIFO threshold.
Definition: mg32f10x_i2c.c:457
void I2C_DMATxReqLevelConfig(I2C_TypeDef *I2Cx, uint8_t Level)
Configures the DMA Tx request level.
Definition: mg32f10x_i2c.c:521
void I2C_WriteDataCmd(I2C_TypeDef *I2Cx, uint16_t I2C_DataCmd)
Write data and command Tx FIFO.
Definition: mg32f10x_i2c.c:224
uint8_t I2C_GetRxFIFOLevel(I2C_TypeDef *I2Cx)
Returns the number of valid data entries in the receive FIFO buffer.
Definition: mg32f10x_i2c.c:483
void I2C_TxFIFOThresholdConfig(I2C_TypeDef *I2Cx, uint8_t Threshold)
Configures the Transmit FIFO threshold.
Definition: mg32f10x_i2c.c:471
void I2C_SlaveDataNAckOnlyConfig(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables generate NACK after data byte received when as slave-receiver.
Definition: mg32f10x_i2c.c:175
ITStatus I2C_GetRawITStatus(I2C_TypeDef *I2Cx, uint16_t I2C_IT)
Checks whether the specified I2Cx raw interrupt status.
Definition: mg32f10x_i2c.c:336
void I2C_OwnAddressConfig(I2C_TypeDef *I2Cx, uint16_t Address)
Configures the specified I2C own address.
Definition: mg32f10x_i2c.c:90
void I2C_SCLStuckAtLowTimeoutConfig(I2C_TypeDef *I2Cx, uint32_t Timeout)
Configures the specified I2C SCL stuck at low timeout.
Definition: mg32f10x_i2c.c:128
void I2C_SMBus_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBUS_IT, FunctionalState NewState)
Enables or disables the specified SMBus interrupts.
Definition: mg32f10x_i2c.c:571
void I2C_DeInit(I2C_TypeDef *I2Cx)
Deinitializes the I2Cx peripheral registers to their default reset values.
Definition: mg32f10x_i2c.c:40
void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint16_t I2C_IT)
Clears the I2Cx's interrupt pending bits.
Definition: mg32f10x_i2c.c:418
void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C peripheral.
Definition: mg32f10x_i2c.c:155
void I2C_SMBus_ClearITPendingBit(I2C_TypeDef *I2Cx, uint16_t I2C_SMBUS_IT)
Clears the I2Cx's interrupt pending bits.
Definition: mg32f10x_i2c.c:683
FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
Checks whether the specified I2C flag is set or not.
Definition: mg32f10x_i2c.c:255
ITStatus I2C_SMBus_GetITStatus(I2C_TypeDef *I2Cx, uint16_t I2C_SMBUS_IT)
Checks whether the specified SMBus interrupt has occurred or not.
Definition: mg32f10x_i2c.c:644
void I2C_AckGeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the General Call ACK Generate.
Definition: mg32f10x_i2c.c:194
void I2C_TargetAddressConfig(I2C_TypeDef *I2Cx, uint32_t TargetAddress)
Configures the specified I2C target address.
Definition: mg32f10x_i2c.c:77
ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint16_t I2C_IT)
Checks whether the specified I2Cx interrupt has occurred or not.
Definition: mg32f10x_i2c.c:378
void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState)
Enables or disables the specified I2C interrupts.
Definition: mg32f10x_i2c.c:299
uint8_t I2C_GetTxFIFOLevel(I2C_TypeDef *I2Cx)
Returns the number of valid data entries in the transmit FIFO buffer.
Definition: mg32f10x_i2c.c:495
Definition: mg32f10x.h:606
void I2C_HighSpeedModeMasterCodeConfig(I2C_TypeDef *I2Cx, uint8_t Code)
Configures the I2C HS mode master code.
Definition: mg32f10x_i2c.c:103
uint32_t I2C_GetTxAbortSource(I2C_TypeDef *I2Cx)
Returns the transmit abort source for the specified I2C.
Definition: mg32f10x_i2c.c:115
void I2C_SDAStuckAtLowTimeoutConfig(I2C_TypeDef *I2Cx, uint32_t Timeout)
Configures the specified I2C SDA stuck at low timeout.
Definition: mg32f10x_i2c.c:141
void I2C_DMARxReqLevelConfig(I2C_TypeDef *I2Cx, uint8_t Level)
Configures the DMA Rx request level.
Definition: mg32f10x_i2c.c:508
uint16_t I2C_ReadData(I2C_TypeDef *I2Cx)
Read data from Rx FIFO.
Definition: mg32f10x_i2c.c:211
void I2C_DMACmd(I2C_TypeDef *I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState)
Enables or disables the I2Cx's DMA interface.
Definition: mg32f10x_i2c.c:539
ITStatus I2C_SMBus_GetRawITStatus(I2C_TypeDef *I2Cx, uint16_t I2C_SMBUS_IT)
Checks whether the specified SMBus raw interrupt status.
Definition: mg32f10x_i2c.c:605