◆ ADDR
DMA Address Register for DMA channel x, Address offset: 0x208, 0x218, 0x228
◆ CNTL
DMA Control Register for DMA channel x, Address offset: 0x204, 0x214, 0x224
◆ COUNT
DMA Count Register for DMA channel x, Address offset: 0x20C, 0x21C, 0x22C
◆ COUNT0
Number of received bytes in Endpoint 0 FIFO, Address offset: 0x016
◆ CSR0
Control Status register for Endpoint 0, Address offset: 0x011
◆ DMAINTR
DMA Interrupt Register, Address offset: 0x200
◆ FADDR
Function address register, Address offset: 0x000
◆ FIFO
FIFOs for Endpoints 0 to 15 (must accessed by bytes), Address offset: 0x020 - 0x05F
◆ FRAMEH
Frame number bits 8 to 10, Address offset: 0x00D
◆ FRAMEL
Frame number bits 0 to 7, Address offset: 0x00C
◆ INCSR1
Control Status register 1 for IN endpoint, Address offset: 0x011
◆ INCSR2
Control Status register 2 for IN endpoint, Address offset: 0x012
◆ INDEX
Index register, Address offset: 0x00E
◆ INMAXP
Maximum packet size for IN endpoint, Address offset: 0x010
◆ INTRIN
Interrupt register for Endpoint 0 plus IN Endpoints 1 to 3, Address offset: 0x002
◆ INTRINE
Interrupt enable register for IntrIn, Address offset: 0x007
◆ INTROUT
Interrupt register for OUT Endpoints 1 to 3, Address offset: 0x004
◆ INTROUTE
Interrupt enable register for IntrOut, Address offset: 0x009
◆ INTRUSB
Interrupt register for common USB interrupts, Address offset: 0x006
◆ INTRUSBE
Interrupt enable register for IntrUSB, Address offset: 0x00B
◆ OUTCOUNTH
Number of bytes in OUT endpoint FIFO (upper byte), Address offset: 0x017
◆ OUTCOUNTL
Number of bytes in OUT endpoint FIFO (lower byte), Address offset: 0x016
◆ OUTCSR1
Control Status register 1 for OUT endpoint, Address offset: 0x014
◆ OUTCSR2
Control Status register 2 for OUT endpoint, Address offset: 0x015
◆ OUTMAXP
Maximum packet size for OUT endpoint, Address offset: 0x013
◆ POWER
Power management register, Address offset: 0x001
◆ RESERVED0
◆ RESERVED1
◆ RESERVED2
◆ RESERVED3
◆ RESERVED4
◆ RESERVED5
◆ RESERVED6
The documentation for this struct was generated from the following file: