◆ AHBENR0
RCC AHB peripheral clock enable register 0, Address offset: 0x03C
◆ AHBENR1
RCC AHB peripheral clock enable register 1, Address offset: 0x040
◆ AHBENR2
RCC AHB peripheral clock enable register 2, Address offset: 0x044
◆ AHBPRE
RCC AHB prescaler register, Address offset: 0x018
◆ AHBRSTR1
RCC AHB peripheral reset register 1, Address offset: 0x088
◆ APB1ENR
RCC APB1 peripheral clock enable register, Address offset: 0x048
◆ APB1PRE
RCC APB1 prescaler register, Address offset: 0x01C
◆ APB1RSTR
RCC APB1 peripheral reset register, Address offset: 0x090
◆ APB2ENR
RCC APB2 peripheral clock enable register, Address offset: 0x04C
◆ APB2PRE
RCC APB2 prescaler register, Address offset: 0x020
◆ APB2RSTR
RCC APB2 peripheral reset register, Address offset: 0x094
◆ BDRSTR
RCC Batt domain reset register, Address offset: 0x0D4
◆ CLRRSTSTAT
__IOM uint32_t CLRRSTSTAT |
RCC clear reset status register, Address offset: 0x0C8
◆ HSE2RTCENR
__IOM uint32_t HSE2RTCENR |
RCC HSE to RTC clock enable register, Address offset: 0x0DC
◆ I2SCLKENR
RCC I2S SCLK enable register, Address offset: 0x070
◆ I2SCLKRSTR
__IOM uint32_t I2SCLKRSTR |
RCC I2S SCLK reset register, Address offset: 0x0B8
◆ I2SPRE
RCC I2S prescaler register, Address offset: 0x028
◆ IWDGCLKENR
__IOM uint32_t IWDGCLKENR |
RCC IWDG clock enable register, Address offset: 0x064
◆ LSI2RTCENR
__IOM uint32_t LSI2RTCENR |
RCC LSI to RTC clock enable register, Address offset: 0x0D8
◆ MAINCLKSRC
__IOM uint32_t MAINCLKSRC |
RCC main clock source register, Address offset: 0x008
◆ MAINCLKUEN
__IOM uint32_t MAINCLKUEN |
RCC main clock update enable register, Address offset: 0x00C
◆ MCLKPRE
RCC MCLK prescaler register, Address offset: 0x024
◆ MCLKSRC
RCC MCLK source register, Address offset: 0x02C
◆ MCOSEL
RCC MCO select register, Address offset: 0x038
◆ PCLKENR
RCC panel PCLK clock enable register, Address offset: 0x060
◆ PLLPRE
RCC PLL prescaler register, Address offset: 0x000
◆ PLLSRC
RCC PLL source register, Address offset: 0x004
◆ RESERVED0
◆ RESERVED1
◆ RESERVED10
◆ RESERVED2
◆ RESERVED4
◆ RESERVED5
◆ RESERVED6
◆ RESERVED7
◆ RESERVED8
◆ RESERVED9
◆ RNGCLKENR
RCC RNG clock enable register, Address offset: 0x05C
◆ RSTSTAT
RCC reset status register, Address offset: 0x100
◆ SPIS1CLKENR
__IOM uint32_t SPIS1CLKENR |
RCC SPIS1 clock enable register, Address offset: 0x074
◆ SPIS2CLKENR
__IOM uint32_t SPIS2CLKENR |
RCC SPIS2 clock enable register, Address offset: 0x078
◆ USBCLKENR
RCC USB clock enable register, Address offset: 0x06C
◆ USBFIFOCLKENR
__IOM uint32_t USBFIFOCLKENR |
RCC USB FIFO clock enable register, Address offset: 0x07C
◆ USBFIFOCLKSRC
__IOM uint32_t USBFIFOCLKSRC |
RCC USB FIFO clock source register, Address offset: 0x034
◆ USBPRE
RCC USB prescaler register, Address offset: 0x014
The documentation for this struct was generated from the following file: