◆ BAUDR
Baud Rate Select, Address offset: 0x014
◆ CR0
Control Register 0, Address offset: 0x000
◆ CR1
Control Register 1, Address offset: 0x004
◆ DMACR
DMA Control Register, Address offset: 0x04C
◆ DMARDLR
DMA Receive Data Level, Address offset: 0x054
◆ DMATDLR
DMA Transmit Data Level, Address offset: 0x050
◆ DR
Data Register, Address offset: 0x060
◆ ESPICR
Enhanced SPI Control Register, Address offset: 0x0F4
◆ ICR
Interrupt Clear Register, Address offset: 0x048
◆ IER
Interrupt Enable Register, Address offset: 0x02C
◆ ISR
Interrupt Status Register, Address offset: 0x030
◆ MSTICR
Multi-Master Interrupt Clear Register, Address offset: 0x044
◆ MWCR
Microwire Control Register, Address offset: 0x00C
◆ RESERVED0
◆ RESERVED1
◆ RISR
Raw Interrupt Status Register, Address offset: 0x034
◆ RX_SAMPLE_DLY
__IOM uint32_t RX_SAMPLE_DLY |
RX Sample Delay Register, Address offset: 0x0F0
◆ RXFLR
Receive FIFO Level Register, Address offset: 0x024
◆ RXFTLR
Receive FIFO Threshold Level, Address offset: 0x01C
◆ RXOICR
Receive FIFO Overflow Interrupt Clear Register, Address offset: 0x03C
◆ RXUICR
Receive FIFO Underflow Interrupt Clear Register, Address offset: 0x040
◆ SER
Slave Enable Register, Address offset: 0x010
◆ SPIENR
SPI Enable Register, Address offset: 0x008
◆ SR
Status Register, Address offset: 0x028
◆ TXFLR
Transmit FIFO Level Register, Address offset: 0x020
◆ TXFTLR
Transmit FIFO Threshold Level, Address offset: 0x018
◆ TXOICR
Transmit FIFO Overflow Interrupt Clear Register, Address offset: 0x038
The documentation for this struct was generated from the following file: