MG32F10x Standard Peripherals Firmware Library
Data Fields
I2S_TypeDef Struct Reference

Data Fields

__IOM uint32_t IER
 
__IOM uint32_t IRER
 
__IOM uint32_t ITER
 
__IOM uint32_t CER
 
__IOM uint32_t CCR
 
__OM uint32_t RXFFR
 
__OM uint32_t TXFFR
 
uint32_t RESERVED0
 
struct {
   union {
      __IM uint32_t   LRBR
 
      __OM uint32_t   LTHR
 
   } 
 
   union {
      __IM uint32_t   RRBR
 
      __OM uint32_t   RTHR
 
   } 
 
   __IOM uint32_t   RER
 
   __IOM uint32_t   TER
 
   __IOM uint32_t   RCR
 
   __IOM uint32_t   TCR
 
   __IM uint32_t   ISR
 
   __IOM uint32_t   IMR
 
   __IM uint32_t   ROR
 
   __IM uint32_t   TOR
 
   __IOM uint32_t   RFCR
 
   __IOM uint32_t   TFCR
 
   __OM uint32_t   RFF
 
   __OM uint32_t   TFF
 
   uint32_t   RESERVED0
 
   uint32_t   RESERVED1
 
Ch [2]
 
__IM uint32_t RXDMA
 
__OM uint32_t RRXDMA
 
__OM uint32_t TXDMA
 
__OM uint32_t RTXDMA
 

Field Documentation

◆ CCR

__IOM uint32_t CCR

Clock Configuration Register, Address offset: 0x010

◆ CER

__IOM uint32_t CER

Clock Enable Register, Address offset: 0x00C

◆ IER

__IOM uint32_t IER

I2S Enable Register, Address offset: 0x000

◆ IMR

__IOM uint32_t IMR

Interrupt Mask Register, Address offset: 0x03C, 0x07C

◆ IRER

__IOM uint32_t IRER

I2S Receiver Block Enable Register, Address offset: 0x004

◆ ISR

__IM uint32_t ISR

Interrupt Status Register, Address offset: 0x038, 0x078

◆ ITER

__IOM uint32_t ITER

I2S Transmitter Block Enable Register, Address offset: 0x008

◆ LRBR

__IM uint32_t LRBR

Left Receive Buffer Register, Address offset: 0x020, 0x060

◆ LTHR

__OM uint32_t LTHR

Left Transmit Holding Register, Address offset: 0x020, 0x060

◆ RCR

__IOM uint32_t RCR

Receive Configuration Register, Address offset: 0x030, 0x070

◆ RER

__IOM uint32_t RER

Receive Enable Register, Address offset: 0x028, 0x068

◆ RESERVED0

uint32_t RESERVED0

Reserved, 0x01C

◆ RESERVED1

uint32_t RESERVED1

Reserved, 0x0A0 - 0x1BC

◆ RFCR

__IOM uint32_t RFCR

Receive FIFO Configuration Register, Address offset: 0x048, 0x088

◆ RFF

__OM uint32_t RFF

Receive FIFO Flush Register, Address offset: 0x050, 0x090

◆ ROR

__IM uint32_t ROR

Receive Overrun Register, Address offset: 0x040, 0x080

◆ RRBR

__IM uint32_t RRBR

Right Receive Buffer Register, Address offset: 0x024, 0x064

◆ RRXDMA

__OM uint32_t RRXDMA

Reset Receiver Block DMA Register, Address offset: 0x1C4

◆ RTHR

__OM uint32_t RTHR

Right Transmit Holding Register, Address offset: 0x024, 0x064

◆ RTXDMA

__OM uint32_t RTXDMA

Reset Transmitter Block DMA Register, Address offset: 0x1CC

◆ RXDMA

__IM uint32_t RXDMA

Receiver Block DMA Register, Address offset: 0x1C0

◆ RXFFR

__OM uint32_t RXFFR

Receiver Block FIFO Reset Register, Address offset: 0x014

◆ TCR

__IOM uint32_t TCR

Transmit Configuration Register, Address offset: 0x034, 0x074

◆ TER

__IOM uint32_t TER

Transmit Enable Register, Address offset: 0x02C, 0x06C

◆ TFCR

__IOM uint32_t TFCR

Transmit FIFO Configuration Register, Address offset: 0x04C, 0x08C

◆ TFF

__OM uint32_t TFF

Transmit FIFO Flush Register, Address offset: 0x054, 0x094

◆ TOR

__IM uint32_t TOR

Transmit Overrun Register, Address offset: 0x044, 0x084

◆ TXDMA

__OM uint32_t TXDMA

Transmitter Block DMA Register, Address offset: 0x1C8

◆ TXFFR

__OM uint32_t TXFFR

Transmitter Block FIFO Reset Register, Address offset: 0x018


The documentation for this struct was generated from the following file: