◆ ACK_GENERAL_CALL
__IOM uint32_t ACK_GENERAL_CALL |
I2C ACK General Call Register, Address offset: 0x098
◆ CLR_ACTIVITY
__IM uint32_t CLR_ACTIVITY |
Clear ACTIVITY Interrupt Register, Address offset: 0x05C
◆ CLR_GEN_CALL
__IM uint32_t CLR_GEN_CALL |
Clear GEN_CALL Interrupt Register, Address offset: 0x068
◆ CLR_INTR
Clear Combined and Individual Interrupt Register, Address offset: 0x040
◆ CLR_RD_REQ
Clear RD_REQ Interrupt Register, Address offset: 0x050
◆ CLR_RESTART_DET
__IM uint32_t CLR_RESTART_DET |
Clear RESTART_DET Interrupt Register, Address offset: 0x0A8
◆ CLR_RX_DONE
__IM uint32_t CLR_RX_DONE |
Clear RX_DONE Interrupt Register, Address offset: 0x058
◆ CLR_RX_OVER
__IM uint32_t CLR_RX_OVER |
Clear RX_OVER Interrupt Register, Address offset: 0x048
◆ CLR_RX_UNDER
__IM uint32_t CLR_RX_UNDER |
Clear RX_UNDER Interrupt Register, Address offset: 0x044
◆ CLR_SCL_STUCK_DET
__IM uint32_t CLR_SCL_STUCK_DET |
Clear SCL Stuck at Low Detect Interrupt Register, Address offset: 0x0B4
◆ CLR_SMBUS_INTR
__OM uint32_t CLR_SMBUS_INTR |
SMBus Clear Interrupt Register, Address offset: 0x0D4
◆ CLR_START_DET
__IM uint32_t CLR_START_DET |
Clear START_DET Interrupt Register, Address offset: 0x064
◆ CLR_STOP_DET
__IM uint32_t CLR_STOP_DET |
Clear STOP_DET Interrupt Register, Address offset: 0x060
◆ CLR_TX_ABRT
__IM uint32_t CLR_TX_ABRT |
Clear TX_ABRT Interrupt Register, Address offset: 0x054
◆ CLR_TX_OVER
__IM uint32_t CLR_TX_OVER |
Clear TX_OVER Interrupt Register, Address offset: 0x04C
◆ CON
I2C Control Register, Address offset: 0x000
◆ DATA_CMD
I2C Rx/Tx Data Buffer and Command Register, Address offset: 0x010
◆ DMA_CR
DMA Control Register, Address offset: 0x088
◆ DMA_RDLR
DMA Receive Data Level Register, Address offset: 0x090
◆ DMA_TDLR
DMA Transmit Data Level Register, Address offset: 0x08C
◆ ENABLE
I2C Enable Register, Address offset: 0x06C
◆ ENABLE_STATUS
__IM uint32_t ENABLE_STATUS |
I2C Enable Status Register, Address offset: 0x09C
◆ FS_SCL_HCNT
__IOM uint32_t FS_SCL_HCNT |
Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register, Address offset: 0x01C
◆ FS_SCL_LCNT
__IOM uint32_t FS_SCL_LCNT |
Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register, Address offset: 0x020
◆ FS_SPKLEN
I2C SS, FS or FM+ spike suppression limit, Address offset: 0x0A0
◆ HS_MADDR
I2C High Speed Master Mode Code Address Register, Address offset: 0x00C
◆ HS_SCL_HCNT
__IOM uint32_t HS_SCL_HCNT |
High Speed I2C Clock SCL High Count Register, Address offset: 0x024
◆ HS_SCL_LCNT
__IOM uint32_t HS_SCL_LCNT |
High Speed I2C Clock SCL Low Count Register, Address offset: 0x028
◆ HS_SPKLEN
I2C HS spike suppression limit, Address offset: 0x0A4
◆ INTR_MASK
I2C Interrupt Mask Register, Address offset: 0x030
◆ INTR_STAT
I2C Interrupt Status Register, Address offset: 0x02C
◆ OPTIONAL_SAR
__IOM uint32_t OPTIONAL_SAR |
I2C Optional Slave Address Register, Address offset: 0x0D8
◆ RAW_INTR_STAT
__IM uint32_t RAW_INTR_STAT |
I2C Raw Interrupt Status Register, Address offset: 0x034
◆ RESERVED0
◆ RX_TL
I2C Receive FIFO Threshold Register, Address offset: 0x038
◆ RXFLR
I2C Receive FIFO Level Register, Address offset: 0x078
◆ SAR
I2C Slave Address Register, Address offset: 0x008
◆ SCL_STUCK_AT_LOW_TIMEOUT
__IOM uint32_t SCL_STUCK_AT_LOW_TIMEOUT |
I2C SCL Stuck at Low Timeout, Address offset: 0x0AC
◆ SDA_HOLD
I2C SDA Hold Time Length Register, Address offset: 0x07C
◆ SDA_SETUP
I2C SDA Setup Register, Address offset: 0x094
◆ SDA_STUCK_AT_LOW_TIMEOUT
__IOM uint32_t SDA_STUCK_AT_LOW_TIMEOUT |
I2C SDA Stuck at Low Timeout, Address offset: 0x0B0
◆ SLV_DATA_NACK_ONLY
__IOM uint32_t SLV_DATA_NACK_ONLY |
Generate Slave Data NACK Register, Address offset: 0x084
◆ SMBUS_CLK_LOW_MEXT
__IOM uint32_t SMBUS_CLK_LOW_MEXT |
SMBus Master Clock Extend Timeout Register, Address offset: 0x0C0
◆ SMBUS_CLK_LOW_SEXT
__IOM uint32_t SMBUS_CLK_LOW_SEXT |
SMBus Slave Clock Extend Timeout Register, Address offset: 0x0BC
◆ SMBUS_INTR_MASK
__IOM uint32_t SMBUS_INTR_MASK |
SMBus Interrupt Mask Register, Address offset: 0x0CC
◆ SMBUS_INTR_STAT
__IM uint32_t SMBUS_INTR_STAT |
SMBUS Interrupt Status Register, Address offset: 0x0C8
◆ SMBUS_RAW_INTR_STAT
__IM uint32_t SMBUS_RAW_INTR_STAT |
SMBus Raw Interrupt Status Register, Address offset: 0x0D0
◆ SMBUS_THIGH_MAX_IDLE_COUNT
__IOM uint32_t SMBUS_THIGH_MAX_IDLE_COUNT |
SMBus Master THigh MAX Bus-idle count Register, Address offset: 0x0C4
◆ SMBUS_UDID_LSB
__IOM uint32_t SMBUS_UDID_LSB |
SMBUS ARP UDID LSB Register, Address offset: 0x0DC
◆ SS_SCL_HCNT
__IOM uint32_t SS_SCL_HCNT |
Standard Speed I2C Clock SCL High Count Register, Address offset: 0x014
◆ SS_SCL_LCNT
__IOM uint32_t SS_SCL_LCNT |
Standard Speed I2C Clock SCL Low Count Register, Address offset: 0x018
◆ STATUS
I2C Status Register, Address offset: 0x070
◆ TAR
I2C Target Address Register, Address offset: 0x004
◆ TX_ABRT_SOURCE
__IM uint32_t TX_ABRT_SOURCE |
I2C Transmit Abort Source Register, Address offset: 0x080
◆ TX_TL
I2C Transmit FIFO Threshold Register, Address offset: 0x03C
◆ TXFLR
I2C Transmit FIFO Level Register, Address offset: 0x074
The documentation for this struct was generated from the following file: