MG32F10x Standard Peripherals Firmware Library
|
*************** (C) COPYRIGHT 2020 - 2023 megawin Technology *************** * @file I2C/I2C_MasterDMARx_SlaveDMATx/readme.txt * @author megawin Application Team * @version V0.1.10 * @date 05-January-2023 * @brief Description of the I2C I2C_MasterDMARx_SlaveDMATx example. ****************************************************************************** * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, MEGAWIN SHALL NOT BE HELD LIABLE FOR ANY DIRECT, * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM * THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. ******************************************************************************
This example describes The I2C Master receives data using DMA and The I2C slave transmits data using DMA.
In this example, Main clock is from PLL clock and it is configured at 96MHz. The PLL clock is based on 8MHz HSE. APB1 and APB2 clock is from Main clock.
In this example, I2C1 as slave and I2C2 as Master,I2C1 and I2C2 need to be connected;
DMAC2 Channel 0 is used as I2C1 slave to transmits data;
DMAC2 Channel 1 is used as I2C2 Master to transmits data;
DMAC2 Channel 2 is used as I2C2 Master to receives data;
At the end of the data transfer, a data consistency check will be performed in master and slave sides, and print out the check result through UART1.
In order to make the program work, you must do the following :
Run the example