MG32F10x Standard Peripherals Firmware Library
Data Fields
TIM_TypeDef Struct Reference

Data Fields

__IOM uint32_t CR1
 
__IOM uint32_t CR2
 
__IOM uint32_t SMCR
 
__IOM uint32_t DIER
 
__IOM uint32_t SR
 
__OM uint32_t EGR
 
__IOM uint32_t CCMR1
 
__IOM uint32_t CCMR2
 
__IOM uint32_t CCER
 
__IOM uint32_t CNT
 
__IOM uint32_t PSC
 
__IOM uint32_t ARR
 
__IOM uint32_t RCR
 
__IOM uint32_t CCR1
 
__IOM uint32_t CCR2
 
__IOM uint32_t CCR3
 
__IOM uint32_t CCR4
 
__IOM uint32_t BDTR
 

Field Documentation

◆ ARR

__IOM uint32_t ARR

Auto-reload register, Address offset: 0x02C

◆ BDTR

__IOM uint32_t BDTR

Break and dead-time register, Address offset: 0x044

◆ CCER

__IOM uint32_t CCER

Capture/compare enable register, Address offset: 0x020

◆ CCMR1

__IOM uint32_t CCMR1

Capture/compare mode register 1, Address offset: 0x018

◆ CCMR2

__IOM uint32_t CCMR2

Capture/compare mode register 2, Address offset: 0x01C

◆ CCR1

__IOM uint32_t CCR1

Capture/compare register 1, Address offset: 0x034

◆ CCR2

__IOM uint32_t CCR2

Capture/compare register 2, Address offset: 0x038

◆ CCR3

__IOM uint32_t CCR3

Capture/compare register 3, Address offset: 0x03C

◆ CCR4

__IOM uint32_t CCR4

Capture/compare register 4, Address offset: 0x040

◆ CNT

__IOM uint32_t CNT

Counter, Address offset: 0x024

◆ CR1

__IOM uint32_t CR1

Control register 1, Address offset: 0x000

◆ CR2

__IOM uint32_t CR2

Control register 2, Address offset: 0x004

◆ DIER

__IOM uint32_t DIER

DMA/interrupt enable register, Address offset: 0x00C

◆ EGR

__OM uint32_t EGR

Event generation register, Address offset: 0x014

◆ PSC

__IOM uint32_t PSC

Prescaler, Address offset: 0x028

◆ RCR

__IOM uint32_t RCR

Repetition counter register, Address offset: 0x030

◆ SMCR

__IOM uint32_t SMCR

Slave mode control register, Address offset: 0x008

◆ SR

__IOM uint32_t SR

Status register, Address offset: 0x010


The documentation for this struct was generated from the following file: