MG32F10x Standard Peripherals Firmware Library
Data Fields
UART_TypeDef Struct Reference

Data Fields

union {
   __IM uint32_t   RBR
 
   __OM uint32_t   THR
 
   __IOM uint32_t   DLL
 
}; 
 
union {
   __IOM uint32_t   DLH
 
   __IOM uint32_t   IER
 
}; 
 
union {
   __IM uint32_t   IIR
 
   __OM uint32_t   FCR
 
}; 
 
__IOM uint32_t LCR
 
__IOM uint32_t MCR
 
__IM uint32_t LSR
 
__IM uint32_t MSR
 
__IOM uint32_t SCR
 
uint32_t RESERVED0 [23]
 
__IM uint32_t USR
 
__IM uint32_t TFL
 
__IM uint32_t RFL
 
__OM uint32_t SRR
 
__IOM uint32_t SRTS
 
__IOM uint32_t SBCR
 
uint32_t RESERVED1
 
__IOM uint32_t SFE
 
__IOM uint32_t SRT
 
__IOM uint32_t STET
 
__IOM uint32_t HTX
 
__OM uint32_t DMASA
 
uint32_t RESERVED2 [5]
 
__IOM uint32_t DLF
 
__IOM uint32_t RAR
 
__IOM uint32_t TAR
 
__IOM uint32_t EXTLCR
 

Field Documentation

◆ DLF

__IOM uint32_t DLF

Divisor Latch Fractional Value, Address offset: 0x0C0

◆ DLH

__IOM uint32_t DLH

Divisor Latch(High), Address offset: 0x004

◆ DLL

__IOM uint32_t DLL

Divisor Latch(Low), Address offset: 0x000

◆ DMASA

__OM uint32_t DMASA

DMA Software Acknowledge, Address offset: 0x0A8

◆ EXTLCR

__IOM uint32_t EXTLCR

Line Extended Control Register, Address offset: 0x0CC

◆ FCR

__OM uint32_t FCR

FIFO Control Register, Address offset: 0x008

◆ HTX

__IOM uint32_t HTX

Halt TX, Address offset: 0x0A4

◆ IER

__IOM uint32_t IER

Interrupt Enable Register, Address offset: 0x004

◆ IIR

__IM uint32_t IIR

Interrupt Identification Register, Address offset: 0x008

◆ LCR

__IOM uint32_t LCR

Line Control Register, Address offset: 0x00C

◆ LSR

__IM uint32_t LSR

Line Status Register, Address offset: 0x014

◆ MCR

__IOM uint32_t MCR

Modem Control Register, Address offset: 0x010

◆ MSR

__IM uint32_t MSR

Modem Status Register, Address offset: 0x018

◆ RAR

__IOM uint32_t RAR

Receive Address Register, Address offset: 0x0C4

◆ RBR

__IM uint32_t RBR

Receive Buffer Register, Address offset: 0x000

◆ RESERVED0

uint32_t RESERVED0[23]

Reserved, 0x020 - 0x078

◆ RESERVED1

uint32_t RESERVED1

Reserved, 0x094

◆ RESERVED2

uint32_t RESERVED2[5]

Reserved, 0x0AC - 0x0BC

◆ RFL

__IM uint32_t RFL

Receive FIFO Level, Address offset: 0x084

◆ SBCR

__IOM uint32_t SBCR

Shadow Break Control Register, Address offset: 0x090

◆ SCR

__IOM uint32_t SCR

Scratchpad Register, Address offset: 0x01C

◆ SFE

__IOM uint32_t SFE

Shadow FIFO Enable, Address offset: 0x098

◆ SRR

__OM uint32_t SRR

Software Reset Register, Address offset: 0x088

◆ SRT

__IOM uint32_t SRT

Shadow RCVR Trigger, Address offset: 0x09C

◆ SRTS

__IOM uint32_t SRTS

Shadow Request to Send, Address offset: 0x08C

◆ STET

__IOM uint32_t STET

Shadow TX Empty Trigger, Address offset: 0x0A0

◆ TAR

__IOM uint32_t TAR

Transmit Address Register, Address offset: 0x0C8

◆ TFL

__IM uint32_t TFL

Transmit FIFO Level, Address offset: 0x080

◆ THR

__OM uint32_t THR

Transmit Holding Register, Address offset: 0x000

◆ USR

__IM uint32_t USR

UART Status Register, Address offset: 0x07C


The documentation for this struct was generated from the following file: