MG32F10x Standard Peripherals Firmware Library
Data Fields

Structure type to access the Trace Port Interface Register (TPI). More...

#include <core_cm3.h>

Data Fields

__IM uint32_t SSPSR
 
__IOM uint32_t CSPSR
 
uint32_t RESERVED0 [2U]
 
__IOM uint32_t ACPR
 
uint32_t RESERVED1 [55U]
 
__IOM uint32_t SPPR
 
uint32_t RESERVED2 [131U]
 
__IM uint32_t FFSR
 
__IOM uint32_t FFCR
 
__IM uint32_t FSCR
 
uint32_t RESERVED3 [759U]
 
__IM uint32_t TRIGGER
 
__IM uint32_t FIFO0
 
__IM uint32_t ITATBCTR2
 
uint32_t RESERVED4 [1U]
 
__IM uint32_t ITATBCTR0
 
__IM uint32_t FIFO1
 
__IOM uint32_t ITCTRL
 
uint32_t RESERVED5 [39U]
 
__IOM uint32_t CLAIMSET
 
__IOM uint32_t CLAIMCLR
 
uint32_t RESERVED7 [8U]
 
__IM uint32_t DEVID
 
__IM uint32_t DEVTYPE
 

Detailed Description

Structure type to access the Trace Port Interface Register (TPI).

Field Documentation

◆ ACPR

__IOM uint32_t ACPR

Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register

◆ CLAIMCLR

__IOM uint32_t CLAIMCLR

Offset: 0xFA4 (R/W) Claim tag clear

◆ CLAIMSET

__IOM uint32_t CLAIMSET

Offset: 0xFA0 (R/W) Claim tag set

◆ CSPSR

__IOM uint32_t CSPSR

Offset: 0x004 (R/W) Current Parallel Port Size Register

◆ DEVID

__IM uint32_t DEVID

Offset: 0xFC8 (R/ ) TPIU_DEVID

◆ DEVTYPE

__IM uint32_t DEVTYPE

Offset: 0xFCC (R/ ) TPIU_DEVTYPE

◆ FFCR

__IOM uint32_t FFCR

Offset: 0x304 (R/W) Formatter and Flush Control Register

◆ FFSR

__IM uint32_t FFSR

Offset: 0x300 (R/ ) Formatter and Flush Status Register

◆ FIFO0

__IM uint32_t FIFO0

Offset: 0xEEC (R/ ) Integration ETM Data

◆ FIFO1

__IM uint32_t FIFO1

Offset: 0xEFC (R/ ) Integration ITM Data

◆ FSCR

__IM uint32_t FSCR

Offset: 0x308 (R/ ) Formatter Synchronization Counter Register

◆ ITATBCTR0

__IM uint32_t ITATBCTR0

Offset: 0xEF8 (R/ ) ITATBCTR0

◆ ITATBCTR2

__IM uint32_t ITATBCTR2

Offset: 0xEF0 (R/ ) ITATBCTR2

◆ ITCTRL

__IOM uint32_t ITCTRL

Offset: 0xF00 (R/W) Integration Mode Control

◆ SPPR

__IOM uint32_t SPPR

Offset: 0x0F0 (R/W) Selected Pin Protocol Register

◆ SSPSR

__IM uint32_t SSPSR

Offset: 0x000 (R/ ) Supported Parallel Port Size Register

◆ TRIGGER

__IM uint32_t TRIGGER

Offset: 0xEE8 (R/ ) TRIGGER Register


The documentation for this struct was generated from the following file: