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union { |
__IM uint32_t RBR |
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__OM uint32_t THR |
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__IOM uint32_t DLL |
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}; | |
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union { |
__IOM uint32_t DLH |
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__IOM uint32_t IER |
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}; | |
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union { |
__IM uint32_t IIR |
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__OM uint32_t FCR |
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}; | |
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__IOM uint32_t | LCR |
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__IOM uint32_t | MCR |
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__IM uint32_t | LSR |
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__IM uint32_t | MSR |
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__IOM uint32_t | SCR |
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uint32_t | RESERVED0 [23] |
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__IM uint32_t | USR |
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__IM uint32_t | TFL |
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__IM uint32_t | RFL |
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__OM uint32_t | SRR |
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__IOM uint32_t | SRTS |
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__IOM uint32_t | SBCR |
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uint32_t | RESERVED1 |
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__IOM uint32_t | SFE |
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__IOM uint32_t | SRT |
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__IOM uint32_t | STET |
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__IOM uint32_t | HTX |
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__OM uint32_t | DMASA |
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uint32_t | RESERVED2 [5] |
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__IOM uint32_t | DLF |
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__IOM uint32_t | RAR |
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__IOM uint32_t | TAR |
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__IOM uint32_t | EXTLCR |
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◆ DLF
Divisor Latch Fractional Value, Address offset: 0x0C0
◆ DLH
Divisor Latch(High), Address offset: 0x004
◆ DLL
Divisor Latch(Low), Address offset: 0x000
◆ DMASA
DMA Software Acknowledge, Address offset: 0x0A8
◆ EXTLCR
Line Extended Control Register, Address offset: 0x0CC
◆ FCR
FIFO Control Register, Address offset: 0x008
◆ HTX
Halt TX, Address offset: 0x0A4
◆ IER
Interrupt Enable Register, Address offset: 0x004
◆ IIR
Interrupt Identification Register, Address offset: 0x008
◆ LCR
Line Control Register, Address offset: 0x00C
◆ LSR
Line Status Register, Address offset: 0x014
◆ MCR
Modem Control Register, Address offset: 0x010
◆ MSR
Modem Status Register, Address offset: 0x018
◆ RAR
Receive Address Register, Address offset: 0x0C4
◆ RBR
Receive Buffer Register, Address offset: 0x000
◆ RESERVED0
◆ RESERVED1
◆ RESERVED2
◆ RFL
Receive FIFO Level, Address offset: 0x084
◆ SBCR
Shadow Break Control Register, Address offset: 0x090
◆ SCR
Scratchpad Register, Address offset: 0x01C
◆ SFE
Shadow FIFO Enable, Address offset: 0x098
◆ SRR
Software Reset Register, Address offset: 0x088
◆ SRT
Shadow RCVR Trigger, Address offset: 0x09C
◆ SRTS
Shadow Request to Send, Address offset: 0x08C
◆ STET
Shadow TX Empty Trigger, Address offset: 0x0A0
◆ TAR
Transmit Address Register, Address offset: 0x0C8
◆ TFL
Transmit FIFO Level, Address offset: 0x080
◆ THR
Transmit Holding Register, Address offset: 0x000
◆ USR
UART Status Register, Address offset: 0x07C
The documentation for this struct was generated from the following file: