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struct { |
__IOM uint32_t SAR |
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uint32_t Undefined_SAR |
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__IOM uint32_t DAR |
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uint32_t Undefined_DAR |
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uint32_t RESERVED0 [2] |
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__IOM uint32_t CTLL |
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__IOM uint32_t CTLH |
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uint32_t RESERVED1 [8] |
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__IOM uint32_t CFGL |
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__IOM uint32_t CFGH |
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__IOM uint32_t SGR |
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uint32_t Undefined_SGR |
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__IOM uint32_t DSR |
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uint32_t Undefined_DSR |
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} | Ch [3] |
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uint32_t | RESERVED2 [110] |
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__IM uint32_t | RawTfr |
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uint32_t | Undefined_RawTfr |
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__IM uint32_t | RawBlock |
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uint32_t | Undefined_RawBlock |
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__IM uint32_t | RawSrcTran |
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uint32_t | Undefined_RawSrcTran |
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__IM uint32_t | RawDstTran |
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uint32_t | Undefined_RawDstTran |
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__IM uint32_t | RawErr |
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uint32_t | Undefined_RawErr |
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__IM uint32_t | StatusTfr |
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uint32_t | Undefined_StatusTfr |
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__IM uint32_t | StatusBlock |
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uint32_t | Undefined_StatusBlock |
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__IM uint32_t | StatusSrcTran |
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uint32_t | Undefined_StatusSrcTran |
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__IM uint32_t | StatusDstTran |
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uint32_t | Undefined_StatusDstTran |
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__IM uint32_t | StatusErr |
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uint32_t | Undefined_StatusErr |
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__IOM uint32_t | MaskTfr |
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uint32_t | Undefined_MaskTfr |
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__IOM uint32_t | MaskBlock |
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uint32_t | Undefined_MaskBlock |
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__IOM uint32_t | MaskSrcTran |
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uint32_t | Undefined_MaskSrcTran |
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__IOM uint32_t | MaskDstTran |
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uint32_t | Undefined_MaskDstTran |
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__IOM uint32_t | MaskErr |
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uint32_t | Undefined_MaskErr |
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__OM uint32_t | ClearTfr |
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uint32_t | Undefined_ClearTfr |
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__OM uint32_t | ClearBlock |
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uint32_t | Undefined_ClearBlock |
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__OM uint32_t | ClearSrcTran |
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uint32_t | Undefined_ClearSrcTran |
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__OM uint32_t | ClearDstTran |
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uint32_t | Undefined_ClearDstTran |
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__OM uint32_t | ClearErr |
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uint32_t | Undefined_ClearErr |
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__IM uint32_t | StatusInt |
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uint32_t | Undefined_StatusInt |
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__IOM uint32_t | ReqSrcReg |
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uint32_t | Undefined_ReqSrcReg |
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__IOM uint32_t | ReqDstReg |
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uint32_t | Undefined_ReqDstReg |
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__IOM uint32_t | SglReqSrcReg |
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uint32_t | Undefined_SglReqSrcReg |
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__IOM uint32_t | SglReqDstReg |
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uint32_t | Undefined_SglReqDstReg |
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__IOM uint32_t | LstSrcReg |
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uint32_t | Undefined_LstSrcReg |
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__IOM uint32_t | LstDstReg |
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uint32_t | Undefined_LstDstReg |
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__IOM uint32_t | DmaCfgReg |
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uint32_t | Undefined_DmaCfgReg |
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__IOM uint32_t | ChEnReg |
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uint32_t | Undefined_ChEnReg |
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◆ CFGH
Channel x Configuration High Register, Address offset: 0x044, 0x09C, 0x0F4
◆ CFGL
Channel x Configuration Low Register, Address offset: 0x040, 0x098, 0x0F0
◆ ChEnReg
DMA Channel Enable Register, Address offset: 0x3A0
◆ ClearBlock
Clear for IntBlock Interrupt, Address offset: 0x340
◆ ClearDstTran
__OM uint32_t ClearDstTran |
Clear for IntDstTran Interrupt, Address offset: 0x350
◆ ClearErr
Clear for IntErr Interrupt, Address offset: 0x358
◆ ClearSrcTran
__OM uint32_t ClearSrcTran |
Clear for IntSrcTran Interrupt, Address offset: 0x348
◆ ClearTfr
Clear for IntTfr Interrupt, Address offset: 0x338
◆ CTLH
Channel x Control High Register, Address offset: 0x01C, 0x074, 0x0CC
◆ CTLL
Channel x Control Low Register, Address offset: 0x018, 0x070, 0x0C8
◆ DAR
Channel x Destination Address Register, Address offset: 0x008, 0x060, 0x0B8
◆ DmaCfgReg
DMA Configuration Register, Address offset: 0x398
◆ DSR
Channel x Destination Scatter Register, Address offset: 0x050, 0x0A8, 0x100
◆ LstDstReg
Last Destination Transaction Request Register, Address offset: 0x390
◆ LstSrcReg
Last Source Transaction Request Register, Address offset: 0x388
◆ MaskBlock
Mask for IntBlock Interrupt, Address offset: 0x318
◆ MaskDstTran
__IOM uint32_t MaskDstTran |
Mask for IntDstTran Interrupt, Address offset: 0x328
◆ MaskErr
Mask for IntErr Interrupt, Address offset: 0x330
◆ MaskSrcTran
__IOM uint32_t MaskSrcTran |
Mask for IntSrcTran Interrupt, Address offset: 0x320
◆ MaskTfr
Mask for IntTfr Interrupt, Address offset: 0x310
◆ RawBlock
Raw Status for IntBlock Interrupt, Address offset: 0x2C8
◆ RawDstTran
Raw Status for IntDstTran Interrupt, Address offset: 0x2D8
◆ RawErr
Raw Status for IntErr Interrupt, Address offset: 0x2E0
◆ RawSrcTran
Raw Status for IntSrcTran Interrupt, Address offset: 0x2D0
◆ RawTfr
Raw Status for IntTfr Interrupt, Address offset: 0x2C0
◆ ReqDstReg
Destination Software Transaction Request Register, Address offset: 0x370
◆ ReqSrcReg
Source Software Transaction Request Register, Address offset: 0x368
◆ RESERVED0
◆ RESERVED1
◆ RESERVED2
◆ SAR
Channel x Source Address Register, Address offset: 0x000, 0x058, 0x0B0
◆ SglReqDstReg
__IOM uint32_t SglReqDstReg |
Single Destination Transaction Request Register, Address offset: 0x380
◆ SglReqSrcReg
__IOM uint32_t SglReqSrcReg |
Single Source Transaction Request Register, Address offset: 0x378
◆ SGR
Channel x Source Gather Register, Address offset: 0x048, 0x0A0, 0x0F8
◆ StatusBlock
__IM uint32_t StatusBlock |
Status for IntBlock Interrupt, Address offset: 0x2F0
◆ StatusDstTran
__IM uint32_t StatusDstTran |
Status for IntDstTran Interrupt, Address offset: 0x300
◆ StatusErr
Status for IntErr Interrupt, Address offset: 0x308
◆ StatusInt
Status for each interrupt type, Address offset: 0x360
◆ StatusSrcTran
__IM uint32_t StatusSrcTran |
Status for IntSrcTran Interrupt, Address offset: 0x2F8
◆ StatusTfr
Status for IntTfr Interrupt, Address offset: 0x2E8
The documentation for this struct was generated from the following file: