MG32F10x Standard Peripherals Firmware Library
mg32f10x.h
1 /******************************************************************************
2  * @file mg32f10x.h
3  * @brief CMSIS Core Peripheral Access Layer Header File for
4  * mg32f10x Device Series
5  * @version V0.1.10
6  * @date 05-January-2023
7  * @attention
8  *
9  * Copyright (c) 2020 - 2023 megawin Technology (Shenzhen) Corp., Ltd
10  * All rights reserved.
11  *
12  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14  * TIME. AS A RESULT, MEGAWIN TECHNOLOGY SHALL NOT BE HELD LIABLE FOR ANY
15  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18  *
19  ******************************************************************************/
20 
29 #ifndef __MG32F10x_H__
30 #define __MG32F10x_H__
31 
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35 
40 #if !defined USE_STDPERIPH_DRIVER
41 
46  /*#define USE_STDPERIPH_DRIVER*/
47 #endif
48 
49 
57 #if !defined HSE_VALUE
58  #define HSE_VALUE (8000000)
59 #endif /* HSE_VALUE */
60 
61 
66 #define HSE_STARTUP_TIMEOUT (48000)
72 #define __MG32F10x_STDPERIPH_VERSION_MAIN (0x00)
73 #define __MG32F10x_STDPERIPH_VERSION_SUB1 (0x01)
74 #define __MG32F10x_STDPERIPH_VERSION_SUB2 (0x0A)
75 #define __MG32F10x_STDPERIPH_VERSION_RC (0x00)
76 #define __MG32F10x_STDPERIPH_VERSION ( (__MG32F10x_STDPERIPH_VERSION_MAIN << 24)\
77  |(__MG32F10x_STDPERIPH_VERSION_SUB1 << 16)\
78  |(__MG32F10x_STDPERIPH_VERSION_SUB2 << 8)\
79  |(__MG32F10x_STDPERIPH_VERSION_RC))
80 
85 #define MHSI_VALUE (8000000)
86 #define FHSI_VALUE (48000000)
89 /* ------------------------- Interrupt Number Definition ------------------------ */
90 
91 typedef enum IRQn
92 {
93 /* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
94  NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
95  HardFault_IRQn = -13, /* 3 HardFault Interrupt */
96  MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
97  BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
98  UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
99  SVCall_IRQn = -5, /* 11 SV Call Interrupt */
100  DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
101  PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
102  SysTick_IRQn = -1, /* 15 System Tick Interrupt */
103 
104 /* ---------------------- MG32F10x Specific Interrupt Numbers --------------------- */
105  WWDG_IRQn = 0, /* Window WatchDog Interrupt */
106  PVD_IRQn = 1, /* PVD through EXTI Line detection Interrupt */
107  TAMPER_IRQn = 2, /* Tamper Interrupt */
108  RTC_IRQn = 3, /* RTC global Interrupt */
109  FMC_IRQn = 4, /* FMC global Interrupt */
110  RCC_IRQn = 5, /* RCC global Interrupt */
111  EXTI0_IRQn = 6, /* EXTI Line0 Interrupt */
112  EXTI1_IRQn = 7, /* EXTI Line1 Interrupt */
113  EXTI2_IRQn = 8, /* EXTI Line2 Interrupt */
114  EXTI3_IRQn = 9, /* EXTI Line3 Interrupt */
115  EXTI4_IRQn = 10, /* EXTI Line4 Interrupt */
116  DMAC1_IRQn = 11, /* DMAC1 Interrupt */
117  DMAC2_IRQn = 12, /* DMAC2 Interrupt */
118  ADC_IRQn = 13, /* ADC global Interrupt */
119  USB_IRQn = 14, /* USB Interrupt */
120  USB_DMA_IRQn = 15, /* USB DMA Interrupt */
121  EXTI9_5_IRQn = 16, /* External Line[9:5] Interrupts */
122  TIM1_BRK_IRQn = 17, /* TIM1 Break Interrupt */
123  TIM1_UP_IRQn = 18, /* TIM1 Update Interrupt */
124  TIM1_TRG_COM_IRQn = 19, /* TIM1 Trigger and Commutation Interrupt */
125  TIM1_CC_IRQn = 20, /* TIM1 Capture Compare Interrupt */
126  TIM2_IRQn = 21, /* TIM2 global Interrupt */
127  TIM3_IRQn = 22, /* TIM3 global Interrupt */
128  TIM4_IRQn = 23, /* TIM4 global Interrupt */
129  I2C1_IRQn = 24, /* I2C1 global Interrupt */
130  I2C2_IRQn = 25, /* I2C2 global Interrupt */
131  QSPI_IRQn = 26, /* QSPI global Interrupt */
132  SPIM2_IRQn = 27, /* SPIM2 global Interrupt */
133  SPIS1_IRQn = 28, /* SPIS1 global Interrupt */
134  SPIS2_IRQn = 29, /* SPIS2 global Interrupt */
135  UART1_IRQn = 30, /* UART1 global Interrupt */
136  UART2_IRQn = 31, /* UART2 global Interrupt */
137  UART3_IRQn = 32, /* UART3 global Interrupt */
138  EXTI15_10_IRQn = 33, /* External Line[15:10] Interrupts */
139  RTCAlarm_IRQn = 34, /* RTC Alarm through EXTI Line Interrupt */
140  USBP_WKUP_IRQn = 35, /* USB PIN global interrupt */
141  I2S_IRQn = 36, /* I2S global Interrupt */
142  ISO_IRQn = 37, /* ISO7816 global Interrupt */
143 } IRQn_Type;
144 
145 
146 /* ================================================================================ */
147 /* ================ Processor and Core Peripheral Section ================ */
148 /* ================================================================================ */
149 
150 /* ------- Start of section using anonymous unions and disabling warnings ------- */
151 #if defined (__CC_ARM)
152  #pragma push
153  #pragma anon_unions
154 #elif defined (__ICCARM__)
155  #pragma language=extended
156 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
157  #pragma clang diagnostic push
158  #pragma clang diagnostic ignored "-Wc11-extensions"
159  #pragma clang diagnostic ignored "-Wreserved-id-macro"
160 #elif defined (__GNUC__)
161  /* anonymous unions are enabled by default */
162 #elif defined (__TMS470__)
163  /* anonymous unions are enabled by default */
164 #elif defined (__TASKING__)
165  #pragma warning 586
166 #elif defined (__CSMC__)
167  /* anonymous unions are enabled by default */
168 #else
169  #warning Not supported compiler type
170 #endif
171 
172 
173 /* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */
174 #define __CM3_REV 0x0200U /* Core revision r2p0 */
175 #define __MPU_PRESENT 1 /* MG32F10x devices provide an MPU */
176 #define __VTOR_PRESENT 1 /* VTOR present or not */
177 #define __NVIC_PRIO_BITS 4 /* Number of Bits used for Priority Levels */
178 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
179 
180 #include "core_cm3.h" /* Processor and core peripherals */
181 #include "system_mg32f10x.h" /* System Header */
182 
183 
184 
185 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
186 
187 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
188 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
189 
190 typedef enum {INACTIVE = 0, ACTIVE = !INACTIVE} SignalState;
191 
192 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
193 
194 
195 /* ================================================================================ */
196 /* ================ Device Specific Peripheral Section ================ */
197 /* ================================================================================ */
198 
199 
200 /* ================================================================================ */
201 /* ================ General-purpose I/Os (GPIO) ================ */
202 /* ================================================================================ */
203 typedef struct
204 {
205  __IOM uint32_t MODER;
206  __IOM uint32_t OTYPER;
207  __IOM uint32_t OSPEEDR;
208  __IOM uint32_t PUPDR;
209  __IM uint32_t IDR;
210  __IOM uint32_t ODR;
211  __OM uint32_t BSRR;
212  __IOM uint32_t LCKR;
213  __IOM uint32_t AFRL;
214  __IOM uint32_t AFRH;
215  __IOM uint32_t SMIT;
216  __IOM uint32_t CURRENT;
217  __IOM uint32_t CFGMSK;
218 } GPIO_TypeDef;
219 
220 
221 /* ================================================================================ */
222 /* ================ Timer (TIM) ================ */
223 /* ================================================================================ */
224 typedef struct
225 {
226  __IOM uint32_t CR1;
227  __IOM uint32_t CR2;
228  __IOM uint32_t SMCR;
229  __IOM uint32_t DIER;
230  __IOM uint32_t SR;
231  __OM uint32_t EGR;
232  __IOM uint32_t CCMR1;
233  __IOM uint32_t CCMR2;
234  __IOM uint32_t CCER;
235  __IOM uint32_t CNT;
236  __IOM uint32_t PSC;
237  __IOM uint32_t ARR;
238  __IOM uint32_t RCR;
239  __IOM uint32_t CCR1;
240  __IOM uint32_t CCR2;
241  __IOM uint32_t CCR3;
242  __IOM uint32_t CCR4;
243  __IOM uint32_t BDTR;
244 } TIM_TypeDef;
245 
246 
247 /* ================================================================================ */
248 /* ================ External Interrupt/Event Controller (EXTI) ================ */
249 /* ================================================================================ */
250 typedef struct
251 {
252  __IOM uint32_t IMR;
253  __IOM uint32_t EMR;
254  __IOM uint32_t RTSR;
255  __IOM uint32_t FTSR;
256  __IOM uint32_t SWIER;
257  __IOM uint32_t PR;
258 } EXTI_TypeDef;
259 
260 
261 /* ================================================================================ */
262 /* ================ Alternate Function I/O (AFIO) ================ */
263 /* ================================================================================ */
264 typedef struct
265 {
266  uint32_t RESERVED0[2];
267  __IOM uint32_t EXTICR[4];
268 } AFIO_TypeDef;
269 
270 
271 /* ================================================================================ */
272 /* ================ Window watchdog (WWDG) ================ */
273 /* ================================================================================ */
274 typedef struct
275 {
276  __IOM uint32_t CR;
277  __IOM uint32_t CFR;
278  __IOM uint32_t SR;
279 } WWDG_TypeDef;
280 
281 
282 /* ================================================================================ */
283 /* ================ Independent watchdog (IWDG) ================ */
284 /* ================================================================================ */
285 typedef struct
286 {
287  __OM uint32_t KR;
288  __IOM uint32_t PR;
289  __IOM uint32_t RLR;
290  __IM uint32_t SR;
291 } IWDG_TypeDef;
292 
293 
294 /* ================================================================================ */
295 /* ================ Backup Registers (BKP) ================ */
296 /* ================================================================================ */
297 typedef struct
298 {
299  __IOM uint32_t RTCCR;
300  __IOM uint32_t CR;
301  __IOM uint32_t CSR;
302  uint32_t RESERVED0;
303  __IOM uint32_t DR1;
304  __IOM uint32_t DR2;
305  __IOM uint32_t DR3;
306  __IOM uint32_t DR4;
307  __IOM uint32_t DR5;
308  __IOM uint32_t DR6;
309  __IOM uint32_t DR7;
310  __IOM uint32_t DR8;
311  __IOM uint32_t DR9;
312  __IOM uint32_t DR10;
313  __IOM uint32_t DR11;
314  __IOM uint32_t DR12;
315  __IOM uint32_t DR13;
316  __IOM uint32_t DR14;
317  __IOM uint32_t DR15;
318  __IOM uint32_t DR16;
319  __IOM uint32_t DR17;
320  __IOM uint32_t DR18;
321  __IOM uint32_t DR19;
322  __IOM uint32_t DR20;
323  __IOM uint32_t DR21;
324  uint32_t RESERVED1[39];
325  __IOM uint32_t BDCR;
326 } BKP_TypeDef;
327 
328 
329 /* ================================================================================ */
330 /* ================ Real-Time Clock (RTC) ================ */
331 /* ================================================================================ */
332 typedef struct
333 {
334  __IOM uint16_t CRH; uint16_t RESERVED0;
335  __IOM uint16_t CRL; uint16_t RESERVED1;
336  __OM uint16_t PRLH; uint16_t RESERVED2;
337  union {
338  __IM uint32_t PRL;
339  __OM uint16_t PRLL;
340  };
341  __IM uint16_t DIVH; uint16_t RESERVED4;
342  union {
343  __IM uint32_t DIV;
344  __IM uint16_t DIVL;
345  };
346  __IOM uint16_t CNTH; uint16_t RESERVED5;
347  union {
348  __IM uint32_t CNT;
349  __IOM uint16_t CNTL;
350  };
351  __OM uint16_t ALRH; uint16_t RESERVED6;
352  union {
353  __IM uint32_t ALR;
354  __OM uint16_t ALRL;
355  };
356 } RTC_TypeDef;
357 
358 
359 /* ================================================================================ */
360 /* ================ LED ================ */
361 /* ================================================================================ */
362 typedef struct
363 {
364  __IOM uint32_t CON;
365  __IOM uint32_t CYC;
366  __IOM uint32_t ECO;
367  __IOM uint32_t SEGH;
368  __IOM uint32_t SEGL;
369 } LED_TypeDef;
370 
371 
372 /* ================================================================================ */
373 /* ================ Special Function Macro (SFM) ================ */
374 /* ================================================================================ */
375 typedef struct
376 {
377  __IOM uint32_t CTRL;
378  __IOM uint32_t DATA;
379  __IM uint32_t DOUT[8];
380  uint32_t RESERVED0[6];
381  __IOM uint32_t USBPCON;
382  __IOM uint32_t USBPSDCSR;
383  __IM uint32_t USBPSTAT;
384 } SFM_TypeDef;
385 
386 
387 /* ================================================================================ */
388 /* ================ ISO7816 (ISO) ================ */
389 /* ================================================================================ */
390 typedef struct
391 {
392  __OM uint32_t TXBUF;
393  __IM uint32_t RXBUF;
394  __IOM uint32_t TXDONE;
395  __IOM uint32_t RXDONE;
396  __IOM uint32_t STARTDET;
397  __IM uint32_t CLRTXDONE;
398  __IM uint32_t CLRRXDONE;
399  __IM uint32_t CLRSTART;
400  __IOM uint32_t TRANSR;
401  __IOM uint32_t FIFOSR;
402  __IOM uint32_t IER;
403  __IOM uint32_t MODE;
404  __IOM uint32_t ETU;
405  __IM uint32_t RISR;
406  __IM uint32_t ISR;
407 } ISO_TypeDef;
408 
409 
410 /* ================================================================================ */
411 /* ================ Cache Registers (CACHE) ================ */
412 /* ================================================================================ */
413 typedef struct
414 {
415  __IOM uint32_t CR;
416 } CACHE_TypeDef;
417 
418 
419 /* ================================================================================ */
420 /* ================ FMC ================ */
421 /* ================================================================================ */
422 typedef struct
423 {
424  __IOM uint32_t CON;
425  __IOM uint32_t CRCON;
426  __IOM uint32_t STAT;
427  __OM uint32_t KEY;
428  __IOM uint32_t ADDR;
429  uint32_t RESERVED2[2];
430  __IM uint32_t DATA1;
431  uint32_t RESERVED3[56];
432  __OM uint32_t BUF[64];
433 } FMC_TypeDef;
434 
435 
436 /* ================================================================================ */
437 /* ================ SYS ================ */
438 /* ================================================================================ */
439 typedef struct
440 {
441  __IM uint32_t ID;
442  __IM uint32_t MEMSZ;
443  uint32_t RESERVED0;
444  __IM uint32_t BTCR;
445  __IM uint32_t MEMWEN;
446  __IM uint32_t SENDEV;
447  __IM uint32_t RSTCR;
448  __IM uint32_t IF4LCK;
449  __IM uint32_t IF5LCK;
450  __IM uint32_t IF6LCK;
451  __IM uint32_t IF7LCK;
452  uint32_t RESERVED1[2];
453  __IM uint32_t BTSR;
454 } SYS_TypeDef;
455 
456 
457 /* ================================================================================ */
458 /* ================ Cyclic Redundancy Check (CRC) ================ */
459 /* ================================================================================ */
460 typedef struct
461 {
462  __IOM uint32_t MODE;
463  __IOM uint32_t SEED;
464  union {
465  __IM uint32_t SUM;
466  __OM uint32_t WR_DATA_WORD;
467  __OM uint16_t WR_DATA_HALF_WORD;
468  __OM uint8_t WR_DATA_BYTE;
469  };
470 } CRC_TypeDef;
471 
472 
473 
474 /* ================================================================================ */
475 /* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
476 /* ================================================================================ */
477 typedef struct
478 {
479  union {
480  __IM uint32_t RBR;
481  __OM uint32_t THR;
482  __IOM uint32_t DLL;
483  };
484  union {
485  __IOM uint32_t DLH;
486  __IOM uint32_t IER;
487  };
488  union {
489  __IM uint32_t IIR;
490  __OM uint32_t FCR;
491  };
492  __IOM uint32_t LCR;
493  __IOM uint32_t MCR;
494  __IM uint32_t LSR;
495  __IM uint32_t MSR;
496  __IOM uint32_t SCR;
497  uint32_t RESERVED0[23];
498  __IM uint32_t USR;
499  __IM uint32_t TFL;
500  __IM uint32_t RFL;
501  __OM uint32_t SRR;
502  __IOM uint32_t SRTS;
503  __IOM uint32_t SBCR;
504  uint32_t RESERVED1;
505  __IOM uint32_t SFE;
506  __IOM uint32_t SRT;
507  __IOM uint32_t STET;
508  __IOM uint32_t HTX;
509  __OM uint32_t DMASA;
510  uint32_t RESERVED2[5];
511  __IOM uint32_t DLF;
512  __IOM uint32_t RAR;
513  __IOM uint32_t TAR;
514  __IOM uint32_t EXTLCR;
515 } UART_TypeDef;
516 
517 
518 /* ================================================================================ */
519 /* ============== Direct Memory Access Controller (DMAC) ============= */
520 /* ================================================================================ */
521 typedef struct
522 {
523  struct {
524  __IOM uint32_t SAR; uint32_t Undefined_SAR;
525  __IOM uint32_t DAR; uint32_t Undefined_DAR;
526  uint32_t RESERVED0[2];
527  __IOM uint32_t CTLL;
528  __IOM uint32_t CTLH;
529  uint32_t RESERVED1[8];
530  __IOM uint32_t CFGL;
531  __IOM uint32_t CFGH;
532  __IOM uint32_t SGR; uint32_t Undefined_SGR;
533  __IOM uint32_t DSR; uint32_t Undefined_DSR;
534  } Ch[3];
535  uint32_t RESERVED2[110];
536  __IM uint32_t RawTfr; uint32_t Undefined_RawTfr;
537  __IM uint32_t RawBlock; uint32_t Undefined_RawBlock;
538  __IM uint32_t RawSrcTran; uint32_t Undefined_RawSrcTran;
539  __IM uint32_t RawDstTran; uint32_t Undefined_RawDstTran;
540  __IM uint32_t RawErr; uint32_t Undefined_RawErr;
541  __IM uint32_t StatusTfr; uint32_t Undefined_StatusTfr;
542  __IM uint32_t StatusBlock; uint32_t Undefined_StatusBlock;
543  __IM uint32_t StatusSrcTran; uint32_t Undefined_StatusSrcTran;
544  __IM uint32_t StatusDstTran; uint32_t Undefined_StatusDstTran;
545  __IM uint32_t StatusErr; uint32_t Undefined_StatusErr;
546  __IOM uint32_t MaskTfr; uint32_t Undefined_MaskTfr;
547  __IOM uint32_t MaskBlock; uint32_t Undefined_MaskBlock;
548  __IOM uint32_t MaskSrcTran; uint32_t Undefined_MaskSrcTran;
549  __IOM uint32_t MaskDstTran; uint32_t Undefined_MaskDstTran;
550  __IOM uint32_t MaskErr; uint32_t Undefined_MaskErr;
551  __OM uint32_t ClearTfr; uint32_t Undefined_ClearTfr;
552  __OM uint32_t ClearBlock; uint32_t Undefined_ClearBlock;
553  __OM uint32_t ClearSrcTran; uint32_t Undefined_ClearSrcTran;
554  __OM uint32_t ClearDstTran; uint32_t Undefined_ClearDstTran;
555  __OM uint32_t ClearErr; uint32_t Undefined_ClearErr;
556  __IM uint32_t StatusInt; uint32_t Undefined_StatusInt;
557  __IOM uint32_t ReqSrcReg; uint32_t Undefined_ReqSrcReg;
558  __IOM uint32_t ReqDstReg; uint32_t Undefined_ReqDstReg;
559  __IOM uint32_t SglReqSrcReg; uint32_t Undefined_SglReqSrcReg;
560  __IOM uint32_t SglReqDstReg; uint32_t Undefined_SglReqDstReg;
561  __IOM uint32_t LstSrcReg; uint32_t Undefined_LstSrcReg;
562  __IOM uint32_t LstDstReg; uint32_t Undefined_LstDstReg;
563  __IOM uint32_t DmaCfgReg; uint32_t Undefined_DmaCfgReg;
564  __IOM uint32_t ChEnReg; uint32_t Undefined_ChEnReg;
565 } DMAC_TypeDef;
566 
567 
568 /* ================================================================================ */
569 /* ============== Serial Peripheral Interface (SPI) ============= */
570 /* ================================================================================ */
571 typedef struct
572 {
573  __IOM uint32_t CR0;
574  __IOM uint32_t CR1;
575  __IOM uint32_t SPIENR;
576  __IOM uint32_t MWCR;
577  __IOM uint32_t SER;
578  __IOM uint32_t BAUDR;
579  __IOM uint32_t TXFTLR;
580  __IOM uint32_t RXFTLR;
581  __IM uint32_t TXFLR;
582  __IM uint32_t RXFLR;
583  __IM uint32_t SR;
584  __IOM uint32_t IER;
585  __IM uint32_t ISR;
586  __IM uint32_t RISR;
587  __IM uint32_t TXOICR;
588  __IM uint32_t RXOICR;
589  __IM uint32_t RXUICR;
590  __IM uint32_t MSTICR;
591  __IM uint32_t ICR;
592  __IOM uint32_t DMACR;
593  __IOM uint32_t DMATDLR;
594  __IOM uint32_t DMARDLR;
595  uint32_t RESERVED0[2];
596  __IOM uint32_t DR;
597  uint32_t RESERVED1[35];
598  __IOM uint32_t RX_SAMPLE_DLY;
599  __IOM uint32_t ESPICR;
600 } SPI_TypeDef;
601 
602 
603 /* ================================================================================ */
604 /* ============== Inter-Integrated Circuit (I2C) ============= */
605 /* ================================================================================ */
606 typedef struct
607 {
608  __IOM uint32_t CON;
609  __IOM uint32_t TAR;
610  __IOM uint32_t SAR;
611  __IOM uint32_t HS_MADDR;
612  __IOM uint32_t DATA_CMD;
613  __IOM uint32_t SS_SCL_HCNT;
614  __IOM uint32_t SS_SCL_LCNT;
615  __IOM uint32_t FS_SCL_HCNT;
616  __IOM uint32_t FS_SCL_LCNT;
617  __IOM uint32_t HS_SCL_HCNT;
618  __IOM uint32_t HS_SCL_LCNT;
619  __IM uint32_t INTR_STAT;
620  __IOM uint32_t INTR_MASK;
621  __IM uint32_t RAW_INTR_STAT;
622  __IOM uint32_t RX_TL;
623  __IOM uint32_t TX_TL;
624  __IM uint32_t CLR_INTR;
625  __IM uint32_t CLR_RX_UNDER;
626  __IM uint32_t CLR_RX_OVER;
627  __IM uint32_t CLR_TX_OVER;
628  __IM uint32_t CLR_RD_REQ;
629  __IM uint32_t CLR_TX_ABRT;
630  __IM uint32_t CLR_RX_DONE;
631  __IM uint32_t CLR_ACTIVITY;
632  __IM uint32_t CLR_STOP_DET;
633  __IM uint32_t CLR_START_DET;
634  __IM uint32_t CLR_GEN_CALL;
635  __IOM uint32_t ENABLE;
636  __IM uint32_t STATUS;
637  __IM uint32_t TXFLR;
638  __IM uint32_t RXFLR;
639  __IOM uint32_t SDA_HOLD;
640  __IM uint32_t TX_ABRT_SOURCE;
641  __IOM uint32_t SLV_DATA_NACK_ONLY;
642  __IOM uint32_t DMA_CR;
643  __IOM uint32_t DMA_TDLR;
644  __IOM uint32_t DMA_RDLR;
645  __IOM uint32_t SDA_SETUP;
646  __IOM uint32_t ACK_GENERAL_CALL;
647  __IM uint32_t ENABLE_STATUS;
648  __IOM uint32_t FS_SPKLEN;
649  __IOM uint32_t HS_SPKLEN;
650  __IM uint32_t CLR_RESTART_DET;
651  __IOM uint32_t SCL_STUCK_AT_LOW_TIMEOUT;
652  __IOM uint32_t SDA_STUCK_AT_LOW_TIMEOUT;
653  __IM uint32_t CLR_SCL_STUCK_DET;
654  uint32_t RESERVED0;
655  __IOM uint32_t SMBUS_CLK_LOW_SEXT;
656  __IOM uint32_t SMBUS_CLK_LOW_MEXT;
657  __IOM uint32_t SMBUS_THIGH_MAX_IDLE_COUNT;
658  __IM uint32_t SMBUS_INTR_STAT;
659  __IOM uint32_t SMBUS_INTR_MASK;
660  __IM uint32_t SMBUS_RAW_INTR_STAT;
661  __OM uint32_t CLR_SMBUS_INTR;
662  __IOM uint32_t OPTIONAL_SAR;
663  __IOM uint32_t SMBUS_UDID_LSB;
664 } I2C_TypeDef;
665 
666 
667 /* ================================================================================ */
668 /* ================ Inter-IC Sound (I2S) ================ */
669 /* ================================================================================ */
670 typedef struct
671 {
672  __IOM uint32_t IER;
673  __IOM uint32_t IRER;
674  __IOM uint32_t ITER;
675  __IOM uint32_t CER;
676  __IOM uint32_t CCR;
677  __OM uint32_t RXFFR;
678  __OM uint32_t TXFFR;
679  uint32_t RESERVED0;
680  struct {
681  union {
682  __IM uint32_t LRBR;
683  __OM uint32_t LTHR;
684  };
685  union {
686  __IM uint32_t RRBR;
687  __OM uint32_t RTHR;
688  };
689  __IOM uint32_t RER;
690  __IOM uint32_t TER;
691  __IOM uint32_t RCR;
692  __IOM uint32_t TCR;
693  __IM uint32_t ISR;
694  __IOM uint32_t IMR;
695  __IM uint32_t ROR;
696  __IM uint32_t TOR;
697  __IOM uint32_t RFCR;
698  __IOM uint32_t TFCR;
699  __OM uint32_t RFF;
700  __OM uint32_t TFF;
701  uint32_t RESERVED0;
702  uint32_t RESERVED1;
703  } Ch[2];
704  uint32_t RESERVED1[72];
705  __IM uint32_t RXDMA;
706  __OM uint32_t RRXDMA;
707  __OM uint32_t TXDMA;
708  __OM uint32_t RTXDMA;
709 } I2S_TypeDef;
710 
711 
712 /* ================================================================================ */
713 /* ============== Random Number Generator (RNG) ============= */
714 /* ================================================================================ */
715 typedef struct
716 {
717  __IM uint32_t RAND;
718  __IOM uint32_t STOP;
719 } RNG_TypeDef;
720 
721 
722 /* ================================================================================ */
723 /* ============== Universal Serial Bus (USB) ============= */
724 /* ================================================================================ */
725 typedef struct
726 {
727  __IOM uint8_t FADDR;
728  __IOM uint8_t POWER;
729  __IM uint8_t INTRIN;
730  uint8_t RESERVED0;
731  __IM uint8_t INTROUT;
732  uint8_t RESERVED1;
733  __IM uint8_t INTRUSB;
734  __IOM uint8_t INTRINE;
735  uint8_t RESERVED2;
736  __IOM uint8_t INTROUTE;
737  uint8_t RESERVED3;
738  __IOM uint8_t INTRUSBE;
739  __IM uint8_t FRAMEL;
740  __IM uint8_t FRAMEH;
741  __IOM uint8_t INDEX;
742  uint8_t RESERVED4;
744  __IOM uint8_t INMAXP;
745  union {
746  __IOM uint8_t CSR0;
747  __IOM uint8_t INCSR1;
748  };
749  __IOM uint8_t INCSR2;
750  __IOM uint8_t OUTMAXP;
751  __IOM uint8_t OUTCSR1;
752  __IOM uint8_t OUTCSR2;
753  union {
754  __IM uint8_t COUNT0;
755  __IM uint8_t OUTCOUNTL;
756  };
757  __IM uint8_t OUTCOUNTH;
758  uint8_t RESERVED5[8];
760  __IOM uint32_t FIFO[16];
761  uint32_t RESERVED6[104];
763  __IOM uint32_t DMAINTR;
764  struct {
765  __IOM uint32_t CNTL;
766  __IOM uint32_t ADDR;
767  __IOM uint32_t COUNT;
768  uint32_t RESERVED;
769  } DMACH[8];
770 } USB_TypeDef;
771 
772 
773 /* ================================================================================ */
774 /* ================ Analog to Digital Converter (ADC) ================ */
775 /* ================================================================================ */
776 typedef struct
777 {
778  __IOM uint32_t SR;
779  __IOM uint32_t CR1;
780  __IOM uint32_t CR2;
781  __IOM uint32_t SMPR1;
782  __IOM uint32_t SMPR2;
783  __IOM uint32_t JOFR1;
784  __IOM uint32_t JOFR2;
785  __IOM uint32_t JOFR3;
786  __IOM uint32_t JOFR4;
787  __IOM uint32_t HTR;
788  __IOM uint32_t LTR;
789  __IOM uint32_t SQR1;
790  __IOM uint32_t SQR2;
791  __IOM uint32_t SQR3;
792  __IOM uint32_t JSQR;
793  __IOM uint32_t JDR1;
794  __IOM uint32_t JDR2;
795  __IOM uint32_t JDR3;
796  __IOM uint32_t JDR4;
797  __IOM uint32_t DR;
798  __IOM uint32_t HS;
799  __IOM uint32_t CR3;
800  __IOM uint32_t JDMAR;
801 } ADC_TypeDef;
802 
803 
804 /* ================================================================================ */
805 /* ================ ANCTL ================ */
806 /* ================================================================================ */
807 typedef struct
808 {
809  uint32_t RESERVED0[7];
810  __IOM uint32_t BGCR2;
811  uint32_t RESERVED1[3];
812  __IOM uint32_t MHSIENR;
813  __IOM uint32_t MHSISR;
814  uint32_t RESERVED2;
815  __IOM uint32_t FHSIENR;
816  __IOM uint32_t FHSISR;
817  uint32_t RESERVED3;
818  __IOM uint32_t LSIENR;
819  __IOM uint32_t LSISR;
820  __IOM uint32_t HSECR0;
821  __IOM uint32_t HSECR1;
822  uint32_t RESERVED4;
823  __IOM uint32_t HSESR;
824  uint32_t RESERVED5[6];
825  __IOM uint32_t PLLCR;
826  __IOM uint32_t PLLENR;
827  __IOM uint32_t PLLSR;
828  __IOM uint32_t PVDCR;
829  __IOM uint32_t PVDENR;
830  uint32_t RESERVED6;
831  __IOM uint32_t SARENR;
832  __IOM uint32_t USBPCR;
833  __IOM uint32_t PORCR;
834  __IOM uint32_t CMPACR;
835  __IOM uint32_t CMPBCR;
836  __IOM uint32_t ISR;
837  __IOM uint32_t IER;
838  __IOM uint32_t ICR;
839  __IOM uint32_t CMPASR;
840  __IOM uint32_t CMPBSR;
841  __IOM uint32_t DCSSENR;
842  __IOM uint32_t DCSSCR;
843 } ANCTL_TypeDef;
844 
845 
846 /* ================================================================================ */
847 /* ================ Reset and Clock Control (RCC) ================ */
848 /* ================================================================================ */
849 typedef struct
850 {
851  __IOM uint32_t PLLPRE;
852  __IOM uint32_t PLLSRC;
853  __IOM uint32_t MAINCLKSRC;
854  __IOM uint32_t MAINCLKUEN;
855  uint32_t RESERVED0;
856  __IOM uint32_t USBPRE;
857  __IOM uint32_t AHBPRE;
858  __IOM uint32_t APB1PRE;
859  __IOM uint32_t APB2PRE;
860  __IOM uint32_t MCLKPRE;
861  __IOM uint32_t I2SPRE;
862  __IOM uint32_t MCLKSRC;
863  uint32_t RESERVED1;
864  __IOM uint32_t USBFIFOCLKSRC;
865  __IOM uint32_t MCOSEL;
866  __IOM uint32_t AHBENR0;
867  __IOM uint32_t AHBENR1;
868  __IOM uint32_t AHBENR2;
869  __IOM uint32_t APB1ENR;
870  __IOM uint32_t APB2ENR;
871  uint32_t RESERVED2[3];
872  __IOM uint32_t RNGCLKENR;
873  __IOM uint32_t PCLKENR;
874  __IOM uint32_t IWDGCLKENR;
875  uint32_t RESERVED4;
876  __IOM uint32_t USBCLKENR;
877  __IOM uint32_t I2SCLKENR;
878  __IOM uint32_t SPIS1CLKENR;
879  __IOM uint32_t SPIS2CLKENR;
880  __IOM uint32_t USBFIFOCLKENR;
881  uint32_t RESERVED5[2];
882  __IOM uint32_t AHBRSTR1;
883  uint32_t RESERVED6;
884  __IOM uint32_t APB1RSTR;
885  __IOM uint32_t APB2RSTR;
886  uint32_t RESERVED7[8];
887  __IOM uint32_t I2SCLKRSTR;
888  uint32_t RESERVED8[3];
889  __IOM uint32_t CLRRSTSTAT;
890  uint32_t RESERVED9[2];
891  __IOM uint32_t BDRSTR;
892  __IOM uint32_t LSI2RTCENR;
893  __IOM uint32_t HSE2RTCENR;
894  uint32_t RESERVED10[8];
895  __IOM uint32_t RSTSTAT;
896 } RCC_TypeDef;
897 
898 
899 /* ================================================================================ */
900 /* ================ Power Control (PWR) ================ */
901 /* ================================================================================ */
902 typedef struct
903 {
904  __IOM uint32_t CR0;
905  __OM uint32_t CR1;
906  __IOM uint32_t CR2;
907  uint32_t RESERVED0;
908  __IM uint32_t SR0;
909  __IM uint32_t SR1;
910  __IOM uint32_t GPREG0;
911  __IOM uint32_t GPREG1;
912  __IOM uint32_t CFGR;
913  uint32_t RESERVED1;
914  __OM uint32_t ANAKEY1;
915  __OM uint32_t ANAKEY2;
916 } PWR_TypeDef;
917 
918 
919 /* ================================================================================ */
920 /* ================ Debug MCU (DBGMCU) ================ */
921 /* ================================================================================ */
922 typedef struct
923 {
924  uint32_t RESERVED0;
925  __IOM uint32_t CR;
927 
928 
929 /* -------- End of section using anonymous unions and disabling warnings -------- */
930 #if defined (__CC_ARM)
931  #pragma pop
932 #elif defined (__ICCARM__)
933  /* leave anonymous unions enabled */
934 #elif (__ARMCC_VERSION >= 6010050)
935  #pragma clang diagnostic pop
936 #elif defined (__GNUC__)
937  /* anonymous unions are enabled by default */
938 #elif defined (__TMS470__)
939  /* anonymous unions are enabled by default */
940 #elif defined (__TASKING__)
941  #pragma warning restore
942 #elif defined (__CSMC__)
943  /* anonymous unions are enabled by default */
944 #else
945  #warning Not supported compiler type
946 #endif
947 
948 
949 
950 
951 /* ================================================================================ */
952 /* ================ Peripheral memory map ================ */
953 /* ================================================================================ */
954 #define FLASH_BASE ((uint32_t)0x08000000UL)
955 #define SRAM_BASE ((uint32_t)0x20000000UL)
956 #define PERIPH_BASE ((uint32_t)0x40000000UL)
958 #define SRAM_BB_BASE ((uint32_t)0x22000000UL)
959 #define PERIPH_BB_BASE ((uint32_t)0x42000000UL)
961 #define APB1PERIPH_BASE PERIPH_BASE
962 #define APB2PERIPH_BASE (PERIPH_BASE + 0x08000)
963 #define AHBPERIPH_BASE (PERIPH_BASE + 0x10000)
964 
965 
966 #define GPIOA_BASE (APB1PERIPH_BASE + 0x0000) // 4000_0000
967 #define GPIOB_BASE (APB1PERIPH_BASE + 0x0400) // 4000_0400
968 #define GPIOC_BASE (APB1PERIPH_BASE + 0x0800) // 4000_0800
969 #define GPIOD_BASE (APB1PERIPH_BASE + 0x0C00) // 4000_0C00
970 #define AFIO_BASE (APB1PERIPH_BASE + 0x1400) // 4000_1400
971 #define EXTI_BASE (APB1PERIPH_BASE + 0x1800) // 4000_1800
972 #define TIM1_BASE (APB1PERIPH_BASE + 0x1C00) // 4000_1C00
973 #define TIM2_BASE (APB1PERIPH_BASE + 0x2000) // 4000_2000
974 #define TIM3_BASE (APB1PERIPH_BASE + 0x2400) // 4000_2400
975 #define TIM4_BASE (APB1PERIPH_BASE + 0x2800) // 4000_2800
976 #define QSPI_BASE (APB1PERIPH_BASE + 0x3000) // 4000_3000
977 #define SPIS1_BASE (APB1PERIPH_BASE + 0x3400) // 4000_3400
978 #define UART1_BASE (APB1PERIPH_BASE + 0x3800) // 4000_3800
979 #define ADC_BASE (APB1PERIPH_BASE + 0x3C00) // 4000_3C00
980 #define DMAC1_BASE (APB1PERIPH_BASE + 0x7C00) // 4000_7C00
981 
982 #define UART2_BASE (APB2PERIPH_BASE + 0x0000) // 4000_8000
983 #define UART3_BASE (APB2PERIPH_BASE + 0x0400) // 4000_8400
984 #define I2C1_BASE (APB2PERIPH_BASE + 0x0800) // 4000_8800
985 #define I2C2_BASE (APB2PERIPH_BASE + 0x0C00) // 4000_8C00
986 #define SPIM2_BASE (APB2PERIPH_BASE + 0x1000) // 4000_9000
987 #define SPIS2_BASE (APB2PERIPH_BASE + 0x1400) // 4000_9400
988 #define WWDG_BASE (APB2PERIPH_BASE + 0x1800) // 4000_9800
989 #define I2S_BASE (APB2PERIPH_BASE + 0x3400) // 4000_B400
990 #define RNG_BASE (APB2PERIPH_BASE + 0x3800) // 4000_B800
991 #define LED_BASE (APB2PERIPH_BASE + 0x3C00) // 4000_BC00
992 #define DMAC2_BASE (APB2PERIPH_BASE + 0x7C00) // 4000_FC00
993 
994 #define PWR_BASE (AHBPERIPH_BASE + 0x0000) // 4001_0000
995 #define ANCTL_BASE (AHBPERIPH_BASE + 0x0400) // 4001_0400
996 #define IWDG_BASE (AHBPERIPH_BASE + 0x0800) // 4001_0800
997 #define RCC_BASE (AHBPERIPH_BASE + 0x0C00) // 4001_0C00
998 #define USB_BASE (AHBPERIPH_BASE + 0x4000) // 4001_4000
999 #define CRC_BASE (AHBPERIPH_BASE + 0x4800) // 4001_4800
1000 #define SFM_BASE (AHBPERIPH_BASE + 0x4C00) // 4001_4C00
1001 #define CACHE_BASE (AHBPERIPH_BASE + 0x5400) // 4001_5400
1002 #define RTC_BASE (AHBPERIPH_BASE + 0x5800) // 4001_5800
1003 #define BKP_BASE (AHBPERIPH_BASE + 0x5C00) // 4001_5C00
1004 #define ISO_BASE (AHBPERIPH_BASE + 0x6000) // 4001_6000
1005 #define SYS_BASE (AHBPERIPH_BASE + 0x6400) // 4001_6400
1006 #define FMC_BASE (AHBPERIPH_BASE + 0x7800) // 4001_7800
1007 
1008 #define DBGMCU_BASE (0xE0042000UL) // E004_2000
1009 
1010 
1011 
1012 
1013 
1014 /* ================================================================================ */
1015 /* ================ Peripheral declaration ================ */
1016 /* ================================================================================ */
1017 #define GPIOA (( GPIO_TypeDef *) GPIOA_BASE)
1018 #define GPIOB (( GPIO_TypeDef *) GPIOB_BASE)
1019 #define GPIOC (( GPIO_TypeDef *) GPIOC_BASE)
1020 #define GPIOD (( GPIO_TypeDef *) GPIOD_BASE)
1021 #define AFIO (( AFIO_TypeDef *) AFIO_BASE)
1022 #define EXTI (( EXTI_TypeDef *) EXTI_BASE)
1023 #define TIM1 (( TIM_TypeDef *) TIM1_BASE)
1024 #define TIM2 (( TIM_TypeDef *) TIM2_BASE)
1025 #define TIM3 (( TIM_TypeDef *) TIM3_BASE)
1026 #define TIM4 (( TIM_TypeDef *) TIM4_BASE)
1027 #define QSPI (( SPI_TypeDef *) QSPI_BASE)
1028 #define SPIS1 (( SPI_TypeDef *) SPIS1_BASE)
1029 #define UART1 (( UART_TypeDef *) UART1_BASE)
1030 #define ADC (( ADC_TypeDef *) ADC_BASE)
1031 #define DMAC1 (( DMAC_TypeDef *) DMAC1_BASE)
1032 
1033 #define UART2 (( UART_TypeDef *) UART2_BASE)
1034 #define UART3 (( UART_TypeDef *) UART3_BASE)
1035 #define I2C1 (( I2C_TypeDef *) I2C1_BASE)
1036 #define I2C2 (( I2C_TypeDef *) I2C2_BASE)
1037 #define SPIM2 (( SPI_TypeDef *) SPIM2_BASE)
1038 #define SPIS2 (( SPI_TypeDef *) SPIS2_BASE)
1039 #define WWDG (( WWDG_TypeDef *) WWDG_BASE)
1040 #define I2S (( I2S_TypeDef *) I2S_BASE)
1041 #define RNG (( RNG_TypeDef *) RNG_BASE)
1042 #define LED (( LED_TypeDef *) LED_BASE)
1043 #define DMAC2 (( DMAC_TypeDef *) DMAC2_BASE)
1044 
1045 #define PWR (( PWR_TypeDef *) PWR_BASE)
1046 #define ANCTL (( ANCTL_TypeDef *) ANCTL_BASE)
1047 #define IWDG (( IWDG_TypeDef *) IWDG_BASE)
1048 #define RCC (( RCC_TypeDef *) RCC_BASE)
1049 #define USB (( USB_TypeDef *) USB_BASE)
1050 #define CRC (( CRC_TypeDef *) CRC_BASE)
1051 #define SFM (( SFM_TypeDef *) SFM_BASE)
1052 #define CACHE (( CACHE_TypeDef *) CACHE_BASE)
1053 #define RTC (( RTC_TypeDef *) RTC_BASE)
1054 #define BKP (( BKP_TypeDef *) BKP_BASE)
1055 #define ISO (( ISO_TypeDef *) ISO_BASE)
1056 #define SYS (( SYS_TypeDef *) SYS_BASE)
1057 #define FMC (( FMC_TypeDef *) FMC_BASE)
1058 
1059 #define DBGMCU (( DBGMCU_TypeDef *) DBGMCU_BASE)
1060 
1061 
1062 
1063 
1064 
1065 
1066 
1067 /*------------------------------------------------------------------------------------------------------*/
1068 /*--- General-purpose I/Os (GPIO) ---*/
1069 /*------------------------------------------------------------------------------------------------------*/
1070 /******************************** Bit definition for GPIO_MODER register ******************************/
1071 #define GPIO_MODER_MODER0_Pos (0U)
1072 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos)
1073 #define GPIO_MODER_MODER1_Pos (2U)
1074 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos)
1075 #define GPIO_MODER_MODER2_Pos (4U)
1076 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos)
1077 #define GPIO_MODER_MODER3_Pos (6U)
1078 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos)
1079 #define GPIO_MODER_MODER4_Pos (8U)
1080 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos)
1081 #define GPIO_MODER_MODER5_Pos (10U)
1082 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos)
1083 #define GPIO_MODER_MODER6_Pos (12U)
1084 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos)
1085 #define GPIO_MODER_MODER7_Pos (14U)
1086 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos)
1087 #define GPIO_MODER_MODER8_Pos (16U)
1088 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos)
1089 #define GPIO_MODER_MODER9_Pos (18U)
1090 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos)
1091 #define GPIO_MODER_MODER10_Pos (20U)
1092 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos)
1093 #define GPIO_MODER_MODER11_Pos (22U)
1094 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos)
1095 #define GPIO_MODER_MODER12_Pos (24U)
1096 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos)
1097 #define GPIO_MODER_MODER13_Pos (26U)
1098 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos)
1099 #define GPIO_MODER_MODER14_Pos (28U)
1100 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos)
1101 #define GPIO_MODER_MODER15_Pos (30U)
1102 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos)
1103 
1104 /******************************** Bit definition for GPIO_OTYPER register ******************************/
1105 #define GPIO_OTYPER_OT0 (0x1U << 0)
1106 #define GPIO_OTYPER_OT1 (0x1U << 1)
1107 #define GPIO_OTYPER_OT2 (0x1U << 2)
1108 #define GPIO_OTYPER_OT3 (0x1U << 3)
1109 #define GPIO_OTYPER_OT4 (0x1U << 4)
1110 #define GPIO_OTYPER_OT5 (0x1U << 5)
1111 #define GPIO_OTYPER_OT6 (0x1U << 6)
1112 #define GPIO_OTYPER_OT7 (0x1U << 7)
1113 #define GPIO_OTYPER_OT8 (0x1U << 8)
1114 #define GPIO_OTYPER_OT9 (0x1U << 9)
1115 #define GPIO_OTYPER_OT10 (0x1U << 10)
1116 #define GPIO_OTYPER_OT11 (0x1U << 11)
1117 #define GPIO_OTYPER_OT12 (0x1U << 12)
1118 #define GPIO_OTYPER_OT13 (0x1U << 13)
1119 #define GPIO_OTYPER_OT14 (0x1U << 14)
1120 #define GPIO_OTYPER_OT15 (0x1U << 15)
1121 
1122 /******************************** Bit definition for GPIO_OSPEEDR register ******************************/
1123 #define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
1124 #define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos)
1125 #define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
1126 #define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos)
1127 #define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
1128 #define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos)
1129 #define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
1130 #define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos)
1131 #define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
1132 #define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos)
1133 #define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
1134 #define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos)
1135 #define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
1136 #define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos)
1137 #define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
1138 #define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos)
1139 #define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
1140 #define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos)
1141 #define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
1142 #define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos)
1143 #define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
1144 #define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos)
1145 #define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
1146 #define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos)
1147 #define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
1148 #define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos)
1149 #define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
1150 #define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos)
1151 #define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
1152 #define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos)
1153 #define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
1154 #define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos)
1155 
1156 /******************************** Bit definition for GPIO_PUPDR register ******************************/
1157 #define GPIO_PUPDR_PUPDR0_Pos (0U)
1158 #define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos)
1159 #define GPIO_PUPDR_PUPDR1_Pos (2U)
1160 #define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos)
1161 #define GPIO_PUPDR_PUPDR2_Pos (4U)
1162 #define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos)
1163 #define GPIO_PUPDR_PUPDR3_Pos (6U)
1164 #define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos)
1165 #define GPIO_PUPDR_PUPDR4_Pos (8U)
1166 #define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos)
1167 #define GPIO_PUPDR_PUPDR5_Pos (10U)
1168 #define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos)
1169 #define GPIO_PUPDR_PUPDR6_Pos (12U)
1170 #define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos)
1171 #define GPIO_PUPDR_PUPDR7_Pos (14U)
1172 #define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos)
1173 #define GPIO_PUPDR_PUPDR8_Pos (16U)
1174 #define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos)
1175 #define GPIO_PUPDR_PUPDR9_Pos (18U)
1176 #define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos)
1177 #define GPIO_PUPDR_PUPDR10_Pos (20U)
1178 #define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos)
1179 #define GPIO_PUPDR_PUPDR11_Pos (22U)
1180 #define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos)
1181 #define GPIO_PUPDR_PUPDR12_Pos (24U)
1182 #define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos)
1183 #define GPIO_PUPDR_PUPDR13_Pos (26U)
1184 #define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos)
1185 #define GPIO_PUPDR_PUPDR14_Pos (28U)
1186 #define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos)
1187 #define GPIO_PUPDR_PUPDR15_Pos (30U)
1188 #define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos)
1189 
1190 /******************************** Bit definition for GPIO_IDR register ******************************/
1191 #define GPIO_IDR_IDR0 (0x1U << 0)
1192 #define GPIO_IDR_IDR1 (0x1U << 1)
1193 #define GPIO_IDR_IDR2 (0x1U << 2)
1194 #define GPIO_IDR_IDR3 (0x1U << 3)
1195 #define GPIO_IDR_IDR4 (0x1U << 4)
1196 #define GPIO_IDR_IDR5 (0x1U << 5)
1197 #define GPIO_IDR_IDR6 (0x1U << 6)
1198 #define GPIO_IDR_IDR7 (0x1U << 7)
1199 #define GPIO_IDR_IDR8 (0x1U << 8)
1200 #define GPIO_IDR_IDR9 (0x1U << 9)
1201 #define GPIO_IDR_IDR10 (0x1U << 10)
1202 #define GPIO_IDR_IDR11 (0x1U << 11)
1203 #define GPIO_IDR_IDR12 (0x1U << 12)
1204 #define GPIO_IDR_IDR13 (0x1U << 13)
1205 #define GPIO_IDR_IDR14 (0x1U << 14)
1206 #define GPIO_IDR_IDR15 (0x1U << 15)
1208 /******************************** Bit definition for GPIO_ODR register ******************************/
1209 #define GPIO_ODR_ODR0 (0x1U << 0)
1210 #define GPIO_ODR_ODR1 (0x1U << 1)
1211 #define GPIO_ODR_ODR2 (0x1U << 2)
1212 #define GPIO_ODR_ODR3 (0x1U << 3)
1213 #define GPIO_ODR_ODR4 (0x1U << 4)
1214 #define GPIO_ODR_ODR5 (0x1U << 5)
1215 #define GPIO_ODR_ODR6 (0x1U << 6)
1216 #define GPIO_ODR_ODR7 (0x1U << 7)
1217 #define GPIO_ODR_ODR8 (0x1U << 8)
1218 #define GPIO_ODR_ODR9 (0x1U << 9)
1219 #define GPIO_ODR_ODR10 (0x1U << 10)
1220 #define GPIO_ODR_ODR11 (0x1U << 11)
1221 #define GPIO_ODR_ODR12 (0x1U << 12)
1222 #define GPIO_ODR_ODR13 (0x1U << 13)
1223 #define GPIO_ODR_ODR14 (0x1U << 14)
1224 #define GPIO_ODR_ODR15 (0x1U << 15)
1226 /******************************** Bit definition for GPIO_BSRR register ******************************/
1227 #define GPIO_BSRR_BS0 (0x1U << 0)
1228 #define GPIO_BSRR_BS1 (0x1U << 1)
1229 #define GPIO_BSRR_BS2 (0x1U << 2)
1230 #define GPIO_BSRR_BS3 (0x1U << 3)
1231 #define GPIO_BSRR_BS4 (0x1U << 4)
1232 #define GPIO_BSRR_BS5 (0x1U << 5)
1233 #define GPIO_BSRR_BS6 (0x1U << 6)
1234 #define GPIO_BSRR_BS7 (0x1U << 7)
1235 #define GPIO_BSRR_BS8 (0x1U << 8)
1236 #define GPIO_BSRR_BS9 (0x1U << 9)
1237 #define GPIO_BSRR_BS10 (0x1U << 10)
1238 #define GPIO_BSRR_BS11 (0x1U << 11)
1239 #define GPIO_BSRR_BS12 (0x1U << 12)
1240 #define GPIO_BSRR_BS13 (0x1U << 13)
1241 #define GPIO_BSRR_BS14 (0x1U << 14)
1242 #define GPIO_BSRR_BS15 (0x1U << 15)
1244 #define GPIO_BSRR_BR0 (0x1U << 16)
1245 #define GPIO_BSRR_BR1 (0x1U << 17)
1246 #define GPIO_BSRR_BR2 (0x1U << 18)
1247 #define GPIO_BSRR_BR3 (0x1U << 19)
1248 #define GPIO_BSRR_BR4 (0x1U << 20)
1249 #define GPIO_BSRR_BR5 (0x1U << 21)
1250 #define GPIO_BSRR_BR6 (0x1U << 22)
1251 #define GPIO_BSRR_BR7 (0x1U << 23)
1252 #define GPIO_BSRR_BR8 (0x1U << 24)
1253 #define GPIO_BSRR_BR9 (0x1U << 25)
1254 #define GPIO_BSRR_BR10 (0x1U << 26)
1255 #define GPIO_BSRR_BR11 (0x1U << 27)
1256 #define GPIO_BSRR_BR12 (0x1U << 28)
1257 #define GPIO_BSRR_BR13 (0x1U << 29)
1258 #define GPIO_BSRR_BR14 (0x1U << 30)
1259 #define GPIO_BSRR_BR15 (0x1U << 31)
1261 /******************************** Bit definition for GPIO_LCKR register *******************************/
1262 #define GPIO_LCKR_LCK0 (0x1U << 0)
1263 #define GPIO_LCKR_LCK1 (0x1U << 1)
1264 #define GPIO_LCKR_LCK2 (0x1U << 2)
1265 #define GPIO_LCKR_LCK3 (0x1U << 3)
1266 #define GPIO_LCKR_LCK4 (0x1U << 4)
1267 #define GPIO_LCKR_LCK5 (0x1U << 5)
1268 #define GPIO_LCKR_LCK6 (0x1U << 6)
1269 #define GPIO_LCKR_LCK7 (0x1U << 7)
1270 #define GPIO_LCKR_LCK8 (0x1U << 8)
1271 #define GPIO_LCKR_LCK9 (0x1U << 9)
1272 #define GPIO_LCKR_LCK10 (0x1U << 10)
1273 #define GPIO_LCKR_LCK11 (0x1U << 11)
1274 #define GPIO_LCKR_LCK12 (0x1U << 12)
1275 #define GPIO_LCKR_LCK13 (0x1U << 13)
1276 #define GPIO_LCKR_LCK14 (0x1U << 14)
1277 #define GPIO_LCKR_LCK15 (0x1U << 15)
1278 #define GPIO_LCKR_LCKK (0x1U << 16)
1280 /******************************** Bit definition for GPIO_AFRL register *******************************/
1281 #define GPIO_AFRL_AFR0_Pos (0U)
1282 #define GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos)
1283 #define GPIO_AFRL_AFR1_Pos (4U)
1284 #define GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos)
1285 #define GPIO_AFRL_AFR2_Pos (8U)
1286 #define GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos)
1287 #define GPIO_AFRL_AFR3_Pos (12U)
1288 #define GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos)
1289 #define GPIO_AFRL_AFR4_Pos (16U)
1290 #define GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos)
1291 #define GPIO_AFRL_AFR5_Pos (20U)
1292 #define GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos)
1293 #define GPIO_AFRL_AFR6_Pos (24U)
1294 #define GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos)
1295 #define GPIO_AFRL_AFR7_Pos (28U)
1296 #define GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos)
1297 
1298 /******************************** Bit definition for GPIO_AFRH register *******************************/
1299 #define GPIO_AFRH_AFR8_Pos (0U)
1300 #define GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos)
1301 #define GPIO_AFRH_AFR9_Pos (4U)
1302 #define GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos)
1303 #define GPIO_AFRH_AFR10_Pos (8U)
1304 #define GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos)
1305 #define GPIO_AFRH_AFR11_Pos (12U)
1306 #define GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos)
1307 #define GPIO_AFRH_AFR12_Pos (16U)
1308 #define GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos)
1309 #define GPIO_AFRH_AFR13_Pos (20U)
1310 #define GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos)
1311 #define GPIO_AFRH_AFR14_Pos (24U)
1312 #define GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos)
1313 #define GPIO_AFRH_AFR15_Pos (28U)
1314 #define GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos)
1315 
1316 /******************************** Bit definition for GPIO_SMIT register *******************************/
1317 #define GPIO_SMIT_SMIT0 (0x1U << 0)
1318 #define GPIO_SMIT_SMIT1 (0x1U << 1)
1319 #define GPIO_SMIT_SMIT2 (0x1U << 2)
1320 #define GPIO_SMIT_SMIT3 (0x1U << 3)
1321 #define GPIO_SMIT_SMIT4 (0x1U << 4)
1322 #define GPIO_SMIT_SMIT5 (0x1U << 5)
1323 #define GPIO_SMIT_SMIT6 (0x1U << 6)
1324 #define GPIO_SMIT_SMIT7 (0x1U << 7)
1325 #define GPIO_SMIT_SMIT8 (0x1U << 8)
1326 #define GPIO_SMIT_SMIT9 (0x1U << 9)
1327 #define GPIO_SMIT_SMIT10 (0x1U << 10)
1328 #define GPIO_SMIT_SMIT11 (0x1U << 11)
1329 #define GPIO_SMIT_SMIT12 (0x1U << 12)
1330 #define GPIO_SMIT_SMIT13 (0x1U << 13)
1331 #define GPIO_SMIT_SMIT14 (0x1U << 14)
1332 #define GPIO_SMIT_SMIT15 (0x1U << 15)
1333 
1334 /******************************** Bit definition for GPIO_CURRENT register *******************************/
1335 #define GPIO_CURRENT_CURRENT0_Pos (0U)
1336 #define GPIO_CURRENT_CURRENT0_Msk (0x3U << GPIO_CURRENT_CURRENT0_Pos)
1337 #define GPIO_CURRENT_CURRENT1_Pos (2U)
1338 #define GPIO_CURRENT_CURRENT1_Msk (0x3U << GPIO_CURRENT_CURRENT1_Pos)
1339 #define GPIO_CURRENT_CURRENT2_Pos (4U)
1340 #define GPIO_CURRENT_CURRENT2_Msk (0x3U << GPIO_CURRENT_CURRENT2_Pos)
1341 #define GPIO_CURRENT_CURRENT3_Pos (6U)
1342 #define GPIO_CURRENT_CURRENT3_Msk (0x3U << GPIO_CURRENT_CURRENT3_Pos)
1343 #define GPIO_CURRENT_CURRENT4_Pos (8U)
1344 #define GPIO_CURRENT_CURRENT4_Msk (0x3U << GPIO_CURRENT_CURRENT4_Pos)
1345 #define GPIO_CURRENT_CURRENT5_Pos (10U)
1346 #define GPIO_CURRENT_CURRENT5_Msk (0x3U << GPIO_CURRENT_CURRENT5_Pos)
1347 #define GPIO_CURRENT_CURRENT6_Pos (12U)
1348 #define GPIO_CURRENT_CURRENT6_Msk (0x3U << GPIO_CURRENT_CURRENT6_Pos)
1349 #define GPIO_CURRENT_CURRENT7_Pos (14U)
1350 #define GPIO_CURRENT_CURRENT7_Msk (0x3U << GPIO_CURRENT_CURRENT7_Pos)
1351 #define GPIO_CURRENT_CURRENT8_Pos (16U)
1352 #define GPIO_CURRENT_CURRENT8_Msk (0x3U << GPIO_CURRENT_CURRENT8_Pos)
1353 #define GPIO_CURRENT_CURRENT9_Pos (18U)
1354 #define GPIO_CURRENT_CURRENT9_Msk (0x3U << GPIO_CURRENT_CURRENT9_Pos)
1355 #define GPIO_CURRENT_CURRENT10_Pos (20U)
1356 #define GPIO_CURRENT_CURRENT10_Msk (0x3U << GPIO_CURRENT_CURRENT10_Pos)
1357 #define GPIO_CURRENT_CURRENT11_Pos (22U)
1358 #define GPIO_CURRENT_CURRENT11_Msk (0x3U << GPIO_CURRENT_CURRENT11_Pos)
1359 #define GPIO_CURRENT_CURRENT12_Pos (24U)
1360 #define GPIO_CURRENT_CURRENT12_Msk (0x3U << GPIO_CURRENT_CURRENT12_Pos)
1361 #define GPIO_CURRENT_CURRENT13_Pos (26U)
1362 #define GPIO_CURRENT_CURRENT13_Msk (0x3U << GPIO_CURRENT_CURRENT13_Pos)
1363 #define GPIO_CURRENT_CURRENT14_Pos (28U)
1364 #define GPIO_CURRENT_CURRENT14_Msk (0x3U << GPIO_CURRENT_CURRENT14_Pos)
1365 #define GPIO_CURRENT_CURRENT15_Pos (30U)
1366 #define GPIO_CURRENT_CURRENT15_Msk (0x3U << GPIO_CURRENT_CURRENT15_Pos)
1367 
1368 /******************************** Bit definition for GPIO_CFGMSK register *******************************/
1369 #define GPIO_CFGMSK_CFGMSK0 (0x1U << 0)
1370 #define GPIO_CFGMSK_CFGMSK1 (0x1U << 1)
1371 #define GPIO_CFGMSK_CFGMSK2 (0x1U << 2)
1372 #define GPIO_CFGMSK_CFGMSK3 (0x1U << 3)
1373 #define GPIO_CFGMSK_CFGMSK4 (0x1U << 4)
1374 #define GPIO_CFGMSK_CFGMSK5 (0x1U << 5)
1375 #define GPIO_CFGMSK_CFGMSK6 (0x1U << 6)
1376 #define GPIO_CFGMSK_CFGMSK7 (0x1U << 7)
1377 #define GPIO_CFGMSK_CFGMSK8 (0x1U << 8)
1378 #define GPIO_CFGMSK_CFGMSK9 (0x1U << 9)
1379 #define GPIO_CFGMSK_CFGMSK10 (0x1U << 10)
1380 #define GPIO_CFGMSK_CFGMSK11 (0x1U << 11)
1381 #define GPIO_CFGMSK_CFGMSK12 (0x1U << 12)
1382 #define GPIO_CFGMSK_CFGMSK13 (0x1U << 13)
1383 #define GPIO_CFGMSK_CFGMSK14 (0x1U << 14)
1384 #define GPIO_CFGMSK_CFGMSK15 (0x1U << 15)
1385 
1386 
1387 
1388 
1389 /*------------------------------------------------------------------------------------------------------*/
1390 /*--- Universal Asyncronous Receiver / Transmitter (UART) ---*/
1391 /*------------------------------------------------------------------------------------------------------*/
1392 /******************************** Bit definition for UART_IER register ********************************/
1393 #define UART_IER_RDAIE (0x1U << 0)
1394 #define UART_IER_THREIE (0x1U << 1)
1395 #define UART_IER_RLSIE (0x1U << 2)
1396 #define UART_IER_MSIE (0x1U << 3)
1397 #define UART_IER_LSRCLRMD (0x1U << 4)
1398 #define UART_IER_PTIME (0x1U << 7)
1400 /******************************** Bit definition for UART_IIR register ********************************/
1401 #define UART_IIR_INTID_Msk (0xFU)
1402 #define UART_IIR_INTID_MSI (0x0U)
1403 #define UART_IIR_INTID_NONE (0x1U)
1404 #define UART_IIR_INTID_THRE (0x2U)
1405 #define UART_IIR_INTID_RDA (0x4U)
1406 #define UART_IIR_INTID_RLS (0x6U)
1407 #define UART_IIR_INTID_BUSY (0x7U)
1408 #define UART_IIR_INTID_CTI (0xCU)
1410 #define UART_IIR_FIFOSE_Pos (6U)
1411 #define UART_IIR_FIFOSE_Msk (0x3U << UART_IIR_FIFOSE_Pos)
1412 
1413 /******************************** Bit definition for UART_FCR register ********************************/
1414 #define UART_FCR_FIFOE (0x1U << 0)
1415 #define UART_FCR_RFIFOR (0x1U << 1)
1416 #define UART_FCR_XFIFOR (0x1U << 2)
1418 /* This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. */
1419 #define UART_FCR_TET_0 (0x0U << 4)
1420 #define UART_FCR_TET_2 (0x1U << 4)
1421 #define UART_FCR_TET_4 (0x2U << 4)
1422 #define UART_FCR_TET_8 (0x3U << 4)
1424 /* This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. */
1425 #define UART_FCR_RT_1 (0x0U << 6)
1426 #define UART_FCR_RT_4 (0x1U << 6)
1427 #define UART_FCR_RT_8 (0x2U << 6)
1428 #define UART_FCR_RT_14 (0x3U << 6)
1431 /******************************** Bit definition for UART_LCR register ********************************/
1432 #define UART_LCR_WLS_Msk (0x3U << 0)
1433 #define UART_LCR_WLS_5BIT (0x0U << 0)
1434 #define UART_LCR_WLS_6BIT (0x1U << 0)
1435 #define UART_LCR_WLS_7BIT (0x2U << 0)
1436 #define UART_LCR_WLS_8BIT (0x3U << 0)
1438 #define UART_LCR_SBS_Msk (0x1U << 2)
1439 #define UART_LCR_SBS_1BIT (0x0U << 2)
1440 #define UART_LCR_SBS_2BIT (0x1U << 2)
1442 // #define UART_LCR_PE (0x1U << 3)
1444 // #define UART_LCR_PS_Msk (0x3U << 4)
1445 // #define UART_LCR_PS_ODD (0x0U << 4)
1446 // #define UART_LCR_PS_EVEN (0x1U << 4)
1447 // #define UART_LCR_PS_MARK (0x2U << 4)
1448 // #define UART_LCR_PS_SPACE (0x3U << 4)
1450 #define UART_LCR_PARITY_Msk (0x7U << 3)
1451 #define UART_LCR_PARITY_NONE (0x0U << 3)
1452 #define UART_LCR_PARITY_ODD (0x1U << 3)
1453 #define UART_LCR_PARITY_EVEN (0x3U << 3)
1454 #define UART_LCR_PARITY_MARK (0x5U << 3)
1455 #define UART_LCR_PARITY_SPACE (0x7U << 3)
1458 #define UART_LCR_BC (0x1U << 6)
1459 #define UART_LCR_DLAB (0x1U << 7)
1462 /******************************** Bit definition for UART_MCR register ********************************/
1463 #define UART_MCR_RTS (0x1U << 1)
1464 #define UART_MCR_LB (0x1U << 4)
1465 #define UART_MCR_AFCE (0x1U << 5)
1466 #define UART_MCR_SIRE (0x1U << 6)
1468 /******************************** Bit definition for UART_LSR register ********************************/
1469 #define UART_LSR_DR (0x1U << 0)
1470 #define UART_LSR_OE (0x1U << 1)
1471 #define UART_LSR_PE (0x1U << 2)
1472 #define UART_LSR_FE (0x1U << 3)
1473 #define UART_LSR_BI (0x1U << 4)
1474 #define UART_LSR_THRE (0x1U << 5)
1475 #define UART_LSR_TEMT (0x1U << 6)
1476 #define UART_LSR_RFE (0x1U << 7)
1477 #define UART_LSR_ADDR_RCVD (0x1U << 8)
1479 /******************************** Bit definition for UART_MSR register ********************************/
1480 #define UART_MSR_DCTS (0x1U << 0)
1481 #define UART_MSR_CTS (0x1U << 4)
1483 /******************************** Bit definition for UART_USR register ********************************/
1484 #define UART_USR_BUSY (0x1U << 0)
1485 #define UART_USR_TFNF (0x1U << 1)
1486 #define UART_USR_TFE (0x1U << 2)
1487 #define UART_USR_RFNE (0x1U << 3)
1488 #define UART_USR_RFF (0x1U << 4)
1490 /******************************** Bit definition for UART_TFL register ********************************/
1491 /******************************** Bit definition for UART_RFL register ********************************/
1492 
1493 /******************************** Bit definition for UART_SRR register ********************************/
1494 #define UART_SRR_UR (0x1U << 0)
1495 #define UART_SRR_RFR (0x1U << 1)
1496 #define UART_SRR_XFR (0x1U << 2)
1498 /******************************** Bit definition for UART_SRTS register ********************************/
1499 #define UART_SRTS_SRTS (0x1U << 0)
1501 /******************************** Bit definition for UART_SBCR register *******************************/
1502 #define UART_SBCR_SBCB (0x1U << 0)
1504 /******************************** Bit definition for UART_SDMAM register ******************************/
1505 #define UART_SDMAM_SDMAM (0x1U << 0)
1507 /******************************** Bit definition for UART_SFE register ********************************/
1508 #define UART_SFE_SFE (0x1U << 0)
1510 /******************************** Bit definition for UART_SRT register ********************************/
1511 /* Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR[7:6]). */
1512 #define UART_SRT_LEV0 (0x0U)
1513 #define UART_SRT_LEV1 (0x1U)
1514 #define UART_SRT_LEV2 (0x2U)
1515 #define UART_SRT_LEV3 (0x3U)
1517 /******************************** Bit definition for UART_STET register *******************************/
1518 /* Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR[5:4]). */
1519 #define UART_STET_LEV0 (0x0U)
1520 #define UART_STET_LEV1 (0x1U)
1521 #define UART_STET_LEV2 (0x2U)
1522 #define UART_STET_LEV3 (0x3U)
1524 /******************************** Bit definition for UART_HTX register ********************************/
1525 #define UART_HTX_HTX (0x1U << 0)
1527 /******************************** Bit definition for UART_DMASA register ******************************/
1528 #define UART_DMASA (0x1U << 0)
1530 /******************************** Bit definition for UART_EXTLCR register ********************************/
1531 #define UART_EXTLCR_WLS_E (0x1U << 0)
1532 #define UART_EXTLCR_ADDR_MATCH (0x1U << 1)
1533 #define UART_EXTLCR_SEND_ADDR (0x1U << 2)
1534 #define UART_EXTLCR_TRANSMIT_MODE (0x1U << 3)
1539 /*------------------------------------------------------------------------------------------------------*/
1540 /*--- Cyclic Redundancy Check (CRC) ---*/
1541 /*------------------------------------------------------------------------------------------------------*/
1542 /******************************** Bit definition for CRC_MODE register ********************************/
1543 #define CRC_MODE_CRC_POLY_Msk (0x3U << 0)
1544 #define CRC_MODE_CRC_POLY_CRC8 (0x0U << 0)
1545 #define CRC_MODE_CRC_POLY_CCITT (0x1U << 0)
1546 #define CRC_MODE_CRC_POLY_CRC16 (0x2U << 0)
1547 #define CRC_MODE_CRC_POLY_CRC32 (0x3U << 0)
1549 #define CRC_MODE_BIT_RVS_WR (0x1U << 2)
1550 #define CRC_MODE_CMPL_WR (0x1U << 3)
1551 #define CRC_MODE_BIT_RVS_SUM (0x1U << 4)
1552 #define CRC_MODE_CMPL_SUM (0x1U << 5)
1553 #define CRC_MODE_SEED_OP (0x1U << 6)
1554 #define CRC_MODE_SEED_SET (0x1U << 7)
1558 /*------------------------------------------------------------------------------------------------------*/
1559 /*--- Special Function Macro (SFM) ---*/
1560 /*------------------------------------------------------------------------------------------------------*/
1561 /******************************** Bit definition for SFM_CTRL register ********************************/
1562 #define SFM_CTRL_EXP_RATE_Msk (0x7U << 0)
1563 #define SFM_CTRL_EXP_RATE_1 (0x0U << 0)
1564 #define SFM_CTRL_EXP_RATE_2 (0x1U << 0)
1565 #define SFM_CTRL_EXP_RATE_3 (0x2U << 0)
1566 #define SFM_CTRL_EXP_RATE_4 (0x3U << 0)
1567 #define SFM_CTRL_EXP_RATE_5 (0x4U << 0)
1568 #define SFM_CTRL_EXP_RATE_6 (0x5U << 0)
1569 #define SFM_CTRL_EXP_RATE_7 (0x6U << 0)
1570 #define SFM_CTRL_EXP_RATE_8 (0x7U << 0)
1572 #define SFM_CTRL_EXP_EN (0x1U << 3)
1574 /******************************** Bit definition for SFM_USBPSDCSR register ********************************/
1575 #define SFM_USBPSDCSR_SE0F (0x1U << 0)
1576 #define SFM_USBPSDCSR_JSTATF (0x1U << 1)
1577 #define SFM_USBPSDCSR_KSTATF (0x1U << 2)
1578 #define SFM_USBPSDCSR_SE1F (0x1U << 3)
1580 #define SFM_USBPSDCSR_SE0EN (0x1U << 8)
1581 #define SFM_USBPSDCSR_JSTATEN (0x1U << 9)
1582 #define SFM_USBPSDCSR_KSTATEN (0x1U << 10)
1583 #define SFM_USBPSDCSR_SE1EN (0x1U << 11)
1587 /*------------------------------------------------------------------------------------------------------*/
1588 /*--- Direct Memory Access Controller (DMAC) ---*/
1589 /*------------------------------------------------------------------------------------------------------*/
1590 /******************************* Bit definition for DMAC_CTLLx register *******************************/
1591 #define DMAC_CTLL_INT_EN (0x1U << 0)
1593 #define DMAC_CTLL_DST_TR_WIDTH_Msk (0x7U << 1)
1594 #define DMAC_CTLL_DST_TR_WIDTH_8 (0x0U << 1)
1595 #define DMAC_CTLL_DST_TR_WIDTH_16 (0x1U << 1)
1596 #define DMAC_CTLL_DST_TR_WIDTH_32 (0x2U << 1)
1598 #define DMAC_CTLL_SRC_TR_WIDTH_Msk (0x7U << 4)
1599 #define DMAC_CTLL_SRC_TR_WIDTH_8 (0x0U << 4)
1600 #define DMAC_CTLL_SRC_TR_WIDTH_16 (0x1U << 4)
1601 #define DMAC_CTLL_SRC_TR_WIDTH_32 (0x2U << 4)
1603 #define DMAC_CTLL_DINC_Msk (0x3U << 7)
1604 #define DMAC_CTLL_DINC_INC (0x0U << 7)
1605 #define DMAC_CTLL_DINC_DEC (0x1U << 7)
1606 #define DMAC_CTLL_DINC_NO (0x2U << 7)
1608 #define DMAC_CTLL_SINC_Msk (0x3U << 9)
1609 #define DMAC_CTLL_SINC_INC (0x0U << 9)
1610 #define DMAC_CTLL_SINC_DEC (0x1U << 9)
1611 #define DMAC_CTLL_SINC_NO (0x2U << 9)
1613 #define DMAC_CTLL_DEST_MSIZE_Msk (0x7U << 11)
1614 #define DMAC_CTLL_DEST_MSIZE_1 (0x0U << 11)
1615 #define DMAC_CTLL_DEST_MSIZE_4 (0x1U << 11)
1616 #define DMAC_CTLL_DEST_MSIZE_8 (0x2U << 11)
1617 #define DMAC_CTLL_DEST_MSIZE_16 (0x3U << 11)
1618 #define DMAC_CTLL_DEST_MSIZE_32 (0x4U << 11)
1619 #define DMAC_CTLL_DEST_MSIZE_64 (0x5U << 11)
1620 #define DMAC_CTLL_DEST_MSIZE_128 (0x6U << 11)
1621 #define DMAC_CTLL_DEST_MSIZE_256 (0x7U << 11)
1623 #define DMAC_CTLL_SRC_MSIZE_Msk (0x7U << 14)
1624 #define DMAC_CTLL_SRC_MSIZE_1 (0x0U << 14)
1625 #define DMAC_CTLL_SRC_MSIZE_4 (0x1U << 14)
1626 #define DMAC_CTLL_SRC_MSIZE_8 (0x2U << 14)
1627 #define DMAC_CTLL_SRC_MSIZE_16 (0x3U << 14)
1628 #define DMAC_CTLL_SRC_MSIZE_32 (0x4U << 14)
1629 #define DMAC_CTLL_SRC_MSIZE_64 (0x5U << 14)
1630 #define DMAC_CTLL_SRC_MSIZE_128 (0x6U << 14)
1631 #define DMAC_CTLL_SRC_MSIZE_256 (0x7U << 14)
1633 #define DMAC_CTLL_SRC_GATHER_EN (0x1U << 17)
1634 #define DMAC_CTLL_DST_SCATTER_EN (0x1U << 18)
1636 #define DMAC_CTLL_TT_FC_Msk (0x7U << 20)
1637 #define DMAC_CTLL_TT_FC_M2M_DMAC (0x0U << 20)
1638 #define DMAC_CTLL_TT_FC_M2P_DMAC (0x1U << 20)
1639 #define DMAC_CTLL_TT_FC_P2M_DMAC (0x2U << 20)
1640 #define DMAC_CTLL_TT_FC_P2P_DMAC (0x3U << 20)
1641 #define DMAC_CTLL_TT_FC_P2M_PERIPH (0x4U << 20)
1642 #define DMAC_CTLL_TT_FC_P2P_SRC_PERIPH (0x5U << 20)
1643 #define DMAC_CTLL_TT_FC_M2P_PERIPH (0x6U << 20)
1644 #define DMAC_CTLL_TT_FC_P2P_DST_PERIPH (0x7U << 20)
1646 #define DMAC_CTLL_LLP_DST_EN (0x1U << 27)
1647 #define DMAC_CTLL_LLP_SRC_EN (0x1U << 28)
1649 /******************************* Bit definition for DMAC_CTLHx register *******************************/
1650 #define DMAC_CTLH_BLOCK_TS_Msk (0xFFFU)
1651 #define DMAC_CTLH_DONE (0x1U << 12)
1656 /******************************* Bit definition for DMAC_CFGLx register *******************************/
1657 #define DMAC_CFGL_CH_PRIOR_Msk (0x7U << 5)
1658 #define DMAC_CFGL_CH_SUSP (0x1U << 8)
1659 #define DMAC_CFGL_FIFO_EMPTY (0x1U << 9)
1660 #define DMAC_CFGL_HS_SEL_DST (0x1U << 10)
1661 #define DMAC_CFGL_HS_SEL_SRC (0x1U << 11)
1663 #define DMAC_CFGL_DST_HS_POL (0x1U << 18)
1664 #define DMAC_CFGL_SRC_HS_POL (0x1U << 19)
1666 #define DMAC_CFGL_RELOAD_SRC (0x1U << 30)
1667 #define DMAC_CFGL_RELOAD_DST (0x1U << 31)
1669 /******************************* Bit definition for DMAC_CFGHx register *******************************/
1670 
1671 #define DMAC_CFGH_FIFO_MODE (0x1U << 1)
1672 #define DMAC_CFGH_DS_UPD_EN (0x1U << 5)
1673 #define DMAC_CFGH_SS_UPD_EN (0x1U << 6)
1675 #define DMAC_CFGH_SRC_PER_Msk (0xFU << 7)
1676 #define DMAC_CFGH_DEST_PER_Msk (0xFU << 11)
1680 /*------------------------------------------------------------------------------------------------------*/
1681 /*--- Inter-Integrated Circuit (I2C) ---*/
1682 /*------------------------------------------------------------------------------------------------------*/
1683 /****************************** Bit definition for I2C_CON register *******************************/
1684 #define I2C_CON_MASTER_MODE (0x1U << 0)
1686 #define I2C_CON_SPEED_Msk (0x3U << 1)
1687 #define I2C_CON_SPEED_STANDARD (0x1U << 1)
1688 #define I2C_CON_SPEED_FAST (0x2U << 1)
1689 #define I2C_CON_SPEED_HIGH (0x3U << 1)
1691 #define I2C_CON_10BITADDR_SLAVE (0x1U << 3)
1692 #define I2C_CON_10BITADDR_MASTER (0x1U << 4)
1693 #define I2C_CON_RESTART_EN (0x1U << 5)
1694 #define I2C_CON_SLAVE_DISABLE (0x1U << 6)
1695 #define I2C_CON_STOP_DET_IFADDRESSED (0x1U << 7)
1696 #define I2C_CON_TX_EMPTY_CTRL (0x1U << 8)
1697 #define I2C_CON_RX_FIFO_FULL_HLD_CTRL (0x1U << 9)
1698 #define I2C_CON_STOP_DET_IF_MASTER_ACTIVE (0x1U << 10)
1699 #define I2C_CON_BUS_CLEAR_FEATURE_CTRL (0x1U << 11)
1700 #define I2C_CON_OPTIONAL_SAR_CTRL (0x1U << 16)
1701 #define I2C_CON_SMBUS_SLAVE_QUICK_EN (0x1U << 17)
1702 #define I2C_CON_SMBUS_ARP_EN (0x1U << 18)
1703 #define I2C_CON_SMBUS_PERSISTANT_SLV_ADDR_EN (0x1U << 19)
1705 /****************************** Bit definition for I2C_TAR register *******************************/
1706 #define I2C_TAR_TAR_Msk (0x3FFU)
1707 #define I2C_TAR_GC_OR_START (0x1U << 10)
1708 #define I2C_TAR_SPECIAL (0x1U << 11)
1709 #define I2C_TAR_10BITADDR_MASTER (0x1U << 12)
1710 #define I2C_TAR_DEVICE_ID (0x1U << 13)
1711 #define I2C_TAR_SMBUS_QUICK_CMD (0x1U << 16)
1713 /****************************** Bit definition for I2C_SAR register *******************************/
1714 /****************************** Bit definition for I2C_HS_MADDR register *******************************/
1715 
1716 /****************************** Bit definition for I2C_DATA_CMD register *******************************/
1717 #define I2C_DATA_CMD_DAT_Msk (0xFFU)
1719 #define I2C_DATA_CMD_READ (0x1U << 8)
1720 #define I2C_DATA_CMD_STOP (0x1U << 9)
1721 #define I2C_DATA_CMD_RESTART (0x1U << 10)
1722 #define I2C_DATA_CMD_FIRST_DATA_BYTE (0x1U << 11)
1724 /****************************** Bit definition for I2C_SS_SCL_HCNT register *******************************/
1725 /****************************** Bit definition for I2C_SS_SCL_LCNT register *******************************/
1726 /****************************** Bit definition for I2C_FS_SCL_HCNT register *******************************/
1727 /****************************** Bit definition for I2C_FS_SCL_LCNT register *******************************/
1728 /****************************** Bit definition for I2C_HS_SCL_HCNT register *******************************/
1729 /****************************** Bit definition for I2C_HS_SCL_LCNT register *******************************/
1730 
1731 /****************************** Bit definition for I2C_INTR_STAT register *******************************/
1732 /****************************** Bit definition for I2C_INTR_MASK register *******************************/
1733 /****************************** Bit definition for I2C_RAW_INTR_STAT register *******************************/
1734 #define I2C_INTR_RX_UNDER (0x1U << 0)
1735 #define I2C_INTR_RX_OVER (0x1U << 1)
1736 #define I2C_INTR_RX_FULL (0x1U << 2)
1737 #define I2C_INTR_TX_OVER (0x1U << 3)
1738 #define I2C_INTR_TX_EMPTY (0x1U << 4)
1739 #define I2C_INTR_RD_REQ (0x1U << 5)
1740 #define I2C_INTR_TX_ABRT (0x1U << 6)
1741 #define I2C_INTR_RX_DONE (0x1U << 7)
1742 #define I2C_INTR_ACTIVITY (0x1U << 8)
1743 #define I2C_INTR_STOP_DET (0x1U << 9)
1744 #define I2C_INTR_START_DET (0x1U << 10)
1745 #define I2C_INTR_GEN_CALL (0x1U << 11)
1746 #define I2C_INTR_RESTART_DET (0x1U << 12)
1747 #define I2C_INTR_SCL_STUCK_AT_LOW (0x1U << 14)
1750 /****************************** Bit definition for I2C_RX_TL register *******************************/
1751 /****************************** Bit definition for I2C_TX_TL register *******************************/
1752 /****************************** Bit definition for I2C_CLR_INTR register *******************************/
1753 /****************************** Bit definition for I2C_CLR_RX_UNDERT register *******************************/
1754 /****************************** Bit definition for I2C_CLR_RX_OVER register *******************************/
1755 /****************************** Bit definition for I2C_CLR_TX_OVER register *******************************/
1756 /****************************** Bit definition for I2C_CLR_RD_REQ register *******************************/
1757 /****************************** Bit definition for I2C_CLR_TX_ABRT register *******************************/
1758 /****************************** Bit definition for I2C_CLR_RX_DONE register *******************************/
1759 /****************************** Bit definition for I2C_CLR_ACTIVITY register *******************************/
1760 /****************************** Bit definition for I2C_CLR_STOP_DET register *******************************/
1761 /****************************** Bit definition for I2C_CLR_START_DET register *******************************/
1762 /****************************** Bit definition for I2C_CLR_GEN_CALL register *******************************/
1763 
1764 /****************************** Bit definition for I2C_ENABLE register *******************************/
1765 #define I2C_ENABLE_ENABLE (0x1U << 0)
1766 #define I2C_ENABLE_ABORT (0x1U << 1)
1767 #define I2C_ENABLE_TX_CMD_BLOCK (0x1U << 2)
1768 #define I2C_ENABLE_SDA_STUCK_RECOVERY_ENA (0x1U << 3)
1769 #define I2C_ENABLE_SMBUS_CLK_RESET (0x1U << 16)
1770 #define I2C_ENABLE_SMBUS_SUSPEND_EN (0x1U << 17)
1771 #define I2C_ENABLE_SMBUS_ALERT_EN (0x1U << 18)
1773 /****************************** Bit definition for I2C_STATUS register *******************************/
1774 #define I2C_STATUS_ACTIVITY (0x1U << 0)
1775 #define I2C_STATUS_TFNF (0x1U << 1)
1776 #define I2C_STATUS_TFE (0x1U << 2)
1777 #define I2C_STATUS_RFNE (0x1U << 3)
1778 #define I2C_STATUS_RFF (0x1U << 4)
1779 #define I2C_STATUS_MST_ACTIVITY (0x1U << 5)
1780 #define I2C_STATUS_SLV_ACTIVITY (0x1U << 6)
1781 #define I2C_STATUS_MST_HOLD_TX_FIFO_EMPTY (0x1U << 7)
1782 #define I2C_STATUS_MST_HOLD_RX_FIFO_FULL (0x1U << 8)
1783 #define I2C_STATUS_SLV_HOLD_TX_FIFO_EMPTY (0x1U << 9)
1784 #define I2C_STATUS_SLV_HOLD_RX_FIFO_FULL (0x1U << 10)
1785 #define I2C_STATUS_SDA_STUCK_NOT_RECOVERED (0x1U << 11)
1786 #define I2C_STATUS_SMBUS_QUICK_CMD_BIT (0x1U << 16)
1787 #define I2C_STATUS_SMBUS_SLAVE_ADDR_VALID (0x1U << 17)
1788 #define I2C_STATUS_SMBUS_SLAVE_ADDR_RESOLVED (0x1U << 18)
1789 #define I2C_STATUS_SMBUS_SUSPEND_STATUS (0x1U << 19)
1790 #define I2C_STATUS_SMBUS_ALERT_STATUS (0x1U << 20)
1792 /****************************** Bit definition for I2C_TXFLR register *******************************/
1793 /****************************** Bit definition for I2C_RXFLR register *******************************/
1794 /****************************** Bit definition for I2C_SDA_HOLD register *******************************/
1795 
1796 /****************************** Bit definition for I2C_TX_ABRT_SOURCE *******************************/
1797 #define I2C_TX_ABRT_SOURCE_7B_ADDR_NOACK (0x1U << 0)
1798 #define I2C_TX_ABRT_SOURCE_10ADDR1_NOACK (0x1U << 1)
1799 #define I2C_TX_ABRT_SOURCE_10ADDR2_NOACK (0x1U << 2)
1800 #define I2C_TX_ABRT_SOURCE_TXDATA_NOACK (0x1U << 3)
1801 #define I2C_TX_ABRT_SOURCE_GCALL_NOACK (0x1U << 4)
1802 #define I2C_TX_ABRT_SOURCE_GCALL_READ (0x1U << 5)
1803 #define I2C_TX_ABRT_SOURCE_HS_ACKDET (0x1U << 6)
1804 #define I2C_TX_ABRT_SOURCE_SBYTE_ACKDET (0x1U << 7)
1805 #define I2C_TX_ABRT_SOURCE_HS_NORSTRT (0x1U << 8)
1806 #define I2C_TX_ABRT_SOURCE_SBYTE_NORSTRT (0x1U << 9)
1807 #define I2C_TX_ABRT_SOURCE_10B_RD_NORSTRT (0x1U << 10)
1808 #define I2C_TX_ABRT_SOURCE_MASTER_DIS (0x1U << 11)
1809 #define I2C_TX_ABRT_SOURCE_LOST (0x1U << 12)
1810 #define I2C_TX_ABRT_SOURCE_SLVFLUSH_TXFIFO (0x1U << 13)
1811 #define I2C_TX_ABRT_SOURCE_SLV_ARBLOST (0x1U << 14)
1812 #define I2C_TX_ABRT_SOURCE_SLVRD_INTX (0x1U << 15)
1813 #define I2C_TX_ABRT_SOURCE_USER_ABRT (0x1U << 16)
1814 #define I2C_TX_ABRT_SOURCE_SDA_STUCK_AT_LOW (0x1U << 17)
1815 #define I2C_TX_ABRT_SOURCE_DEVICE_NOACK (0x1U << 18)
1816 #define I2C_TX_ABRT_SOURCE_DEVICE_SLVADDR_NOACK (0x1U << 19)
1817 #define I2C_TX_ABRT_SOURCE_DEVICE_WRITE (0x1U << 20)
1819 #define I2C_TX_ABRT_SOURCE_TX_FLUSH_CNT_Msk (0xFF800000U)
1821 /****************************** Bit definition for I2C_SLV_DATA_NACK_ONLY register *******************************/
1822 #define I2C_SLV_DATA_NACK_ONLY_NACK (0x1U << 0)
1824 /****************************** Bit definition for I2C_DMA_CR register *******************************/
1825 #define I2C_DMA_CR_RDMAE (0x1U << 0)
1826 #define I2C_DMA_CR_TDMAE (0x1U << 1)
1828 /****************************** Bit definition for I2C_DMA_TDLR register *******************************/
1829 /****************************** Bit definition for I2C_DMA_RDLR register *******************************/
1830 /****************************** Bit definition for I2C_SDA_SETUP register *******************************/
1831 /****************************** Bit definition for I2C_ACK_GENERAL_CALL register *******************************/
1832 
1833 /****************************** Bit definition for I2C_ENABLE_STATUS register *******************************/
1834 #define I2C_ENABLE_STATUS_IC_EN (0x1U << 0)
1835 #define I2C_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY (0x1U << 1)
1836 #define I2C_ENABLE_STATUS_SLV_RX_DATA_LOST (0x1U << 2)
1838 /****************************** Bit definition for FS_SPKLEN register *******************************/
1839 /****************************** Bit definition for HS_SPKLEN register *******************************/
1840 /****************************** Bit definition for CLR_RESTART_DET register *******************************/
1841 /****************************** Bit definition for SCL_STUCK_AT_LOW_TIMEOUT register *******************************/
1842 /****************************** Bit definition for SDA_STUCK_AT_LOW_TIMEOUT register *******************************/
1843 /****************************** Bit definition for CLR_SCL_STUCK_DET register *******************************/
1844 /****************************** Bit definition for SMBUS_CLK_LOW_SEXT register *******************************/
1845 /****************************** Bit definition for SMBUS_CLK_LOW_MEXT register *******************************/
1846 /****************************** Bit definition for SMBUS_THIGH_MAX_IDLE_COUNT register *******************************/
1847 /****************************** Bit definition for SMBUS_INTR_STAT register *******************************/
1848 /****************************** Bit definition for SMBUS_INTR_MASK register *******************************/
1849 /****************************** Bit definition for SMBUS_RAW_INTR_STAT register *******************************/
1850 #define I2C_SMBUS_INTR_SLV_CLOCK_EXTND_TIMEOUT (0x1U << 0)
1851 #define I2C_SMBUS_INTR_MST_CLOCK_EXTND_TIMEOUT (0x1U << 1)
1852 #define I2C_SMBUS_INTR_QUICK_CMD_DET (0x1U << 2)
1853 #define I2C_SMBUS_INTR_HOST_NTFY_MST_DET (0x1U << 3)
1854 #define I2C_SMBUS_INTR_ARP_PREPARE_CMD_DET (0x1U << 4)
1855 #define I2C_SMBUS_INTR_ARP_RST_CMD_DET (0x1U << 5)
1856 #define I2C_SMBUS_INTR_ARP_GET_UDID_CMD_DET (0x1U << 6)
1857 #define I2C_SMBUS_INTR_ARP_ASSGN_ADDR_CMD_DET (0x1U << 7)
1858 #define I2C_SMBUS_INTR_SLV_RX_PEC_NACK (0x1U << 8)
1859 #define I2C_SMBUS_INTR_SMBUS_SUSPEND_DET (0x1U << 9)
1860 #define I2C_SMBUS_INTR_SMBUS_ALERT_DET (0x1U << 10)
1862 /****************************** Bit definition for CLR_SMBUS_INTR register *******************************/
1863 /****************************** Bit definition for OPTIONAL_SAR register *******************************/
1864 /****************************** Bit definition for SMBUS_UDID_LSB register *******************************/
1865 
1866 
1867 
1868 
1869 
1870 /*------------------------------------------------------------------------------------------------------*/
1871 /*--- Serial Peripheral Interface (SPI) ---*/
1872 /*------------------------------------------------------------------------------------------------------*/
1873 /****************************** Bit definition for SPI_CR0 register *******************************/
1874 #define SPI_CR0_DFS_Msk (0xFU << 0)
1875 #define SPI_CR0_DFS_4BITS (0x3U << 0)
1876 #define SPI_CR0_DFS_5BITS (0x4U << 0)
1877 #define SPI_CR0_DFS_6BITS (0x5U << 0)
1878 #define SPI_CR0_DFS_7BITS (0x6U << 0)
1879 #define SPI_CR0_DFS_8BITS (0x7U << 0)
1880 #define SPI_CR0_DFS_9BITS (0x8U << 0)
1881 #define SPI_CR0_DFS_10BITS (0x9U << 0)
1882 #define SPI_CR0_DFS_11BITS (0xAU << 0)
1883 #define SPI_CR0_DFS_12BITS (0xBU << 0)
1884 #define SPI_CR0_DFS_13BITS (0xCU << 0)
1885 #define SPI_CR0_DFS_14BITS (0xDU << 0)
1886 #define SPI_CR0_DFS_15BITS (0xEU << 0)
1887 #define SPI_CR0_DFS_16BITS (0xFU << 0)
1889 #define SPI_CR0_FRF_Msk (0x3U << 4)
1890 #define SPI_CR0_FRF_SPI (0x0U << 4)
1891 #define SPI_CR0_FRF_SSP (0x1U << 4)
1892 #define SPI_CR0_FRF_NS (0x2U << 4)
1894 #define SPI_CR0_CPHA (0x1U << 6)
1895 #define SPI_CR0_CPOL (0x1U << 7)
1897 #define SPI_CR0_TMOD_Msk (0x3U << 8)
1898 #define SPI_CR0_TMOD_TX_AND_RX (0x0U << 8)
1899 #define SPI_CR0_TMOD_TX_ONLY (0x1U << 8)
1900 #define SPI_CR0_TMOD_RX_ONLY (0x2U << 8)
1901 #define SPI_CR0_TMOD_EEPROM_READ (0x3U << 8)
1903 #define SPI_CR0_SLV_OE (0x1U << 10)
1904 #define SPI_CR0_SRL (0x1U << 11)
1906 #define SPI_CR0_CFS_Msk (0xFU << 12)
1907 #define SPI_CR0_CFS_01_BIT (0x0U << 12)
1908 #define SPI_CR0_CFS_02_BIT (0x1U << 12)
1909 #define SPI_CR0_CFS_03_BIT (0x2U << 12)
1910 #define SPI_CR0_CFS_04_BIT (0x3U << 12)
1911 #define SPI_CR0_CFS_05_BIT (0x4U << 12)
1912 #define SPI_CR0_CFS_06_BIT (0x5U << 12)
1913 #define SPI_CR0_CFS_07_BIT (0x6U << 12)
1914 #define SPI_CR0_CFS_08_BIT (0x7U << 12)
1915 #define SPI_CR0_CFS_09_BIT (0x8U << 12)
1916 #define SPI_CR0_CFS_10_BIT (0x9U << 12)
1917 #define SPI_CR0_CFS_11_BIT (0xAU << 12)
1918 #define SPI_CR0_CFS_12_BIT (0xBU << 12)
1919 #define SPI_CR0_CFS_13_BIT (0xCU << 12)
1920 #define SPI_CR0_CFS_14_BIT (0xDU << 12)
1921 #define SPI_CR0_CFS_15_BIT (0xEU << 12)
1922 #define SPI_CR0_CFS_16_BIT (0xFU << 12)
1924 #define SPI_CR0_SPI_MODE_Msk (0x3U << 21)
1925 #define SPI_CR0_SPI_MODE_STD (0x0U << 21)
1926 #define SPI_CR0_SPI_MODE_DUAL (0x1U << 21)
1927 #define SPI_CR0_SPI_MODE_QUAD (0x2U << 21)
1928 #define SPI_CR0_SPI_MODE_OCTAL (0x3U << 21)
1930 #define SPI_CR0_SSTE (0x1U << 24)
1932 /****************************** Bit definition for SPI_CR1 register *******************************/
1933 #define SPI_CR1_NDF_Msk (0xFFFFU)
1935 /****************************** Bit definition for SPI_SPIENR register *******************************/
1936 #define SPI_SPIENR_SPI_EN (0x1U << 0)
1938 /****************************** Bit definition for SPI_MWCR register *******************************/
1939 #define SPI_MWCR_MWMOD (0x1U << 0)
1940 #define SPI_MWCR_MDD (0x1U << 1)
1941 #define SPI_MWCR_MHS (0x1U << 2)
1943 /****************************** Bit definition for SPI_SER register *******************************/
1944 #define SPI_SER_Msk (0x7U << 0)
1945 #define SPI_SER_SE0 (0x1U << 0)
1946 #define SPI_SER_SE1 (0x1U << 1)
1947 #define SPI_SER_SE2 (0x1U << 2)
1949 /****************************** Bit definition for SPI_BAUDR register *******************************/
1950 #define SPI_BAUDR_SCKDV_Msk (0xFFFFU)
1952 /****************************** Bit definition for SPI_TXFTLR register *******************************/
1953 
1954 /****************************** Bit definition for SPI_RXFTLR register *******************************/
1955 
1956 /****************************** Bit definition for SPI_TXFLR register *******************************/
1957 
1958 /****************************** Bit definition for SPI_RXFLR register *******************************/
1959 
1960 /****************************** Bit definition for SPI_SR register *******************************/
1961 #define SPI_SR_BUSY (0x1U << 0)
1962 #define SPI_SR_TFNF (0x1U << 1)
1963 #define SPI_SR_TFE (0x1U << 2)
1964 #define SPI_SR_RFNE (0x1U << 3)
1965 #define SPI_SR_RFF (0x1U << 4)
1966 #define SPI_SR_TXERR (0x1U << 5)
1967 #define SPI_SR_DCOL (0x1U << 6)
1969 /****************************** Bit definition for SPI_IER register *******************************/
1970 #define SPI_IER_TXEIE (0x1U << 0)
1971 #define SPI_IER_TXOIE (0x1U << 1)
1972 #define SPI_IER_RXUIE (0x1U << 2)
1973 #define SPI_IER_RXOIE (0x1U << 3)
1974 #define SPI_IER_RXFIE (0x1U << 4)
1975 #define SPI_IER_MSTIE (0x1U << 5)
1977 /****************************** Bit definition for SPI_ISR register *******************************/
1978 #define SPI_ISR_TXEIS (0x1U << 0)
1979 #define SPI_ISR_TXOIS (0x1U << 1)
1980 #define SPI_ISR_RXUIS (0x1U << 2)
1981 #define SPI_ISR_RXOIS (0x1U << 3)
1982 #define SPI_ISR_RXFIS (0x1U << 4)
1983 #define SPI_ISR_MSTIS (0x1U << 5)
1985 /****************************** Bit definition for SPI_RISR register *******************************/
1986 #define SPI_RISR_TXEIR (0x1U << 0)
1987 #define SPI_RISR_TXOIR (0x1U << 1)
1988 #define SPI_RISR_RXUIR (0x1U << 2)
1989 #define SPI_RISR_RXOIR (0x1U << 3)
1990 #define SPI_RISR_RXFIR (0x1U << 4)
1991 #define SPI_RISR_MSTIR (0x1U << 5)
1994 /****************************** Bit definition for SPI_DMACR register *******************************/
1995 #define SPI_DMACR_RDMAE (0x1U << 0)
1996 #define SPI_DMACR_TDMAE (0x1U << 1)
1998 /****************************** Bit definition for SPI_DMATDLR register *******************************/
1999 
2000 /****************************** Bit definition for SPI_DMARDLR register *******************************/
2001 
2002 
2003 /****************************** Bit definition for SPI_ESPICR register ****************************/
2004 #define SPI_ESPICR_TRANST_Msk (0x3U << 0)
2006 #define SPI_ESPICR_ADDRL_Msk (0xFU << 2)
2007 #define SPI_ESPICR_ADDRL_0BIT (0x0U << 2)
2008 #define SPI_ESPICR_ADDRL_4BIT (0x1U << 2)
2009 #define SPI_ESPICR_ADDRL_8BIT (0x2U << 2)
2010 #define SPI_ESPICR_ADDRL_12BIT (0x3U << 2)
2011 #define SPI_ESPICR_ADDRL_16BIT (0x4U << 2)
2012 #define SPI_ESPICR_ADDRL_20BIT (0x5U << 2)
2013 #define SPI_ESPICR_ADDRL_24BIT (0x6U << 2)
2014 #define SPI_ESPICR_ADDRL_28BIT (0x7U << 2)
2015 #define SPI_ESPICR_ADDRL_32BIT (0x8U << 2)
2016 #define SPI_ESPICR_ADDRL_36BIT (0x9U << 2)
2017 #define SPI_ESPICR_ADDRL_40BIT (0xAU << 2)
2018 #define SPI_ESPICR_ADDRL_44BIT (0xBU << 2)
2019 #define SPI_ESPICR_ADDRL_48BIT (0xCU << 2)
2020 #define SPI_ESPICR_ADDRL_52BIT (0xDU << 2)
2021 #define SPI_ESPICR_ADDRL_56BIT (0xEU << 2)
2022 #define SPI_ESPICR_ADDRL_60BIT (0xFU << 2)
2024 #define SPI_ESPICR_INSTL_Msk (0x3U << 8)
2025 #define SPI_ESPICR_INSTL_0BIT (0x0U << 8)
2026 #define SPI_ESPICR_INSTL_4BIT (0x1U << 8)
2027 #define SPI_ESPICR_INSTL_8BIT (0x2U << 8)
2028 #define SPI_ESPICR_INSTL_16BIT (0x3U << 8)
2030 #define SPI_ESPICR_WCYC_Msk (0x1FU << 11)
2037 /*------------------------------------------------------------------------------------------------------*/
2038 /*--- Inter-IC Sound (I2S) ---*/
2039 /*------------------------------------------------------------------------------------------------------*/
2040 /******************************** Bit definition for I2S_IER register *********************************/
2041 #define I2S_IER_IEN (0x1U << 0)
2043 /******************************** Bit definition for I2S_IRER register ********************************/
2044 #define I2S_IRER_RXEN (0x1U << 0)
2046 /******************************** Bit definition for I2S_ITER register ********************************/
2047 #define I2S_ITER_TXEN (0x1U << 0)
2049 /******************************** Bit definition for I2S_CER register *********************************/
2050 #define I2S_CER_CLKEN (0x1U << 0)
2052 /******************************** Bit definition for I2S_CCR register *********************************/
2053 #define I2S_CCR_SCLKG_Msk (0x7U << 0)
2054 #define I2S_CCR_SCLKG_NONE (0x0U << 0)
2055 #define I2S_CCR_SCLKG_12 (0x1U << 0)
2056 #define I2S_CCR_SCLKG_16 (0x2U << 0)
2057 #define I2S_CCR_SCLKG_20 (0x3U << 0)
2058 #define I2S_CCR_SCLKG_24 (0x4U << 0)
2060 #define I2S_CCR_WSS_Msk (0x3U << 3)
2061 #define I2S_CCR_WSS_16 (0x0U << 3)
2062 #define I2S_CCR_WSS_24 (0x1U << 3)
2063 #define I2S_CCR_WSS_32 (0x2U << 3)
2066 /******************************** Bit definition for I2S_RXFFR register *******************************/
2067 #define I2S_RXFFR_RXFFR (0x1U << 0)
2069 /******************************** Bit definition for I2S_TXFFR register *******************************/
2070 #define I2S_TXFFR_TXFFR (0x1U << 0)
2076 /*------------------------------------------------------------------------------------------------------*/
2077 /*--- Universal Serial Bus (USB) ---*/
2078 /*------------------------------------------------------------------------------------------------------*/
2079 /******************************** Bit definition for USB_FADDR register ********************************/
2080 #define USB_FADDR_FADDR_Msk (0x7FU)
2081 #define USB_FADDR_UPDATE (0x1U << 7)
2083 /******************************** Bit definition for USB_POWER register ********************************/
2084 #define USB_POWER_SUSEN (0x1U << 0)
2085 #define USB_POWER_SUSMD (0x1U << 1)
2086 #define USB_POWER_RESUME (0x1U << 2)
2087 #define USB_POWER_USBRST (0x1U << 3)
2088 #define USB_POWER_ISOUD (0x1U << 7)
2090 /******************************** Bit definition for USB_INTRIN register ********************************/
2091 #define USB_INTRIN_EP0 (0x1U << 0)
2092 #define USB_INTRIN_IN1 (0x1U << 1)
2093 #define USB_INTRIN_IN2 (0x1U << 2)
2094 #define USB_INTRIN_IN3 (0x1U << 3)
2096 /******************************** Bit definition for USB_INTROUT register ********************************/
2097 #define USB_INTROUT_OUT1 (0x1U << 1)
2098 #define USB_INTROUT_OUT2 (0x1U << 2)
2099 #define USB_INTROUT_OUT3 (0x1U << 3)
2101 /******************************** Bit definition for USB_INTRUSB register ********************************/
2102 #define USB_INTRUSB_SUSIS (0x1U << 0)
2103 #define USB_INTRUSB_RSUIS (0x1U << 1)
2104 #define USB_INTRUSB_RSTIS (0x1U << 2)
2105 #define USB_INTRUSB_SOFIS (0x1U << 3)
2107 /******************************** Bit definition for USB_INTRINE register ********************************/
2108 #define USB_INTRINE_EP0E (0x1U << 0)
2109 #define USB_INTRINE_IN1E (0x1U << 1)
2110 #define USB_INTRINE_IN2E (0x1U << 2)
2111 #define USB_INTRINE_IN3E (0x1U << 3)
2113 /******************************** Bit definition for USB_INTROUTE register ********************************/
2114 #define USB_INTROUTE_OUT1E (0x1U << 1)
2115 #define USB_INTROUTE_OUT2E (0x1U << 2)
2116 #define USB_INTROUTE_OUT3E (0x1U << 3)
2118 /******************************** Bit definition for USB_INTRUSBE register ********************************/
2119 #define USB_INTRUSBE_SUSIE (0x1U << 0)
2120 #define USB_INTRUSBE_RSUIE (0x1U << 1)
2121 #define USB_INTRUSBE_RSTIE (0x1U << 2)
2122 #define USB_INTRUSBE_SOFIE (0x1U << 3)
2124 /******************************** Bit definition for USB_CSR0 register ********************************/
2125 #define USB_CSR0_OUTPKTRDY (0x1U << 0)
2126 #define USB_CSR0_INPKTRDY (0x1U << 1)
2127 #define USB_CSR0_SENTSTALL (0x1U << 2)
2128 #define USB_CSR0_DATAEND (0x1U << 3)
2129 #define USB_CSR0_SETUPEND (0x1U << 4)
2130 #define USB_CSR0_SENDSTALL (0x1U << 5)
2131 #define USB_CSR0_SVDOUTPKTRDY (0x1U << 6)
2132 #define USB_CSR0_SVDSETUPEND (0x1U << 7)
2134 /******************************** Bit definition for USB_INCSR1 register ********************************/
2135 #define USB_INCSR1_INPKTRDY (0x1U << 0)
2136 #define USB_INCSR1_FIFONE (0x1U << 1)
2137 #define USB_INCSR1_UNDERRUN (0x1U << 2)
2138 #define USB_INCSR1_FLUSHFIFO (0x1U << 3)
2139 #define USB_INCSR1_SENDSTALL (0x1U << 4)
2140 #define USB_INCSR1_SENTSTALL (0x1U << 5)
2141 #define USB_INCSR1_CLRDATATOG (0x1U << 6)
2143 /******************************** Bit definition for USB_INCSR2 register ********************************/
2144 #define USB_INCSR2_FRCDATATOG (0x1U << 3)
2145 #define USB_INCSR2_DMAEN (0x1U << 4)
2146 #define USB_INCSR2_DIRSEL (0x1U << 5)
2147 #define USB_INCSR2_ISO (0x1U << 6)
2148 #define USB_INCSR2_AUTOSET (0x1U << 7)
2150 /******************************** Bit definition for USB_OUTCSR1 register ********************************/
2151 #define USB_OUTCSR1_OUTPKTRDY (0x1U << 0)
2152 #define USB_OUTCSR1_FIFOFULL (0x1U << 1)
2153 #define USB_OUTCSR1_OVERRUN (0x1U << 2)
2154 #define USB_OUTCSR1_DATAERROR (0x1U << 3)
2155 #define USB_OUTCSR1_FLUSHFIFO (0x1U << 4)
2156 #define USB_OUTCSR1_SENDSTALL (0x1U << 5)
2157 #define USB_OUTCSR1_SENTSTALL (0x1U << 6)
2158 #define USB_OUTCSR1_CLRDATATOG (0x1U << 7)
2160 /******************************** Bit definition for USB_OUTCSR2 register ********************************/
2161 #define USB_OUTCSR2_DMAMODE (0x1U << 4)
2162 #define USB_OUTCSR2_DMAEN (0x1U << 5)
2163 #define USB_OUTCSR2_ISO (0x1U << 6)
2164 #define USB_OUTCSR2_AUTOCLR (0x1U << 7)
2170 /*------------------------------------------------------------------------------------------------------*/
2171 /*--- Timer (TIM) ---*/
2172 /*------------------------------------------------------------------------------------------------------*/
2173 /******************************** Bit definition for TIM_CR1 register ********************************/
2174 #define TIM_CR1_CEN (0x1U << 0)
2175 #define TIM_CR1_UDIS (0x1U << 1)
2176 #define TIM_CR1_URS (0x1U << 2)
2177 #define TIM_CR1_OPM (0x1U << 3)
2178 #define TIM_CR1_DIR (0x1U << 4)
2180 #define TIM_CR1_CMS (0x3U << 5)
2181 #define TIM_CR1_CMS_0 (0x1U << 5)
2182 #define TIM_CR1_CMS_1 (0x1U << 6)
2184 #define TIM_CR1_ARPE (0x1U << 7)
2186 #define TIM_CR1_CKD (0x3U << 8)
2187 #define TIM_CR1_CKD_0 (0x1U << 8)
2188 #define TIM_CR1_CKD_1 (0x1U << 9)
2190 /******************************** Bit definition for TIM_CR2 register ********************************/
2191 #define TIM_CR2_CCPC (0x1U << 0)
2192 #define TIM_CR2_CCUS (0x1U << 2)
2193 #define TIM_CR2_CCDS (0x1U << 3)
2195 #define TIM_CR2_MMS (0x7U << 4)
2196 #define TIM_CR2_MMS_0 (0x1U << 4)
2197 #define TIM_CR2_MMS_1 (0x1U << 5)
2198 #define TIM_CR2_MMS_2 (0x1U << 6)
2200 #define TIM_CR2_TI1S (0x1U << 7)
2201 #define TIM_CR2_OIS1 (0x1U << 8)
2202 #define TIM_CR2_OIS1N (0x1U << 9)
2203 #define TIM_CR2_OIS2 (0x1U << 10)
2204 #define TIM_CR2_OIS2N (0x1U << 11)
2205 #define TIM_CR2_OIS3 (0x1U << 12)
2206 #define TIM_CR2_OIS3N (0x1U << 13)
2207 #define TIM_CR2_OIS4 (0x1U << 14)
2209 /******************************** Bit definition for TIM_SMCR register ********************************/
2210 #define TIM_SMCR_SMS (0x7U << 0)
2211 #define TIM_SMCR_SMS_0 (0x1U << 0)
2212 #define TIM_SMCR_SMS_1 (0x1U << 1)
2213 #define TIM_SMCR_SMS_2 (0x1U << 2)
2215 #define TIM_SMCR_TS (0x7U << 4)
2216 #define TIM_SMCR_TS_0 (0x1U << 4)
2217 #define TIM_SMCR_TS_1 (0x1U << 5)
2218 #define TIM_SMCR_TS_2 (0x1U << 6)
2220 #define TIM_SMCR_MSM (0x1U << 7)
2222 #define TIM_SMCR_ETF (0xFU << 8)
2223 #define TIM_SMCR_ETF_0 (0x1U << 8)
2224 #define TIM_SMCR_ETF_1 (0x1U << 9)
2225 #define TIM_SMCR_ETF_2 (0x1U << 10)
2226 #define TIM_SMCR_ETF_3 (0x1U << 11)
2228 #define TIM_SMCR_ETPS (0x3U << 12)
2229 #define TIM_SMCR_ETPS_0 (0x1U << 12)
2230 #define TIM_SMCR_ETPS_1 (0x1U << 13)
2232 #define TIM_SMCR_ECE (0x1U << 14)
2233 #define TIM_SMCR_ETP (0x1U << 15)
2235 /******************************** Bit definition for TIM_DIER register ********************************/
2236 #define TIM_DIER_UIE (0x1U << 0)
2237 #define TIM_DIER_CC1IE (0x1U << 1)
2238 #define TIM_DIER_CC2IE (0x1U << 2)
2239 #define TIM_DIER_CC3IE (0x1U << 3)
2240 #define TIM_DIER_CC4IE (0x1U << 4)
2241 #define TIM_DIER_COMIE (0x1U << 5)
2242 #define TIM_DIER_TIE (0x1U << 6)
2243 #define TIM_DIER_BIE (0x1U << 7)
2244 #define TIM_DIER_UDE (0x1U << 8)
2245 #define TIM_DIER_CC1DE (0x1U << 9)
2246 #define TIM_DIER_CC2DE (0x1U << 10)
2247 #define TIM_DIER_CC3DE (0x1U << 11)
2248 #define TIM_DIER_CC4DE (0x1U << 12)
2249 #define TIM_DIER_COMDE (0x1U << 13)
2250 #define TIM_DIER_TDE (0x1U << 14)
2252 /******************************** Bit definition for TIM_SR register ********************************/
2253 #define TIM_SR_UIF (0x1U << 0)
2254 #define TIM_SR_CC1IF (0x1U << 1)
2255 #define TIM_SR_CC2IF (0x1U << 2)
2256 #define TIM_SR_CC3IF (0x1U << 3)
2257 #define TIM_SR_CC4IF (0x1U << 4)
2258 #define TIM_SR_COMIF (0x1U << 5)
2259 #define TIM_SR_TIF (0x1U << 6)
2260 #define TIM_SR_BIF (0x1U << 7)
2261 #define TIM_SR_CC1OF (0x1U << 9)
2262 #define TIM_SR_CC2OF (0x1U << 10)
2263 #define TIM_SR_CC3OF (0x1U << 11)
2264 #define TIM_SR_CC4OF (0x1U << 12)
2266 /******************************** Bit definition for TIM_EGR register ********************************/
2267 #define TIM_EGR_UG (0x1U << 0)
2268 #define TIM_EGR_CC1G (0x1U << 1)
2269 #define TIM_EGR_CC2G (0x1U << 2)
2270 #define TIM_EGR_CC3G (0x1U << 3)
2271 #define TIM_EGR_CC4G (0x1U << 4)
2272 #define TIM_EGR_COMG (0x1U << 5)
2273 #define TIM_EGR_TG (0x1U << 6)
2274 #define TIM_EGR_BG (0x1U << 7)
2276 /******************************** Bit definition for TIM_CCMR1 register ********************************/
2277 #define TIM_CCMR1_CC1S (0x3U << 0)
2278 #define TIM_CCMR1_CC1S_0 (0x1U << 0)
2279 #define TIM_CCMR1_CC1S_1 (0x1U << 1)
2281 #define TIM_CCMR1_OC1FE (0x1U << 2)
2282 #define TIM_CCMR1_OC1PE (0x1U << 3)
2284 #define TIM_CCMR1_OC1M (0x7U << 4)
2285 #define TIM_CCMR1_OC1M_0 (0x1U << 4)
2286 #define TIM_CCMR1_OC1M_1 (0x1U << 5)
2287 #define TIM_CCMR1_OC1M_2 (0x1U << 6)
2289 #define TIM_CCMR1_OC1CE (0x1U << 7)
2291 #define TIM_CCMR1_CC2S (0x3U << 8)
2292 #define TIM_CCMR1_CC2S_0 (0x1U << 8)
2293 #define TIM_CCMR1_CC2S_1 (0x1U << 9)
2295 #define TIM_CCMR1_OC2FE (0x1U << 10)
2296 #define TIM_CCMR1_OC2PE (0x1U << 11)
2298 #define TIM_CCMR1_OC2M (0x7U << 12)
2299 #define TIM_CCMR1_OC2M_0 (0x1U << 12)
2300 #define TIM_CCMR1_OC2M_1 (0x1U << 13)
2301 #define TIM_CCMR1_OC2M_2 (0x1U << 14)
2303 #define TIM_CCMR1_OC2CE (0x1U << 15)
2305 /*------------------------------------------------------------------------------------------*/
2306 
2307 #define TIM_CCMR1_IC1PSC (0x3U << 2)
2308 #define TIM_CCMR1_IC1PSC_0 (0x1U << 2)
2309 #define TIM_CCMR1_IC1PSC_1 (0x1U << 3)
2311 #define TIM_CCMR1_IC1F (0xFU << 4)
2312 #define TIM_CCMR1_IC1F_0 (0x1U << 4)
2313 #define TIM_CCMR1_IC1F_1 (0x1U << 5)
2314 #define TIM_CCMR1_IC1F_2 (0x1U << 6)
2315 #define TIM_CCMR1_IC1F_3 (0x1U << 7)
2317 #define TIM_CCMR1_IC2PSC (0x3U << 10)
2318 #define TIM_CCMR1_IC2PSC_0 (0x1U << 10)
2319 #define TIM_CCMR1_IC2PSC_1 (0x1U << 11)
2321 #define TIM_CCMR1_IC2F (0xFU << 12)
2322 #define TIM_CCMR1_IC2F_0 (0x1U << 12)
2323 #define TIM_CCMR1_IC2F_1 (0x1U << 13)
2324 #define TIM_CCMR1_IC2F_2 (0x1U << 14)
2325 #define TIM_CCMR1_IC2F_3 (0x1U << 15)
2327 /******************************** Bit definition for TIM_CCMR2 register ********************************/
2328 #define TIM_CCMR2_CC3S (0x3U << 0)
2329 #define TIM_CCMR2_CC3S_0 (0x1U << 0)
2330 #define TIM_CCMR2_CC3S_1 (0x1U << 1)
2332 #define TIM_CCMR2_OC3FE (0x1U << 2)
2333 #define TIM_CCMR2_OC3PE (0x1U << 3)
2335 #define TIM_CCMR2_OC3M (0x7U << 4)
2336 #define TIM_CCMR2_OC3M_0 (0x1U << 4)
2337 #define TIM_CCMR2_OC3M_1 (0x1U << 5)
2338 #define TIM_CCMR2_OC3M_2 (0x1U << 6)
2340 #define TIM_CCMR2_OC3CE (0x1U << 7)
2342 #define TIM_CCMR2_CC4S (0x3U << 8)
2343 #define TIM_CCMR2_CC4S_0 (0x1U << 8)
2344 #define TIM_CCMR2_CC4S_1 (0x1U << 9)
2346 #define TIM_CCMR2_OC4FE (0x1U << 10)
2347 #define TIM_CCMR2_OC4PE (0x1U << 11)
2349 #define TIM_CCMR2_OC4M (0x7U << 12)
2350 #define TIM_CCMR2_OC4M_0 (0x1U << 12)
2351 #define TIM_CCMR2_OC4M_1 (0x1U << 13)
2352 #define TIM_CCMR2_OC4M_2 (0x1U << 14)
2354 #define TIM_CCMR2_OC4CE (0x1U << 15)
2356 /*------------------------------------------------------------------------------------------*/
2357 
2358 #define TIM_CCMR2_IC3PSC (0x3U << 2)
2359 #define TIM_CCMR2_IC3PSC_0 (0x1U << 2)
2360 #define TIM_CCMR2_IC3PSC_1 (0x1U << 3)
2362 #define TIM_CCMR2_IC3F (0xFU << 4)
2363 #define TIM_CCMR2_IC3F_0 (0x1U << 4)
2364 #define TIM_CCMR2_IC3F_1 (0x1U << 5)
2365 #define TIM_CCMR2_IC3F_2 (0x1U << 6)
2366 #define TIM_CCMR2_IC3F_3 (0x1U << 7)
2368 #define TIM_CCMR2_IC4PSC (0x3U << 10)
2369 #define TIM_CCMR2_IC4PSC_0 (0x1U << 10)
2370 #define TIM_CCMR2_IC4PSC_1 (0x1U << 11)
2372 #define TIM_CCMR2_IC4F (0xFU << 12)
2373 #define TIM_CCMR2_IC4F_0 (0x1U << 12)
2374 #define TIM_CCMR2_IC4F_1 (0x1U << 13)
2375 #define TIM_CCMR2_IC4F_2 (0x1U << 14)
2376 #define TIM_CCMR2_IC4F_3 (0x1U << 15)
2378 /******************************** Bit definition for TIM_CCER register ********************************/
2379 #define TIM_CCER_CC1E (0x1U << 0)
2380 #define TIM_CCER_CC1P (0x1U << 1)
2381 #define TIM_CCER_CC1NE (0x1U << 2)
2382 #define TIM_CCER_CC1NP (0x1U << 3)
2383 #define TIM_CCER_CC2E (0x1U << 4)
2384 #define TIM_CCER_CC2P (0x1U << 5)
2385 #define TIM_CCER_CC2NE (0x1U << 6)
2386 #define TIM_CCER_CC2NP (0x1U << 7)
2387 #define TIM_CCER_CC3E (0x1U << 8)
2388 #define TIM_CCER_CC3P (0x1U << 9)
2389 #define TIM_CCER_CC3NE (0x1U << 10)
2390 #define TIM_CCER_CC3NP (0x1U << 11)
2391 #define TIM_CCER_CC4E (0x1U << 12)
2392 #define TIM_CCER_CC4P (0x1U << 13)
2394 /******************************** Bit definition for TIM_CNT register ********************************/
2395 #define TIM_CNT_CNT (0xFFFFFU)
2397 /******************************** Bit definition for TIM_PSC register ********************************/
2398 #define TIM_PSC_PSC (0xFFFFU)
2400 /******************************** Bit definition for TIM_ARR register ********************************/
2401 #define TIM_ARR_ARR (0xFFFFFU)
2403 /******************************** Bit definition for TIM_RCR register ********************************/
2404 #define TIM_RCR_REP (0xFFU)
2406 /******************************** Bit definition for TIM_CCR1 register ********************************/
2407 #define TIM_CCR1_CCR1 (0xFFFFFU)
2409 /******************************** Bit definition for TIM_CCR2 register ********************************/
2410 #define TIM_CCR2_CCR2 (0xFFFFFU)
2412 /******************************** Bit definition for TIM_CCR3 register ********************************/
2413 #define TIM_CCR3_CCR3 (0xFFFFFU)
2415 /******************************** Bit definition for TIM_CCR4 register ********************************/
2416 #define TIM_CCR4_CCR4 (0xFFFFFU)
2418 /******************************** Bit definition for TIM_BDTR register ********************************/
2419 #define TIM_BDTR_DTG (0xFFU << 0)
2420 #define TIM_BDTR_DTG_0 (0x1U << 0)
2421 #define TIM_BDTR_DTG_1 (0x1U << 1)
2422 #define TIM_BDTR_DTG_2 (0x1U << 2)
2423 #define TIM_BDTR_DTG_3 (0x1U << 3)
2424 #define TIM_BDTR_DTG_4 (0x1U << 4)
2425 #define TIM_BDTR_DTG_5 (0x1U << 5)
2426 #define TIM_BDTR_DTG_6 (0x1U << 6)
2427 #define TIM_BDTR_DTG_7 (0x1U << 7)
2429 #define TIM_BDTR_LOCK (0x3U << 8)
2430 #define TIM_BDTR_LOCK_0 (0x1U << 8)
2431 #define TIM_BDTR_LOCK_1 (0x1U << 9)
2433 #define TIM_BDTR_OSSI (0x1U << 10)
2434 #define TIM_BDTR_OSSR (0x1U << 11)
2435 #define TIM_BDTR_BKE (0x1U << 12)
2436 #define TIM_BDTR_BKP (0x1U << 13)
2437 #define TIM_BDTR_AOE (0x1U << 14)
2438 #define TIM_BDTR_MOE (0x1U << 15)
2441 /*------------------------------------------------------------------------------------------------------*/
2442 /*--- External Interrupt/Event Controller (EXTI) ---*/
2443 /*------------------------------------------------------------------------------------------------------*/
2444 /******************************** Bit definition for EXTI_IMR register ********************************/
2445 #define EXTI_IMR_MR0 ((uint32_t)0x00000001)
2446 #define EXTI_IMR_MR1 ((uint32_t)0x00000002)
2447 #define EXTI_IMR_MR2 ((uint32_t)0x00000004)
2448 #define EXTI_IMR_MR3 ((uint32_t)0x00000008)
2449 #define EXTI_IMR_MR4 ((uint32_t)0x00000010)
2450 #define EXTI_IMR_MR5 ((uint32_t)0x00000020)
2451 #define EXTI_IMR_MR6 ((uint32_t)0x00000040)
2452 #define EXTI_IMR_MR7 ((uint32_t)0x00000080)
2453 #define EXTI_IMR_MR8 ((uint32_t)0x00000100)
2454 #define EXTI_IMR_MR9 ((uint32_t)0x00000200)
2455 #define EXTI_IMR_MR10 ((uint32_t)0x00000400)
2456 #define EXTI_IMR_MR11 ((uint32_t)0x00000800)
2457 #define EXTI_IMR_MR12 ((uint32_t)0x00001000)
2458 #define EXTI_IMR_MR13 ((uint32_t)0x00002000)
2459 #define EXTI_IMR_MR14 ((uint32_t)0x00004000)
2460 #define EXTI_IMR_MR15 ((uint32_t)0x00008000)
2461 #define EXTI_IMR_MR16 ((uint32_t)0x00010000)
2462 #define EXTI_IMR_MR17 ((uint32_t)0x00020000)
2463 #define EXTI_IMR_MR18 ((uint32_t)0x00040000)
2465 /******************************** Bit definition for EXTI_EMR register ********************************/
2466 #define EXTI_EMR_MR0 ((uint32_t)0x00000001)
2467 #define EXTI_EMR_MR1 ((uint32_t)0x00000002)
2468 #define EXTI_EMR_MR2 ((uint32_t)0x00000004)
2469 #define EXTI_EMR_MR3 ((uint32_t)0x00000008)
2470 #define EXTI_EMR_MR4 ((uint32_t)0x00000010)
2471 #define EXTI_EMR_MR5 ((uint32_t)0x00000020)
2472 #define EXTI_EMR_MR6 ((uint32_t)0x00000040)
2473 #define EXTI_EMR_MR7 ((uint32_t)0x00000080)
2474 #define EXTI_EMR_MR8 ((uint32_t)0x00000100)
2475 #define EXTI_EMR_MR9 ((uint32_t)0x00000200)
2476 #define EXTI_EMR_MR10 ((uint32_t)0x00000400)
2477 #define EXTI_EMR_MR11 ((uint32_t)0x00000800)
2478 #define EXTI_EMR_MR12 ((uint32_t)0x00001000)
2479 #define EXTI_EMR_MR13 ((uint32_t)0x00002000)
2480 #define EXTI_EMR_MR14 ((uint32_t)0x00004000)
2481 #define EXTI_EMR_MR15 ((uint32_t)0x00008000)
2482 #define EXTI_EMR_MR16 ((uint32_t)0x00010000)
2483 #define EXTI_EMR_MR17 ((uint32_t)0x00020000)
2484 #define EXTI_EMR_MR18 ((uint32_t)0x00040000)
2486 /******************************** Bit definition for EXTI_RTSR register ********************************/
2487 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001)
2488 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002)
2489 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004)
2490 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008)
2491 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010)
2492 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020)
2493 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040)
2494 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080)
2495 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100)
2496 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200)
2497 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400)
2498 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800)
2499 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000)
2500 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000)
2501 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000)
2502 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000)
2503 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000)
2504 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000)
2505 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000)
2507 /******************************** Bit definition for EXTI_FTSR register ********************************/
2508 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001)
2509 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002)
2510 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004)
2511 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008)
2512 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010)
2513 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020)
2514 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040)
2515 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080)
2516 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100)
2517 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200)
2518 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400)
2519 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800)
2520 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000)
2521 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000)
2522 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000)
2523 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000)
2524 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000)
2525 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000)
2526 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000)
2528 /******************************** Bit definition for EXTI_SWIER register ********************************/
2529 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001)
2530 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002)
2531 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004)
2532 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008)
2533 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010)
2534 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020)
2535 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040)
2536 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080)
2537 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100)
2538 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200)
2539 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400)
2540 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800)
2541 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000)
2542 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000)
2543 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000)
2544 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000)
2545 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000)
2546 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000)
2547 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000)
2549 /******************************** Bit definition for EXTI_PR register ********************************/
2550 #define EXTI_PR_PR0 ((uint32_t)0x00000001)
2551 #define EXTI_PR_PR1 ((uint32_t)0x00000002)
2552 #define EXTI_PR_PR2 ((uint32_t)0x00000004)
2553 #define EXTI_PR_PR3 ((uint32_t)0x00000008)
2554 #define EXTI_PR_PR4 ((uint32_t)0x00000010)
2555 #define EXTI_PR_PR5 ((uint32_t)0x00000020)
2556 #define EXTI_PR_PR6 ((uint32_t)0x00000040)
2557 #define EXTI_PR_PR7 ((uint32_t)0x00000080)
2558 #define EXTI_PR_PR8 ((uint32_t)0x00000100)
2559 #define EXTI_PR_PR9 ((uint32_t)0x00000200)
2560 #define EXTI_PR_PR10 ((uint32_t)0x00000400)
2561 #define EXTI_PR_PR11 ((uint32_t)0x00000800)
2562 #define EXTI_PR_PR12 ((uint32_t)0x00001000)
2563 #define EXTI_PR_PR13 ((uint32_t)0x00002000)
2564 #define EXTI_PR_PR14 ((uint32_t)0x00004000)
2565 #define EXTI_PR_PR15 ((uint32_t)0x00008000)
2566 #define EXTI_PR_PR16 ((uint32_t)0x00010000)
2567 #define EXTI_PR_PR17 ((uint32_t)0x00020000)
2568 #define EXTI_PR_PR18 ((uint32_t)0x00040000)
2571 /*------------------------------------------------------------------------------------------------------*/
2572 /*--- Alternate Function I/O (AFIO) ---*/
2573 /*------------------------------------------------------------------------------------------------------*/
2574 /******************************** Bit definition for AFIO_EXTICR1 register ********************************/
2575 #define AFIO_EXTICR1_EXTI0_Msk ((uint16_t)0x000F)
2576 #define AFIO_EXTICR1_EXTI1_Msk ((uint16_t)0x00F0)
2577 #define AFIO_EXTICR1_EXTI2_Msk ((uint16_t)0x0F00)
2578 #define AFIO_EXTICR1_EXTI3_Msk ((uint16_t)0xF000)
2581 #define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000)
2582 #define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001)
2583 #define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002)
2584 #define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003)
2587 #define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000)
2588 #define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010)
2589 #define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020)
2590 #define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030)
2593 #define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000)
2594 #define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100)
2595 #define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200)
2596 #define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300)
2599 #define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000)
2600 #define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000)
2601 #define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000)
2603 /******************************** Bit definition for AFIO_EXTICR2 register ********************************/
2604 #define AFIO_EXTICR2_EXTI4_Msk ((uint16_t)0x000F)
2605 #define AFIO_EXTICR2_EXTI5_Msk ((uint16_t)0x00F0)
2606 #define AFIO_EXTICR2_EXTI6_Msk ((uint16_t)0x0F00)
2607 #define AFIO_EXTICR2_EXTI7_Msk ((uint16_t)0xF000)
2610 #define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000)
2611 #define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001)
2612 #define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002)
2615 #define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000)
2616 #define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010)
2617 #define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020)
2620 #define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000)
2621 #define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100)
2622 #define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200)
2625 #define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000)
2626 #define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000)
2627 #define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000)
2629 /******************************** Bit definition for AFIO_EXTICR3 register ********************************/
2630 #define AFIO_EXTICR3_EXTI8_Msk ((uint16_t)0x000F)
2631 #define AFIO_EXTICR3_EXTI9_Msk ((uint16_t)0x00F0)
2632 #define AFIO_EXTICR3_EXTI10_Msk ((uint16_t)0x0F00)
2633 #define AFIO_EXTICR3_EXTI11_Msk ((uint16_t)0xF000)
2636 #define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000)
2637 #define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001)
2638 #define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002)
2641 #define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000)
2642 #define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010)
2643 #define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020)
2646 #define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000)
2647 #define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100)
2648 #define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200)
2651 #define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000)
2652 #define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000)
2653 #define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000)
2655 /******************************** Bit definition for AFIO_EXTICR4 register ********************************/
2656 #define AFIO_EXTICR4_EXTI12_Msk ((uint16_t)0x000F)
2657 #define AFIO_EXTICR4_EXTI13_Msk ((uint16_t)0x00F0)
2658 #define AFIO_EXTICR4_EXTI14_Msk ((uint16_t)0x0F00)
2659 #define AFIO_EXTICR4_EXTI15_Msk ((uint16_t)0xF000)
2661 /* EXTI12 configuration */
2662 #define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000)
2663 #define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001)
2664 #define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002)
2666 /* EXTI13 configuration */
2667 #define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000)
2668 #define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010)
2669 #define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020)
2672 #define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000)
2673 #define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100)
2674 #define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200)
2677 #define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000)
2678 #define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000)
2679 #define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000)
2683 /*------------------------------------------------------------------------------------------------------*/
2684 /*--- Real-Time Clock (RTC) ---*/
2685 /*------------------------------------------------------------------------------------------------------*/
2686 /******************************** Bit definition for RTC_CRH register ********************************/
2687 #define RTC_CRH_SECIE ((uint8_t)0x01)
2688 #define RTC_CRH_ALRIE ((uint8_t)0x02)
2689 #define RTC_CRH_OWIE ((uint8_t)0x04)
2691 /******************************** Bit definition for RTC_CRL register ********************************/
2692 #define RTC_CRL_SECF ((uint8_t)0x01)
2693 #define RTC_CRL_ALRF ((uint8_t)0x02)
2694 #define RTC_CRL_OWF ((uint8_t)0x04)
2695 #define RTC_CRL_RSF ((uint8_t)0x08)
2696 #define RTC_CRL_CNF ((uint8_t)0x10)
2697 #define RTC_CRL_RTOFF ((uint8_t)0x20)
2699 /******************************** Bit definition for RTC_PRLH register ********************************/
2700 #define RTC_PRLH_PRL ((uint16_t)0x000F)
2702 /******************************** Bit definition for RTC_PRLL register ********************************/
2703 #define RTC_PRLL_PRL ((uint16_t)0xFFFF)
2705 /******************************** Bit definition for RTC_DIVH register ********************************/
2706 #define RTC_DIVH_RTC_DIV ((uint16_t)0x000F)
2708 /******************************** Bit definition for RTC_DIVL register ********************************/
2709 #define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF)
2711 /******************************** Bit definition for RTC_CNTH register ********************************/
2712 #define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF)
2714 /******************************** Bit definition for RTC_CNTL register ********************************/
2715 #define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF)
2717 /******************************** Bit definition for RTC_ALRH register ********************************/
2718 #define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF)
2720 /******************************** Bit definition for RTC_ALRL register ********************************/
2721 #define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF)
2728 /*------------------------------------------------------------------------------------------------------*/
2729 /*--- Backup Registers (BKP) ---*/
2730 /*------------------------------------------------------------------------------------------------------*/
2731 /******************************** Bit definition for BKP_RTCCR register *********************************/
2732 #define BKP_RTCCR_CAL ((uint16_t)0x007F)
2733 #define BKP_RTCCR_CCO ((uint16_t)0x0080)
2734 #define BKP_RTCCR_ASOE ((uint16_t)0x0100)
2735 #define BKP_RTCCR_ASOS ((uint16_t)0x0200)
2737 /******************************** Bit definition for BKP_CR register *********************************/
2738 #define BKP_CR_TPE ((uint8_t)0x01)
2739 #define BKP_CR_TPAL ((uint8_t)0x02)
2741 /******************************** Bit definition for BKP_CSR register *********************************/
2742 #define BKP_CSR_CTE ((uint16_t)0x0001)
2743 #define BKP_CSR_CTI ((uint16_t)0x0002)
2744 #define BKP_CSR_TPIE ((uint16_t)0x0004)
2745 #define BKP_CSR_TEF ((uint16_t)0x0100)
2746 #define BKP_CSR_TIF ((uint16_t)0x0200)
2752 /*------------------------------------------------------------------------------------------------------*/
2753 /*--- Window watchdog (WWDG) ---*/
2754 /*------------------------------------------------------------------------------------------------------*/
2755 /******************************** Bit definition for WWDG_CR register ********************************/
2756 #define WWDG_CR_T ((uint8_t)0x7F)
2757 #define WWDG_CR_T0 ((uint8_t)0x01)
2758 #define WWDG_CR_T1 ((uint8_t)0x02)
2759 #define WWDG_CR_T2 ((uint8_t)0x04)
2760 #define WWDG_CR_T3 ((uint8_t)0x08)
2761 #define WWDG_CR_T4 ((uint8_t)0x10)
2762 #define WWDG_CR_T5 ((uint8_t)0x20)
2763 #define WWDG_CR_T6 ((uint8_t)0x40)
2765 #define WWDG_CR_WDGA ((uint8_t)0x80)
2767 /******************************** Bit definition for WWDG_CFR register ********************************/
2768 #define WWDG_CFR_W ((uint16_t)0x007F)
2769 #define WWDG_CFR_W0 ((uint16_t)0x0001)
2770 #define WWDG_CFR_W1 ((uint16_t)0x0002)
2771 #define WWDG_CFR_W2 ((uint16_t)0x0004)
2772 #define WWDG_CFR_W3 ((uint16_t)0x0008)
2773 #define WWDG_CFR_W4 ((uint16_t)0x0010)
2774 #define WWDG_CFR_W5 ((uint16_t)0x0020)
2775 #define WWDG_CFR_W6 ((uint16_t)0x0040)
2777 #define WWDG_CFR_WDGTB ((uint16_t)0x0180)
2778 #define WWDG_CFR_WDGTB0 ((uint16_t)0x0080)
2779 #define WWDG_CFR_WDGTB1 ((uint16_t)0x0100)
2781 #define WWDG_CFR_EWI ((uint16_t)0x0200)
2783 /******************************** Bit definition for WWDG_SR register ********************************/
2784 #define WWDG_SR_EWIF ((uint8_t)0x01)
2788 /*------------------------------------------------------------------------------------------------------*/
2789 /*--- Independent watchdog (IWDG) ---*/
2790 /*------------------------------------------------------------------------------------------------------*/
2791 /******************************** Bit definition for IWDG_KR register ********************************/
2792 #define IWDG_KR_KEY ((uint16_t)0xFFFF)
2794 /******************************** Bit definition for IWDG_PR register ********************************/
2795 #define IWDG_PR_PR ((uint8_t)0x07)
2796 #define IWDG_PR_PR_0 ((uint8_t)0x01)
2797 #define IWDG_PR_PR_1 ((uint8_t)0x02)
2798 #define IWDG_PR_PR_2 ((uint8_t)0x04)
2800 /******************************** Bit definition for IWDG_RLR register ********************************/
2801 #define IWDG_RLR_RL ((uint16_t)0x0FFF)
2803 /******************************** Bit definition for IWDG_SR register ********************************/
2804 #define IWDG_SR_PVU ((uint8_t)0x01)
2805 #define IWDG_SR_RVU ((uint8_t)0x02)
2808 /******************************************************************************/
2809 /* */
2810 /* Analog to Digital Converter */
2811 /* */
2812 /******************************************************************************/
2813 
2814 /******************** Bit definition for ADC_SR register ********************/
2815 #define ADC_SR_AWD ((uint8_t)0x01)
2816 #define ADC_SR_EOC ((uint8_t)0x02)
2817 #define ADC_SR_JEOC ((uint8_t)0x04)
2818 #define ADC_SR_JSTRT ((uint8_t)0x08)
2819 #define ADC_SR_STRT ((uint8_t)0x10)
2820 #define ADC_SR_EMP ((uint8_t)0x20)
2821 #define ADC_SR_OVF ((uint8_t)0x40)
2824 /******************* Bit definition for ADC_CR1 register ********************/
2825 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F)
2826 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001)
2827 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002)
2828 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004)
2829 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008)
2830 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010)
2832 #define ADC_CR1_EOCIE ((uint32_t)0x00000020)
2833 #define ADC_CR1_AWDIE ((uint32_t)0x00000040)
2834 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080)
2835 #define ADC_CR1_SCAN ((uint32_t)0x00000100)
2836 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200)
2837 #define ADC_CR1_JAUTO ((uint32_t)0x00000400)
2838 #define ADC_CR1_DISCEN ((uint32_t)0x00000800)
2839 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000)
2841 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000)
2842 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000)
2843 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000)
2844 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000)
2846 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000)
2847 #define ADC_CR1_AWDEN ((uint32_t)0x00800000)
2850 /******************* Bit definition for ADC_CR2 register ********************/
2851 #define ADC_CR2_ADON ((uint32_t)0x00000001)
2852 #define ADC_CR2_CONT ((uint32_t)0x00000002)
2853 #define ADC_CR2_CAL ((uint32_t)0x00000004)
2854 #define ADC_CR2_RSTCAL ((uint32_t)0x00000008)
2855 #define ADC_CR2_DMAEN ((uint32_t)0x00000100)
2856 #define ADC_CR2_JDMAEN ((uint32_t)0x00000200)
2857 #define ADC_CR2_JEXTSYNC ((uint32_t)0x00000400)
2858 #define ADC_CR2_ALIGN ((uint32_t)0x00000800)
2860 #define ADC_CR2_JEXTSEL ((uint32_t)0x00007000)
2861 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000)
2862 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000)
2863 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000)
2865 #define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000)
2866 #define ADC_CR2_EXTSYNC ((uint32_t)0x00010000)
2868 #define ADC_CR2_EXTSEL ((uint32_t)0x000E0000)
2869 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000)
2870 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000)
2871 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000)
2873 #define ADC_CR2_EXTTRIG ((uint32_t)0x00100000)
2874 #define ADC_CR2_JSWSTART ((uint32_t)0x00200000)
2875 #define ADC_CR2_SWSTART ((uint32_t)0x00400000)
2876 #define ADC_CR2_TSVREFE ((uint32_t)0x00800000)
2878 /****************** Bit definition for ADC_SMPR1 register *******************/
2879 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007)
2880 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001)
2881 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002)
2882 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004)
2884 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038)
2885 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008)
2886 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010)
2887 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020)
2889 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0)
2890 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040)
2891 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080)
2892 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100)
2894 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00)
2895 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200)
2896 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400)
2897 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800)
2899 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000)
2900 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000)
2901 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000)
2902 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000)
2904 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000)
2905 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000)
2906 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000)
2907 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000)
2909 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000)
2910 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000)
2911 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000)
2912 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000)
2914 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000)
2915 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000)
2916 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000)
2917 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000)
2919 /****************** Bit definition for ADC_SMPR2 register *******************/
2920 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007)
2921 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001)
2922 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002)
2923 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004)
2925 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038)
2926 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008)
2927 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010)
2928 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020)
2930 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0)
2931 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040)
2932 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080)
2933 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100)
2935 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00)
2936 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200)
2937 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400)
2938 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800)
2940 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000)
2941 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000)
2942 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000)
2943 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000)
2945 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000)
2946 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000)
2947 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000)
2948 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000)
2950 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000)
2951 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000)
2952 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000)
2953 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000)
2955 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000)
2956 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000)
2957 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000)
2958 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000)
2960 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000)
2961 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000)
2962 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000)
2963 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000)
2965 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000)
2966 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000)
2967 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000)
2968 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000)
2970 /****************** Bit definition for ADC_JOFR1 register *******************/
2971 #define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF)
2973 /****************** Bit definition for ADC_JOFR2 register *******************/
2974 #define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF)
2976 /****************** Bit definition for ADC_JOFR3 register *******************/
2977 #define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF)
2979 /****************** Bit definition for ADC_JOFR4 register *******************/
2980 #define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF)
2982 /******************* Bit definition for ADC_HTR register ********************/
2983 #define ADC_HTR_HT ((uint16_t)0x0FFF)
2985 /******************* Bit definition for ADC_LTR register ********************/
2986 #define ADC_LTR_LT ((uint16_t)0x0FFF)
2988 /******************* Bit definition for ADC_SQR1 register *******************/
2989 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F)
2990 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001)
2991 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002)
2992 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004)
2993 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008)
2994 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010)
2996 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0)
2997 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020)
2998 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040)
2999 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080)
3000 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100)
3001 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200)
3003 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00)
3004 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400)
3005 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800)
3006 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000)
3007 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000)
3008 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000)
3010 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000)
3011 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000)
3012 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000)
3013 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000)
3014 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000)
3015 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000)
3017 #define ADC_SQR1_L ((uint32_t)0x00F00000)
3018 #define ADC_SQR1_L_0 ((uint32_t)0x00100000)
3019 #define ADC_SQR1_L_1 ((uint32_t)0x00200000)
3020 #define ADC_SQR1_L_2 ((uint32_t)0x00400000)
3021 #define ADC_SQR1_L_3 ((uint32_t)0x00800000)
3023 /******************* Bit definition for ADC_SQR2 register *******************/
3024 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F)
3025 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001)
3026 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002)
3027 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004)
3028 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008)
3029 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010)
3031 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0)
3032 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020)
3033 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040)
3034 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080)
3035 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100)
3036 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200)
3038 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00)
3039 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400)
3040 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800)
3041 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000)
3042 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000)
3043 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000)
3045 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000)
3046 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000)
3047 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000)
3048 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000)
3049 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000)
3050 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000)
3052 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000)
3053 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000)
3054 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000)
3055 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000)
3056 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000)
3057 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000)
3059 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000)
3060 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000)
3061 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000)
3062 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000)
3063 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000)
3064 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000)
3066 /******************* Bit definition for ADC_SQR3 register *******************/
3067 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F)
3068 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001)
3069 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002)
3070 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004)
3071 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008)
3072 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010)
3074 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0)
3075 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020)
3076 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040)
3077 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080)
3078 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100)
3079 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200)
3081 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00)
3082 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400)
3083 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800)
3084 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000)
3085 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000)
3086 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000)
3088 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000)
3089 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000)
3090 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000)
3091 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000)
3092 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000)
3093 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000)
3095 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000)
3096 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000)
3097 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000)
3098 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000)
3099 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000)
3100 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000)
3102 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000)
3103 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000)
3104 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000)
3105 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000)
3106 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000)
3107 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000)
3109 /******************* Bit definition for ADC_JSQR register *******************/
3110 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F)
3111 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001)
3112 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002)
3113 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004)
3114 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008)
3115 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010)
3117 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0)
3118 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020)
3119 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040)
3120 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080)
3121 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100)
3122 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200)
3124 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00)
3125 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400)
3126 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800)
3127 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000)
3128 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000)
3129 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000)
3131 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000)
3132 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000)
3133 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000)
3134 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000)
3135 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000)
3136 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000)
3138 #define ADC_JSQR_JL ((uint32_t)0x00300000)
3139 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000)
3140 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000)
3142 /******************* Bit definition for ADC_JDR1 register *******************/
3143 #define ADC_JDR1_JDATA ((uint16_t)0xFFFF)
3145 /******************* Bit definition for ADC_JDR2 register *******************/
3146 #define ADC_JDR2_JDATA ((uint16_t)0xFFFF)
3148 /******************* Bit definition for ADC_JDR3 register *******************/
3149 #define ADC_JDR3_JDATA ((uint16_t)0xFFFF)
3151 /******************* Bit definition for ADC_JDR4 register *******************/
3152 #define ADC_JDR4_JDATA ((uint16_t)0xFFFF)
3154 /******************** Bit definition for ADC_DR register ********************/
3155 #define ADC_DR_DATA ((uint32_t)0x0000FFFF)
3158 /******************** Bit definition for ADC_CR3 register ********************/
3159 #define ADC_CR3_ADVMODE ((uint32_t)0x00000003)
3160 #define ADC_CR3_SAMCHN ((uint32_t)0x0000000C)
3161 #define ADC_CR3_VREFCFG ((uint32_t)0x00000030)
3162 #define ADC_CR3_12BIT ((uint32_t)0x00000040)
3163 #define ADC_CR3_PRS ((uint32_t)0x0000FF00)
3164 #define ADC_CR3_OVFIE ((uint32_t)0x00010000)
3165 #define ADC_CR3_EMPIE ((uint32_t)0x00020000)
3167 /******************* Bit definition for ADC_JDMAR register *******************/
3168 #define ADC_JDMAR_JDATA ((uint16_t)0xFFFF)
3174 /*------------------------------------------------------------------------------------------------------*/
3175 /*--- ISO7816 (ISO) ---*/
3176 /*------------------------------------------------------------------------------------------------------*/
3177 /******************************** Bit definition for ISO_FIFOSR register *********************/
3178 #define ISO_FIFOSR_FULL (0x1U << 0)
3179 #define ISO_FIFOSR_EMPTY (0x1U << 1)
3180 
3181 
3182 /*------------------------------------------------------------------------------------------------------*/
3183 /*--- CACHE ---*/
3184 /*------------------------------------------------------------------------------------------------------*/
3185 /******************************** Bit definition for CACHE_CR register ****************************/
3186 #define CACHE_CR_LATENCY_Msk (0xFU)
3187 #define CACHE_CR_LATENCY_0WS (0x0U)
3188 #define CACHE_CR_LATENCY_1WS (0x1U)
3189 #define CACHE_CR_LATENCY_2WS (0x2U)
3190 #define CACHE_CR_LATENCY_3WS (0x3U)
3191 #define CACHE_CR_LATENCY_4WS (0x4U)
3192 #define CACHE_CR_LATENCY_5WS (0x5U)
3193 #define CACHE_CR_LATENCY_6WS (0x6U)
3194 #define CACHE_CR_LATENCY_7WS (0x7U)
3195 #define CACHE_CR_LATENCY_8WS (0x8U)
3196 #define CACHE_CR_LATENCY_9WS (0x9U)
3197 #define CACHE_CR_LATENCY_10WS (0xAU)
3198 #define CACHE_CR_LATENCY_11WS (0xBU)
3199 #define CACHE_CR_LATENCY_12WS (0xCU)
3200 #define CACHE_CR_LATENCY_13WS (0xDU)
3201 #define CACHE_CR_LATENCY_14WS (0xEU)
3202 #define CACHE_CR_LATENCY_15WS (0xFU)
3203 
3204 #define CACHE_CR_PREFEN_Msk (0x3U << 4)
3205 #define CACHE_CR_PREFEN_OFF (0x0U << 4)
3206 #define CACHE_CR_PREFEN_ON (0x1U << 4)
3207 
3208 #define CACHE_CR_HIFREQ (0x1U << 8)
3209 
3210 #define CACHE_CR_CHEEN (0x3U << 24)
3211 
3212 
3213 /*------------------------------------------------------------------------------------------------------*/
3214 /*--- FMC ---*/
3215 /*------------------------------------------------------------------------------------------------------*/
3216 /******************************** Bit definition for FMC_CON register ********************************/
3217 #define FMC_CON_OP_Msk (0x1FU)
3219 #define FMC_CON_WREN (0x1U << 6)
3220 #define FMC_CON_WR (0x1U << 7)
3221 
3222 #define FMC_CON_SETHLDCNT_Msk (0x7FU << 8)
3224 /******************************** Bit definition for FMC_CRCON register ********************************/
3225 #define FMC_CRCON_CRCEN (0x1U << 0)
3226 #define FMC_CRCON_CRCF (0x1U << 1)
3227 #define FMC_CRCON_PAUSE (0x1U << 2)
3228 #define FMC_CRCON_SLOWRD (0x1U << 3)
3229 #define FMC_CRCON_CRCFIE (0x1U << 8)
3230 
3231 #define FMC_CRCON_PERIOD_Pos (12U)
3232 #define FMC_CRCON_PERIOD_Msk (0xFU << FMC_CRCON_PERIOD_Pos)
3233 
3234 #define FMC_CRCON_CRCLEN_Pos (16U)
3235 #define FMC_CRCON_CRCLEN_Msk (0x3FFU << FMC_CRCON_CRCLEN_Pos)
3236 
3237 /******************************** Bit definition for FMC_STAT register *******************************/
3238 #define FMC_STAT_ERR (0x1U << 2)
3239 
3240 
3241 
3242 
3243 
3244 /*------------------------------------------------------------------------------------------------------*/
3245 /*--- ANCTL ---*/
3246 /*------------------------------------------------------------------------------------------------------*/
3247 /******************************** Bit definition for ANCTL_BGCR2 register ***************************/
3248 #define ANCTL_BGCR2_TEMPOUTEN (0x1U << 1)
3249 
3250 /******************************** Bit definition for ANCTL_MHSIENR register ***************************/
3251 #define ANCTL_MHSIENR_MHSION (0x1U << 0)
3253 /******************************** Bit definition for ANCTL_MHSISR register ***************************/
3254 #define ANCTL_MHSISR_MHSIRDY (0x1U << 0)
3256 /******************************** Bit definition for ANCTL_FHSIENR register ***************************/
3257 #define ANCTL_FHSIENR_FHSION (0x1U << 0)
3259 /******************************** Bit definition for ANCTL_FHSISR register ***************************/
3260 #define ANCTL_FHSISR_FHSIRDY (0x1U << 0)
3262 /******************************** Bit definition for ANCTL_LSIENR register ***************************/
3263 #define ANCTL_LSIENR_LSION (0x1U << 0)
3265 /******************************** Bit definition for ANCTL_LSISR register ***************************/
3266 #define ANCTL_LSISR_LSIRDY (0x1U << 0)
3268 /******************************** Bit definition for ANCTL_HSECR0 register ***************************/
3269 #define ANCTL_HSECR0_HSEON (0x1U << 0)
3270 #define ANCTL_HSECR0_BYPASS (0x1U << 1)
3271 
3272 /******************************** Bit definition for ANCTL_HSECR1 register ***************************/
3273 #define ANCTL_HSECR1_PADOEN (0x1U << 1)
3274 
3275 /******************************** Bit definition for ANCTL_HSESR register ***************************/
3276 #define ANCTL_HSESR_HSERDY (0x1U << 0)
3278 /******************************** Bit definition for ANCTL_PLLCR register ***************************/
3279 #define ANCTL_PLLCR_PLLMUL_Msk (0x3U << 6)
3280 #define ANCTL_PLLCR_PLLMUL_24 (0x0U << 6)
3281 #define ANCTL_PLLCR_PLLMUL_20 (0x1U << 6)
3282 #define ANCTL_PLLCR_PLLMUL_16 (0x2U << 6)
3283 #define ANCTL_PLLCR_PLLMUL_12 (0x3U << 6)
3284 
3285 /******************************** Bit definition for ANCTL_PLLENR register ***************************/
3286 #define ANCTL_PLLENR_PLLON (0x1U << 0)
3288 /******************************** Bit definition for ANCTL_PLLSR register ***************************/
3289 #define ANCTL_PLLSR_PLLRDY_Msk (0x3U)
3290 
3291 /******************************** Bit definition for ANCTL_PVDCR register ***************************/
3292 #define ANCTL_PVDCR_PLS_Msk (0x7U)
3293 #define ANCTL_PVDCR_PLS_LEV0 (0x0U)
3294 #define ANCTL_PVDCR_PLS_LEV1 (0x1U)
3295 #define ANCTL_PVDCR_PLS_LEV2 (0x2U)
3296 #define ANCTL_PVDCR_PLS_LEV3 (0x3U)
3297 #define ANCTL_PVDCR_PLS_LEV4 (0x4U)
3298 #define ANCTL_PVDCR_PLS_LEV5 (0x5U)
3299 #define ANCTL_PVDCR_PLS_LEV6 (0x6U)
3300 #define ANCTL_PVDCR_PLS_LEV7 (0x7U)
3301 
3302 /******************************** Bit definition for ANCTL_PVDENR register ***************************/
3303 #define ANCTL_PVDENR_PVDE (0x1U << 0)
3305 /******************************** Bit definition for ANCTL_SARENR register ***************************/
3306 #define ANCTL_SARENR_SAREN (0x1U << 0)
3308 /******************************** Bit definition for ANCTL_USBPCR register ***************************/
3309 #define ANCTL_USBPCR_USBPEN (0x1U << 0)
3310 #define ANCTL_USBPCR_DPPUEN (0x1U << 1)
3311 #define ANCTL_USBPCR_HIGHRESEN (0x1U << 2)
3312 #define ANCTL_USBPCR_DMSTEN (0x1U << 3)
3313 #define ANCTL_USBPCR_DPSTEN (0x1U << 4)
3314 
3315 /******************************** Bit definition for ANCTL_CMPACR register ***************************/
3316 #define ANCTL_CMPACR_PSEL_Msk (0xFU << 0)
3317 #define ANCTL_CMPACR_NSEL_Msk (0xFU << 4)
3318 #define ANCTL_CMPACR_CMPAEN (0x1U << 8)
3319 
3320 /******************************** Bit definition for ANCTL_CMPBCR register ***************************/
3321 #define ANCTL_CMPBCR_PSEL_Msk (0xFU << 0)
3322 #define ANCTL_CMPBCR_NSEL_Msk (0xFU << 4)
3323 #define ANCTL_CMPBCR_CMPBEN (0x1U << 8)
3324 
3325 /******************************** Bit definition for ANCTL_ISR register ***************************/
3326 #define ANCTL_ISR_MHSIIS (0x1U << 0)
3327 #define ANCTL_ISR_FHSIIS (0x1U << 1)
3328 #define ANCTL_ISR_LSIIS (0x1U << 2)
3329 #define ANCTL_ISR_HSEIS (0x1U << 3)
3330 #define ANCTL_ISR_LSEIS (0x1U << 4)
3331 #define ANCTL_ISR_PLLIS (0x1U << 5)
3332 #define ANCTL_ISR_DCSSIS (0x1U << 7)
3333 
3334 /******************************** Bit definition for ANCTL_IER register ***************************/
3335 #define ANCTL_IER_MHSIIE (0x1U << 0)
3336 #define ANCTL_IER_FHSIIE (0x1U << 1)
3337 #define ANCTL_IER_LSIIE (0x1U << 2)
3338 #define ANCTL_IER_HSEIE (0x1U << 3)
3339 #define ANCTL_IER_LSEIE (0x1U << 4)
3340 #define ANCTL_IER_PLLIE (0x1U << 5)
3341 
3342 /******************************** Bit definition for ANCTL_ICR register ***************************/
3343 #define ANCTL_ICR_MHSIIC (0x1U << 0)
3344 #define ANCTL_ICR_FHSIIC (0x1U << 1)
3345 #define ANCTL_ICR_LSIIC (0x1U << 2)
3346 #define ANCTL_ICR_HSEIC (0x1U << 3)
3347 #define ANCTL_ICR_LSEIC (0x1U << 4)
3348 #define ANCTL_ICR_PLLIC (0x1U << 5)
3349 #define ANCTL_ICR_DCSSIC (0x1U << 7)
3350 
3351 /******************************** Bit definition for ANCTL_DCSSENR register ***************************/
3352 #define ANCTL_DCSSENR_DCSSON (0x1U << 0)
3353 
3354 /******************************** Bit definition for ANCTL_DCSSCR register ***************************/
3355 #define ANCTL_DCSSCR_FREQCNT_Msk (0xFFFU)
3356 
3357 
3358 
3359 /*------------------------------------------------------------------------------------------------------*/
3360 /*--- Reset and Clock Control (RCC) ---*/
3361 /*------------------------------------------------------------------------------------------------------*/
3362 /******************************** Bit definition for RCC_PLLPRE register ***************************/
3363 #define RCC_PLLPRE_DIVEN (0x1U << 0)
3364 
3365 #define RCC_PLLPRE_RATIO_Msk (0xFU << 1)
3366 #define RCC_PLLPRE_RATIO_2 (0x0U << 1)
3367 #define RCC_PLLPRE_RATIO_3 (0x1U << 1)
3368 #define RCC_PLLPRE_RATIO_4 (0x2U << 1)
3369 #define RCC_PLLPRE_RATIO_5 (0x3U << 1)
3370 #define RCC_PLLPRE_RATIO_6 (0x4U << 1)
3371 #define RCC_PLLPRE_RATIO_7 (0x5U << 1)
3372 #define RCC_PLLPRE_RATIO_8 (0x6U << 1)
3373 #define RCC_PLLPRE_RATIO_9 (0x7U << 1)
3374 #define RCC_PLLPRE_RATIO_10 (0x8U << 1)
3375 #define RCC_PLLPRE_RATIO_11 (0x9U << 1)
3376 #define RCC_PLLPRE_RATIO_12 (0xAU << 1)
3377 #define RCC_PLLPRE_RATIO_13 (0xBU << 1)
3378 #define RCC_PLLPRE_RATIO_14 (0xCU << 1)
3379 #define RCC_PLLPRE_RATIO_15 (0xDU << 1)
3380 #define RCC_PLLPRE_RATIO_16 (0xEU << 1)
3381 
3382 #define RCC_PLLPRE_SRCEN (0x1U << 5)
3383 
3384 /******************************** Bit definition for RCC_PLLSRC register ***************************/
3385 #define RCC_PLLSRC_MHSI (0x0U)
3386 #define RCC_PLLSRC_HSE (0x1U)
3387 
3388 /******************************** Bit definition for RCC_MAINCLKSRC register ***************************/
3389 #define RCC_MAINCLKSRC_MHSI (0x0U)
3390 #define RCC_MAINCLKSRC_FHSI (0x1U)
3391 #define RCC_MAINCLKSRC_PLLCLK (0x2U)
3392 #define RCC_MAINCLKSRC_HSE (0x3U)
3393 
3394 /******************************** Bit definition for RCC_MAINCLKUEN register ***************************/
3395 #define RCC_MAINCLKUEN_ENA (0x1U)
3396 
3397 /******************************** Bit definition for RCC_USBPRE register ***************************/
3398 #define RCC_USBPRE_DIVEN (0x1U << 0)
3399 
3400 #define RCC_USBPRE_RATIO_Msk (0x3U << 1)
3401 #define RCC_USBPRE_RATIO_1_5 (0x2U << 1)
3402 #define RCC_USBPRE_RATIO_2 (0x0U << 1)
3403 #define RCC_USBPRE_RATIO_3 (0x1U << 1)
3404 
3405 #define RCC_USBPRE_SRCEN (0x1U << 3)
3406 
3407 /******************************** Bit definition for RCC_AHBPRE register ***************************/
3408 #define RCC_AHBPRE_DIVEN (0x1U << 0)
3409 
3410 #define RCC_AHBPRE_RATIO_Msk (0x3FU << 1)
3411 #define RCC_AHBPRE_RATIO_2 (0x0U << 1)
3412 #define RCC_AHBPRE_RATIO_3 (0x1U << 1)
3413 #define RCC_AHBPRE_RATIO_4 (0x2U << 1)
3414 #define RCC_AHBPRE_RATIO_5 (0x3U << 1)
3415 #define RCC_AHBPRE_RATIO_6 (0x4U << 1)
3416 #define RCC_AHBPRE_RATIO_7 (0x5U << 1)
3417 #define RCC_AHBPRE_RATIO_8 (0x6U << 1)
3418 #define RCC_AHBPRE_RATIO_9 (0x7U << 1)
3419 #define RCC_AHBPRE_RATIO_10 (0x8U << 1)
3420 #define RCC_AHBPRE_RATIO_11 (0x9U << 1)
3421 #define RCC_AHBPRE_RATIO_12 (0xAU << 1)
3422 #define RCC_AHBPRE_RATIO_13 (0xBU << 1)
3423 #define RCC_AHBPRE_RATIO_14 (0xCU << 1)
3424 #define RCC_AHBPRE_RATIO_15 (0xDU << 1)
3425 #define RCC_AHBPRE_RATIO_16 (0xEU << 1)
3426 #define RCC_AHBPRE_RATIO_17 (0xFU << 1)
3427 #define RCC_AHBPRE_RATIO_18 (0x10U << 1)
3428 #define RCC_AHBPRE_RATIO_19 (0x11U << 1)
3429 #define RCC_AHBPRE_RATIO_20 (0x12U << 1)
3430 #define RCC_AHBPRE_RATIO_21 (0x13U << 1)
3431 #define RCC_AHBPRE_RATIO_22 (0x14U << 1)
3432 #define RCC_AHBPRE_RATIO_23 (0x15U << 1)
3433 #define RCC_AHBPRE_RATIO_24 (0x16U << 1)
3434 #define RCC_AHBPRE_RATIO_25 (0x17U << 1)
3435 #define RCC_AHBPRE_RATIO_26 (0x18U << 1)
3436 #define RCC_AHBPRE_RATIO_27 (0x19U << 1)
3437 #define RCC_AHBPRE_RATIO_28 (0x1AU << 1)
3438 #define RCC_AHBPRE_RATIO_29 (0x1BU << 1)
3439 #define RCC_AHBPRE_RATIO_30 (0x1CU << 1)
3440 #define RCC_AHBPRE_RATIO_31 (0x1DU << 1)
3441 #define RCC_AHBPRE_RATIO_32 (0x1EU << 1)
3442 #define RCC_AHBPRE_RATIO_33 (0x1FU << 1)
3443 #define RCC_AHBPRE_RATIO_34 (0x20U << 1)
3444 #define RCC_AHBPRE_RATIO_35 (0x21U << 1)
3445 #define RCC_AHBPRE_RATIO_36 (0x22U << 1)
3446 #define RCC_AHBPRE_RATIO_37 (0x23U << 1)
3447 #define RCC_AHBPRE_RATIO_38 (0x24U << 1)
3448 #define RCC_AHBPRE_RATIO_39 (0x25U << 1)
3449 #define RCC_AHBPRE_RATIO_40 (0x26U << 1)
3450 #define RCC_AHBPRE_RATIO_41 (0x27U << 1)
3451 #define RCC_AHBPRE_RATIO_42 (0x28U << 1)
3452 #define RCC_AHBPRE_RATIO_43 (0x29U << 1)
3453 #define RCC_AHBPRE_RATIO_44 (0x2AU << 1)
3454 #define RCC_AHBPRE_RATIO_45 (0x2BU << 1)
3455 #define RCC_AHBPRE_RATIO_46 (0x2CU << 1)
3456 #define RCC_AHBPRE_RATIO_47 (0x2DU << 1)
3457 #define RCC_AHBPRE_RATIO_48 (0x2EU << 1)
3458 #define RCC_AHBPRE_RATIO_49 (0x2FU << 1)
3459 #define RCC_AHBPRE_RATIO_50 (0x30U << 1)
3460 #define RCC_AHBPRE_RATIO_51 (0x31U << 1)
3461 #define RCC_AHBPRE_RATIO_52 (0x32U << 1)
3462 #define RCC_AHBPRE_RATIO_53 (0x33U << 1)
3463 #define RCC_AHBPRE_RATIO_54 (0x34U << 1)
3464 #define RCC_AHBPRE_RATIO_55 (0x35U << 1)
3465 #define RCC_AHBPRE_RATIO_56 (0x36U << 1)
3466 #define RCC_AHBPRE_RATIO_57 (0x37U << 1)
3467 #define RCC_AHBPRE_RATIO_58 (0x38U << 1)
3468 #define RCC_AHBPRE_RATIO_59 (0x39U << 1)
3469 #define RCC_AHBPRE_RATIO_60 (0x3AU << 1)
3470 #define RCC_AHBPRE_RATIO_61 (0x3BU << 1)
3471 #define RCC_AHBPRE_RATIO_62 (0x3CU << 1)
3472 #define RCC_AHBPRE_RATIO_63 (0x3DU << 1)
3473 #define RCC_AHBPRE_RATIO_64 (0x3EU << 1)
3474 
3475 /******************************** Bit definition for RCC_APB1PRE register ***************************/
3476 #define RCC_APB1PRE_DIVEN (0x1U << 0)
3477 
3478 #define RCC_APB1PRE_RATIO_Msk (0x3FU << 1)
3479 #define RCC_APB1PRE_RATIO_2 (0x0U << 1)
3480 #define RCC_APB1PRE_RATIO_3 (0x1U << 1)
3481 #define RCC_APB1PRE_RATIO_4 (0x2U << 1)
3482 #define RCC_APB1PRE_RATIO_5 (0x3U << 1)
3483 #define RCC_APB1PRE_RATIO_6 (0x4U << 1)
3484 #define RCC_APB1PRE_RATIO_7 (0x5U << 1)
3485 #define RCC_APB1PRE_RATIO_8 (0x6U << 1)
3486 #define RCC_APB1PRE_RATIO_9 (0x7U << 1)
3487 #define RCC_APB1PRE_RATIO_10 (0x8U << 1)
3488 #define RCC_APB1PRE_RATIO_11 (0x9U << 1)
3489 #define RCC_APB1PRE_RATIO_12 (0xAU << 1)
3490 #define RCC_APB1PRE_RATIO_13 (0xBU << 1)
3491 #define RCC_APB1PRE_RATIO_14 (0xCU << 1)
3492 #define RCC_APB1PRE_RATIO_15 (0xDU << 1)
3493 #define RCC_APB1PRE_RATIO_16 (0xEU << 1)
3494 #define RCC_APB1PRE_RATIO_17 (0xFU << 1)
3495 #define RCC_APB1PRE_RATIO_18 (0x10U << 1)
3496 #define RCC_APB1PRE_RATIO_19 (0x11U << 1)
3497 #define RCC_APB1PRE_RATIO_20 (0x12U << 1)
3498 #define RCC_APB1PRE_RATIO_21 (0x13U << 1)
3499 #define RCC_APB1PRE_RATIO_22 (0x14U << 1)
3500 #define RCC_APB1PRE_RATIO_23 (0x15U << 1)
3501 #define RCC_APB1PRE_RATIO_24 (0x16U << 1)
3502 #define RCC_APB1PRE_RATIO_25 (0x17U << 1)
3503 #define RCC_APB1PRE_RATIO_26 (0x18U << 1)
3504 #define RCC_APB1PRE_RATIO_27 (0x19U << 1)
3505 #define RCC_APB1PRE_RATIO_28 (0x1AU << 1)
3506 #define RCC_APB1PRE_RATIO_29 (0x1BU << 1)
3507 #define RCC_APB1PRE_RATIO_30 (0x1CU << 1)
3508 #define RCC_APB1PRE_RATIO_31 (0x1DU << 1)
3509 #define RCC_APB1PRE_RATIO_32 (0x1EU << 1)
3510 #define RCC_APB1PRE_RATIO_33 (0x1FU << 1)
3511 #define RCC_APB1PRE_RATIO_34 (0x20U << 1)
3512 #define RCC_APB1PRE_RATIO_35 (0x21U << 1)
3513 #define RCC_APB1PRE_RATIO_36 (0x22U << 1)
3514 #define RCC_APB1PRE_RATIO_37 (0x23U << 1)
3515 #define RCC_APB1PRE_RATIO_38 (0x24U << 1)
3516 #define RCC_APB1PRE_RATIO_39 (0x25U << 1)
3517 #define RCC_APB1PRE_RATIO_40 (0x26U << 1)
3518 #define RCC_APB1PRE_RATIO_41 (0x27U << 1)
3519 #define RCC_APB1PRE_RATIO_42 (0x28U << 1)
3520 #define RCC_APB1PRE_RATIO_43 (0x29U << 1)
3521 #define RCC_APB1PRE_RATIO_44 (0x2AU << 1)
3522 #define RCC_APB1PRE_RATIO_45 (0x2BU << 1)
3523 #define RCC_APB1PRE_RATIO_46 (0x2CU << 1)
3524 #define RCC_APB1PRE_RATIO_47 (0x2DU << 1)
3525 #define RCC_APB1PRE_RATIO_48 (0x2EU << 1)
3526 #define RCC_APB1PRE_RATIO_49 (0x2FU << 1)
3527 #define RCC_APB1PRE_RATIO_50 (0x30U << 1)
3528 #define RCC_APB1PRE_RATIO_51 (0x31U << 1)
3529 #define RCC_APB1PRE_RATIO_52 (0x32U << 1)
3530 #define RCC_APB1PRE_RATIO_53 (0x33U << 1)
3531 #define RCC_APB1PRE_RATIO_54 (0x34U << 1)
3532 #define RCC_APB1PRE_RATIO_55 (0x35U << 1)
3533 #define RCC_APB1PRE_RATIO_56 (0x36U << 1)
3534 #define RCC_APB1PRE_RATIO_57 (0x37U << 1)
3535 #define RCC_APB1PRE_RATIO_58 (0x38U << 1)
3536 #define RCC_APB1PRE_RATIO_59 (0x39U << 1)
3537 #define RCC_APB1PRE_RATIO_60 (0x3AU << 1)
3538 #define RCC_APB1PRE_RATIO_61 (0x3BU << 1)
3539 #define RCC_APB1PRE_RATIO_62 (0x3CU << 1)
3540 #define RCC_APB1PRE_RATIO_63 (0x3DU << 1)
3541 #define RCC_APB1PRE_RATIO_64 (0x3EU << 1)
3542 
3543 #define RCC_APB1PRE_SRCEN (0x1U << 7)
3544 
3545 /******************************** Bit definition for RCC_APB2PRE register ***************************/
3546 #define RCC_APB2PRE_DIVEN (0x1U << 0)
3547 
3548 #define RCC_APB2PRE_RATIO_Msk (0x3FU << 1)
3549 #define RCC_APB2PRE_RATIO_2 (0x0U << 1)
3550 #define RCC_APB2PRE_RATIO_3 (0x1U << 1)
3551 #define RCC_APB2PRE_RATIO_4 (0x2U << 1)
3552 #define RCC_APB2PRE_RATIO_5 (0x3U << 1)
3553 #define RCC_APB2PRE_RATIO_6 (0x4U << 1)
3554 #define RCC_APB2PRE_RATIO_7 (0x5U << 1)
3555 #define RCC_APB2PRE_RATIO_8 (0x6U << 1)
3556 #define RCC_APB2PRE_RATIO_9 (0x7U << 1)
3557 #define RCC_APB2PRE_RATIO_10 (0x8U << 1)
3558 #define RCC_APB2PRE_RATIO_11 (0x9U << 1)
3559 #define RCC_APB2PRE_RATIO_12 (0xAU << 1)
3560 #define RCC_APB2PRE_RATIO_13 (0xBU << 1)
3561 #define RCC_APB2PRE_RATIO_14 (0xCU << 1)
3562 #define RCC_APB2PRE_RATIO_15 (0xDU << 1)
3563 #define RCC_APB2PRE_RATIO_16 (0xEU << 1)
3564 #define RCC_APB2PRE_RATIO_17 (0xFU << 1)
3565 #define RCC_APB2PRE_RATIO_18 (0x10U << 1)
3566 #define RCC_APB2PRE_RATIO_19 (0x11U << 1)
3567 #define RCC_APB2PRE_RATIO_20 (0x12U << 1)
3568 #define RCC_APB2PRE_RATIO_21 (0x13U << 1)
3569 #define RCC_APB2PRE_RATIO_22 (0x14U << 1)
3570 #define RCC_APB2PRE_RATIO_23 (0x15U << 1)
3571 #define RCC_APB2PRE_RATIO_24 (0x16U << 1)
3572 #define RCC_APB2PRE_RATIO_25 (0x17U << 1)
3573 #define RCC_APB2PRE_RATIO_26 (0x18U << 1)
3574 #define RCC_APB2PRE_RATIO_27 (0x19U << 1)
3575 #define RCC_APB2PRE_RATIO_28 (0x1AU << 1)
3576 #define RCC_APB2PRE_RATIO_29 (0x1BU << 1)
3577 #define RCC_APB2PRE_RATIO_30 (0x1CU << 1)
3578 #define RCC_APB2PRE_RATIO_31 (0x1DU << 1)
3579 #define RCC_APB2PRE_RATIO_32 (0x1EU << 1)
3580 #define RCC_APB2PRE_RATIO_33 (0x1FU << 1)
3581 #define RCC_APB2PRE_RATIO_34 (0x20U << 1)
3582 #define RCC_APB2PRE_RATIO_35 (0x21U << 1)
3583 #define RCC_APB2PRE_RATIO_36 (0x22U << 1)
3584 #define RCC_APB2PRE_RATIO_37 (0x23U << 1)
3585 #define RCC_APB2PRE_RATIO_38 (0x24U << 1)
3586 #define RCC_APB2PRE_RATIO_39 (0x25U << 1)
3587 #define RCC_APB2PRE_RATIO_40 (0x26U << 1)
3588 #define RCC_APB2PRE_RATIO_41 (0x27U << 1)
3589 #define RCC_APB2PRE_RATIO_42 (0x28U << 1)
3590 #define RCC_APB2PRE_RATIO_43 (0x29U << 1)
3591 #define RCC_APB2PRE_RATIO_44 (0x2AU << 1)
3592 #define RCC_APB2PRE_RATIO_45 (0x2BU << 1)
3593 #define RCC_APB2PRE_RATIO_46 (0x2CU << 1)
3594 #define RCC_APB2PRE_RATIO_47 (0x2DU << 1)
3595 #define RCC_APB2PRE_RATIO_48 (0x2EU << 1)
3596 #define RCC_APB2PRE_RATIO_49 (0x2FU << 1)
3597 #define RCC_APB2PRE_RATIO_50 (0x30U << 1)
3598 #define RCC_APB2PRE_RATIO_51 (0x31U << 1)
3599 #define RCC_APB2PRE_RATIO_52 (0x32U << 1)
3600 #define RCC_APB2PRE_RATIO_53 (0x33U << 1)
3601 #define RCC_APB2PRE_RATIO_54 (0x34U << 1)
3602 #define RCC_APB2PRE_RATIO_55 (0x35U << 1)
3603 #define RCC_APB2PRE_RATIO_56 (0x36U << 1)
3604 #define RCC_APB2PRE_RATIO_57 (0x37U << 1)
3605 #define RCC_APB2PRE_RATIO_58 (0x38U << 1)
3606 #define RCC_APB2PRE_RATIO_59 (0x39U << 1)
3607 #define RCC_APB2PRE_RATIO_60 (0x3AU << 1)
3608 #define RCC_APB2PRE_RATIO_61 (0x3BU << 1)
3609 #define RCC_APB2PRE_RATIO_62 (0x3CU << 1)
3610 #define RCC_APB2PRE_RATIO_63 (0x3DU << 1)
3611 #define RCC_APB2PRE_RATIO_64 (0x3EU << 1)
3612 
3613 #define RCC_APB2PRE_SRCEN (0x1U << 7)
3614 
3615 /******************************** Bit definition for RCC_MCLKPRE register ***************************/
3616 #define RCC_MCLKPRE_DIVEN (0x1U << 0)
3617 
3618 #define RCC_MCLKPRE_RATIO_Msk (0x3FU << 1)
3619 #define RCC_MCLKPRE_RATIO_2 (0x0U << 1)
3620 #define RCC_MCLKPRE_RATIO_3 (0x1U << 1)
3621 #define RCC_MCLKPRE_RATIO_4 (0x2U << 1)
3622 #define RCC_MCLKPRE_RATIO_5 (0x3U << 1)
3623 #define RCC_MCLKPRE_RATIO_6 (0x4U << 1)
3624 #define RCC_MCLKPRE_RATIO_7 (0x5U << 1)
3625 #define RCC_MCLKPRE_RATIO_8 (0x6U << 1)
3626 #define RCC_MCLKPRE_RATIO_9 (0x7U << 1)
3627 #define RCC_MCLKPRE_RATIO_10 (0x8U << 1)
3628 #define RCC_MCLKPRE_RATIO_11 (0x9U << 1)
3629 #define RCC_MCLKPRE_RATIO_12 (0xAU << 1)
3630 #define RCC_MCLKPRE_RATIO_13 (0xBU << 1)
3631 #define RCC_MCLKPRE_RATIO_14 (0xCU << 1)
3632 #define RCC_MCLKPRE_RATIO_15 (0xDU << 1)
3633 #define RCC_MCLKPRE_RATIO_16 (0xEU << 1)
3634 #define RCC_MCLKPRE_RATIO_17 (0xFU << 1)
3635 #define RCC_MCLKPRE_RATIO_18 (0x10U << 1)
3636 #define RCC_MCLKPRE_RATIO_19 (0x11U << 1)
3637 #define RCC_MCLKPRE_RATIO_20 (0x12U << 1)
3638 #define RCC_MCLKPRE_RATIO_21 (0x13U << 1)
3639 #define RCC_MCLKPRE_RATIO_22 (0x14U << 1)
3640 #define RCC_MCLKPRE_RATIO_23 (0x15U << 1)
3641 #define RCC_MCLKPRE_RATIO_24 (0x16U << 1)
3642 #define RCC_MCLKPRE_RATIO_25 (0x17U << 1)
3643 #define RCC_MCLKPRE_RATIO_26 (0x18U << 1)
3644 #define RCC_MCLKPRE_RATIO_27 (0x19U << 1)
3645 #define RCC_MCLKPRE_RATIO_28 (0x1AU << 1)
3646 #define RCC_MCLKPRE_RATIO_29 (0x1BU << 1)
3647 #define RCC_MCLKPRE_RATIO_30 (0x1CU << 1)
3648 #define RCC_MCLKPRE_RATIO_31 (0x1DU << 1)
3649 #define RCC_MCLKPRE_RATIO_32 (0x1EU << 1)
3650 #define RCC_MCLKPRE_RATIO_33 (0x1FU << 1)
3651 #define RCC_MCLKPRE_RATIO_34 (0x20U << 1)
3652 #define RCC_MCLKPRE_RATIO_35 (0x21U << 1)
3653 #define RCC_MCLKPRE_RATIO_36 (0x22U << 1)
3654 #define RCC_MCLKPRE_RATIO_37 (0x23U << 1)
3655 #define RCC_MCLKPRE_RATIO_38 (0x24U << 1)
3656 #define RCC_MCLKPRE_RATIO_39 (0x25U << 1)
3657 #define RCC_MCLKPRE_RATIO_40 (0x26U << 1)
3658 #define RCC_MCLKPRE_RATIO_41 (0x27U << 1)
3659 #define RCC_MCLKPRE_RATIO_42 (0x28U << 1)
3660 #define RCC_MCLKPRE_RATIO_43 (0x29U << 1)
3661 #define RCC_MCLKPRE_RATIO_44 (0x2AU << 1)
3662 #define RCC_MCLKPRE_RATIO_45 (0x2BU << 1)
3663 #define RCC_MCLKPRE_RATIO_46 (0x2CU << 1)
3664 #define RCC_MCLKPRE_RATIO_47 (0x2DU << 1)
3665 #define RCC_MCLKPRE_RATIO_48 (0x2EU << 1)
3666 #define RCC_MCLKPRE_RATIO_49 (0x2FU << 1)
3667 #define RCC_MCLKPRE_RATIO_50 (0x30U << 1)
3668 #define RCC_MCLKPRE_RATIO_51 (0x31U << 1)
3669 #define RCC_MCLKPRE_RATIO_52 (0x32U << 1)
3670 #define RCC_MCLKPRE_RATIO_53 (0x33U << 1)
3671 #define RCC_MCLKPRE_RATIO_54 (0x34U << 1)
3672 #define RCC_MCLKPRE_RATIO_55 (0x35U << 1)
3673 #define RCC_MCLKPRE_RATIO_56 (0x36U << 1)
3674 #define RCC_MCLKPRE_RATIO_57 (0x37U << 1)
3675 #define RCC_MCLKPRE_RATIO_58 (0x38U << 1)
3676 #define RCC_MCLKPRE_RATIO_59 (0x39U << 1)
3677 #define RCC_MCLKPRE_RATIO_60 (0x3AU << 1)
3678 #define RCC_MCLKPRE_RATIO_61 (0x3BU << 1)
3679 #define RCC_MCLKPRE_RATIO_62 (0x3CU << 1)
3680 #define RCC_MCLKPRE_RATIO_63 (0x3DU << 1)
3681 #define RCC_MCLKPRE_RATIO_64 (0x3EU << 1)
3682 
3683 #define RCC_MCLKPRE_SRCEN (0x1U << 7)
3684 
3685 /******************************** Bit definition for RCC_I2SPRE register ***************************/
3686 #define RCC_I2SPRE_DIVEN (0x1U << 0)
3687 
3688 #define RCC_I2SPRE_RATIO_Msk (0x1FFU << 1)
3689 #define RCC_I2SPRE_RATIO_2 (0x0U << 1)
3690 #define RCC_I2SPRE_RATIO_3 (0x1U << 1)
3691 #define RCC_I2SPRE_RATIO_4 (0x2U << 1)
3692 #define RCC_I2SPRE_RATIO_5 (0x3U << 1)
3693 #define RCC_I2SPRE_RATIO_6 (0x4U << 1)
3694 #define RCC_I2SPRE_RATIO_7 (0x5U << 1)
3695 #define RCC_I2SPRE_RATIO_8 (0x6U << 1)
3696 #define RCC_I2SPRE_RATIO_9 (0x7U << 1)
3697 #define RCC_I2SPRE_RATIO_10 (0x8U << 1)
3698 #define RCC_I2SPRE_RATIO_11 (0x9U << 1)
3699 #define RCC_I2SPRE_RATIO_12 (0xAU << 1)
3700 #define RCC_I2SPRE_RATIO_13 (0xBU << 1)
3701 #define RCC_I2SPRE_RATIO_14 (0xCU << 1)
3702 #define RCC_I2SPRE_RATIO_15 (0xDU << 1)
3703 #define RCC_I2SPRE_RATIO_16 (0xEU << 1)
3704 #define RCC_I2SPRE_RATIO_17 (0xFU << 1)
3705 #define RCC_I2SPRE_RATIO_18 (0x10U << 1)
3706 #define RCC_I2SPRE_RATIO_19 (0x11U << 1)
3707 #define RCC_I2SPRE_RATIO_20 (0x12U << 1)
3708 #define RCC_I2SPRE_RATIO_21 (0x13U << 1)
3709 #define RCC_I2SPRE_RATIO_22 (0x14U << 1)
3710 #define RCC_I2SPRE_RATIO_23 (0x15U << 1)
3711 #define RCC_I2SPRE_RATIO_24 (0x16U << 1)
3712 #define RCC_I2SPRE_RATIO_25 (0x17U << 1)
3713 #define RCC_I2SPRE_RATIO_26 (0x18U << 1)
3714 #define RCC_I2SPRE_RATIO_27 (0x19U << 1)
3715 #define RCC_I2SPRE_RATIO_28 (0x1AU << 1)
3716 #define RCC_I2SPRE_RATIO_29 (0x1BU << 1)
3717 #define RCC_I2SPRE_RATIO_30 (0x1CU << 1)
3718 #define RCC_I2SPRE_RATIO_31 (0x1DU << 1)
3719 #define RCC_I2SPRE_RATIO_32 (0x1EU << 1)
3720 #define RCC_I2SPRE_RATIO_33 (0x1FU << 1)
3721 #define RCC_I2SPRE_RATIO_34 (0x20U << 1)
3722 #define RCC_I2SPRE_RATIO_35 (0x21U << 1)
3723 #define RCC_I2SPRE_RATIO_36 (0x22U << 1)
3724 #define RCC_I2SPRE_RATIO_37 (0x23U << 1)
3725 #define RCC_I2SPRE_RATIO_38 (0x24U << 1)
3726 #define RCC_I2SPRE_RATIO_39 (0x25U << 1)
3727 #define RCC_I2SPRE_RATIO_40 (0x26U << 1)
3728 #define RCC_I2SPRE_RATIO_41 (0x27U << 1)
3729 #define RCC_I2SPRE_RATIO_42 (0x28U << 1)
3730 #define RCC_I2SPRE_RATIO_43 (0x29U << 1)
3731 #define RCC_I2SPRE_RATIO_44 (0x2AU << 1)
3732 #define RCC_I2SPRE_RATIO_45 (0x2BU << 1)
3733 #define RCC_I2SPRE_RATIO_46 (0x2CU << 1)
3734 #define RCC_I2SPRE_RATIO_47 (0x2DU << 1)
3735 #define RCC_I2SPRE_RATIO_48 (0x2EU << 1)
3736 #define RCC_I2SPRE_RATIO_49 (0x2FU << 1)
3737 #define RCC_I2SPRE_RATIO_50 (0x30U << 1)
3738 #define RCC_I2SPRE_RATIO_51 (0x31U << 1)
3739 #define RCC_I2SPRE_RATIO_52 (0x32U << 1)
3740 #define RCC_I2SPRE_RATIO_53 (0x33U << 1)
3741 #define RCC_I2SPRE_RATIO_54 (0x34U << 1)
3742 #define RCC_I2SPRE_RATIO_55 (0x35U << 1)
3743 #define RCC_I2SPRE_RATIO_56 (0x36U << 1)
3744 #define RCC_I2SPRE_RATIO_57 (0x37U << 1)
3745 #define RCC_I2SPRE_RATIO_58 (0x38U << 1)
3746 #define RCC_I2SPRE_RATIO_59 (0x39U << 1)
3747 #define RCC_I2SPRE_RATIO_60 (0x3AU << 1)
3748 #define RCC_I2SPRE_RATIO_61 (0x3BU << 1)
3749 #define RCC_I2SPRE_RATIO_62 (0x3CU << 1)
3750 #define RCC_I2SPRE_RATIO_63 (0x3DU << 1)
3751 #define RCC_I2SPRE_RATIO_64 (0x3EU << 1)
3752 #define RCC_I2SPRE_RATIO_65 (0x3FU << 1)
3753 #define RCC_I2SPRE_RATIO_66 (0x40U << 1)
3754 #define RCC_I2SPRE_RATIO_67 (0x41U << 1)
3755 #define RCC_I2SPRE_RATIO_68 (0x42U << 1)
3756 #define RCC_I2SPRE_RATIO_69 (0x43U << 1)
3757 #define RCC_I2SPRE_RATIO_70 (0x44U << 1)
3758 #define RCC_I2SPRE_RATIO_71 (0x45U << 1)
3759 #define RCC_I2SPRE_RATIO_72 (0x46U << 1)
3760 #define RCC_I2SPRE_RATIO_73 (0x47U << 1)
3761 #define RCC_I2SPRE_RATIO_74 (0x48U << 1)
3762 #define RCC_I2SPRE_RATIO_75 (0x49U << 1)
3763 #define RCC_I2SPRE_RATIO_76 (0x4AU << 1)
3764 #define RCC_I2SPRE_RATIO_77 (0x4BU << 1)
3765 #define RCC_I2SPRE_RATIO_78 (0x4CU << 1)
3766 #define RCC_I2SPRE_RATIO_79 (0x4DU << 1)
3767 #define RCC_I2SPRE_RATIO_80 (0x4EU << 1)
3768 #define RCC_I2SPRE_RATIO_81 (0x4FU << 1)
3769 #define RCC_I2SPRE_RATIO_82 (0x50U << 1)
3770 #define RCC_I2SPRE_RATIO_83 (0x51U << 1)
3771 #define RCC_I2SPRE_RATIO_84 (0x52U << 1)
3772 #define RCC_I2SPRE_RATIO_85 (0x53U << 1)
3773 #define RCC_I2SPRE_RATIO_86 (0x54U << 1)
3774 #define RCC_I2SPRE_RATIO_87 (0x55U << 1)
3775 #define RCC_I2SPRE_RATIO_88 (0x56U << 1)
3776 #define RCC_I2SPRE_RATIO_89 (0x57U << 1)
3777 #define RCC_I2SPRE_RATIO_90 (0x58U << 1)
3778 #define RCC_I2SPRE_RATIO_91 (0x59U << 1)
3779 #define RCC_I2SPRE_RATIO_92 (0x5AU << 1)
3780 #define RCC_I2SPRE_RATIO_93 (0x5BU << 1)
3781 #define RCC_I2SPRE_RATIO_94 (0x5CU << 1)
3782 #define RCC_I2SPRE_RATIO_95 (0x5DU << 1)
3783 #define RCC_I2SPRE_RATIO_96 (0x5EU << 1)
3784 #define RCC_I2SPRE_RATIO_97 (0x5FU << 1)
3785 #define RCC_I2SPRE_RATIO_98 (0x60U << 1)
3786 #define RCC_I2SPRE_RATIO_99 (0x61U << 1)
3787 #define RCC_I2SPRE_RATIO_100 (0x62U << 1)
3788 #define RCC_I2SPRE_RATIO_101 (0x63U << 1)
3789 #define RCC_I2SPRE_RATIO_102 (0x64U << 1)
3790 #define RCC_I2SPRE_RATIO_103 (0x65U << 1)
3791 #define RCC_I2SPRE_RATIO_104 (0x66U << 1)
3792 #define RCC_I2SPRE_RATIO_105 (0x67U << 1)
3793 #define RCC_I2SPRE_RATIO_106 (0x68U << 1)
3794 #define RCC_I2SPRE_RATIO_107 (0x69U << 1)
3795 #define RCC_I2SPRE_RATIO_108 (0x6AU << 1)
3796 #define RCC_I2SPRE_RATIO_109 (0x6BU << 1)
3797 #define RCC_I2SPRE_RATIO_110 (0x6CU << 1)
3798 #define RCC_I2SPRE_RATIO_111 (0x6DU << 1)
3799 #define RCC_I2SPRE_RATIO_112 (0x6EU << 1)
3800 #define RCC_I2SPRE_RATIO_113 (0x6FU << 1)
3801 #define RCC_I2SPRE_RATIO_114 (0x70U << 1)
3802 #define RCC_I2SPRE_RATIO_115 (0x71U << 1)
3803 #define RCC_I2SPRE_RATIO_116 (0x72U << 1)
3804 #define RCC_I2SPRE_RATIO_117 (0x73U << 1)
3805 #define RCC_I2SPRE_RATIO_118 (0x74U << 1)
3806 #define RCC_I2SPRE_RATIO_119 (0x75U << 1)
3807 #define RCC_I2SPRE_RATIO_120 (0x76U << 1)
3808 #define RCC_I2SPRE_RATIO_121 (0x77U << 1)
3809 #define RCC_I2SPRE_RATIO_122 (0x78U << 1)
3810 #define RCC_I2SPRE_RATIO_123 (0x79U << 1)
3811 #define RCC_I2SPRE_RATIO_124 (0x7AU << 1)
3812 #define RCC_I2SPRE_RATIO_125 (0x7BU << 1)
3813 #define RCC_I2SPRE_RATIO_126 (0x7CU << 1)
3814 #define RCC_I2SPRE_RATIO_127 (0x7DU << 1)
3815 #define RCC_I2SPRE_RATIO_128 (0x7EU << 1)
3816 #define RCC_I2SPRE_RATIO_129 (0x7FU << 1)
3817 #define RCC_I2SPRE_RATIO_130 (0x80U << 1)
3818 #define RCC_I2SPRE_RATIO_131 (0x81U << 1)
3819 #define RCC_I2SPRE_RATIO_132 (0x82U << 1)
3820 #define RCC_I2SPRE_RATIO_133 (0x83U << 1)
3821 #define RCC_I2SPRE_RATIO_134 (0x84U << 1)
3822 #define RCC_I2SPRE_RATIO_135 (0x85U << 1)
3823 #define RCC_I2SPRE_RATIO_136 (0x86U << 1)
3824 #define RCC_I2SPRE_RATIO_137 (0x87U << 1)
3825 #define RCC_I2SPRE_RATIO_138 (0x88U << 1)
3826 #define RCC_I2SPRE_RATIO_139 (0x89U << 1)
3827 #define RCC_I2SPRE_RATIO_140 (0x8AU << 1)
3828 #define RCC_I2SPRE_RATIO_141 (0x8BU << 1)
3829 #define RCC_I2SPRE_RATIO_142 (0x8CU << 1)
3830 #define RCC_I2SPRE_RATIO_143 (0x8DU << 1)
3831 #define RCC_I2SPRE_RATIO_144 (0x8EU << 1)
3832 #define RCC_I2SPRE_RATIO_145 (0x8FU << 1)
3833 #define RCC_I2SPRE_RATIO_146 (0x90U << 1)
3834 #define RCC_I2SPRE_RATIO_147 (0x91U << 1)
3835 #define RCC_I2SPRE_RATIO_148 (0x92U << 1)
3836 #define RCC_I2SPRE_RATIO_149 (0x93U << 1)
3837 #define RCC_I2SPRE_RATIO_150 (0x94U << 1)
3838 #define RCC_I2SPRE_RATIO_151 (0x95U << 1)
3839 #define RCC_I2SPRE_RATIO_152 (0x96U << 1)
3840 #define RCC_I2SPRE_RATIO_153 (0x97U << 1)
3841 #define RCC_I2SPRE_RATIO_154 (0x98U << 1)
3842 #define RCC_I2SPRE_RATIO_155 (0x99U << 1)
3843 #define RCC_I2SPRE_RATIO_156 (0x9AU << 1)
3844 #define RCC_I2SPRE_RATIO_157 (0x9BU << 1)
3845 #define RCC_I2SPRE_RATIO_158 (0x9CU << 1)
3846 #define RCC_I2SPRE_RATIO_159 (0x9DU << 1)
3847 #define RCC_I2SPRE_RATIO_160 (0x9EU << 1)
3848 #define RCC_I2SPRE_RATIO_161 (0x9FU << 1)
3849 #define RCC_I2SPRE_RATIO_162 (0xA0U << 1)
3850 #define RCC_I2SPRE_RATIO_163 (0xA1U << 1)
3851 #define RCC_I2SPRE_RATIO_164 (0xA2U << 1)
3852 #define RCC_I2SPRE_RATIO_165 (0xA3U << 1)
3853 #define RCC_I2SPRE_RATIO_166 (0xA4U << 1)
3854 #define RCC_I2SPRE_RATIO_167 (0xA5U << 1)
3855 #define RCC_I2SPRE_RATIO_168 (0xA6U << 1)
3856 #define RCC_I2SPRE_RATIO_169 (0xA7U << 1)
3857 #define RCC_I2SPRE_RATIO_170 (0xA8U << 1)
3858 #define RCC_I2SPRE_RATIO_171 (0xA9U << 1)
3859 #define RCC_I2SPRE_RATIO_172 (0xAAU << 1)
3860 #define RCC_I2SPRE_RATIO_173 (0xABU << 1)
3861 #define RCC_I2SPRE_RATIO_174 (0xACU << 1)
3862 #define RCC_I2SPRE_RATIO_175 (0xADU << 1)
3863 #define RCC_I2SPRE_RATIO_176 (0xAEU << 1)
3864 #define RCC_I2SPRE_RATIO_177 (0xAFU << 1)
3865 #define RCC_I2SPRE_RATIO_178 (0xB0U << 1)
3866 #define RCC_I2SPRE_RATIO_179 (0xB1U << 1)
3867 #define RCC_I2SPRE_RATIO_180 (0xB2U << 1)
3868 #define RCC_I2SPRE_RATIO_181 (0xB3U << 1)
3869 #define RCC_I2SPRE_RATIO_182 (0xB4U << 1)
3870 #define RCC_I2SPRE_RATIO_183 (0xB5U << 1)
3871 #define RCC_I2SPRE_RATIO_184 (0xB6U << 1)
3872 #define RCC_I2SPRE_RATIO_185 (0xB7U << 1)
3873 #define RCC_I2SPRE_RATIO_186 (0xB8U << 1)
3874 #define RCC_I2SPRE_RATIO_187 (0xB9U << 1)
3875 #define RCC_I2SPRE_RATIO_188 (0xBAU << 1)
3876 #define RCC_I2SPRE_RATIO_189 (0xBBU << 1)
3877 #define RCC_I2SPRE_RATIO_190 (0xBCU << 1)
3878 #define RCC_I2SPRE_RATIO_191 (0xBDU << 1)
3879 #define RCC_I2SPRE_RATIO_192 (0xBEU << 1)
3880 #define RCC_I2SPRE_RATIO_193 (0xBFU << 1)
3881 #define RCC_I2SPRE_RATIO_194 (0xC0U << 1)
3882 #define RCC_I2SPRE_RATIO_195 (0xC1U << 1)
3883 #define RCC_I2SPRE_RATIO_196 (0xC2U << 1)
3884 #define RCC_I2SPRE_RATIO_197 (0xC3U << 1)
3885 #define RCC_I2SPRE_RATIO_198 (0xC4U << 1)
3886 #define RCC_I2SPRE_RATIO_199 (0xC5U << 1)
3887 #define RCC_I2SPRE_RATIO_200 (0xC6U << 1)
3888 #define RCC_I2SPRE_RATIO_201 (0xC7U << 1)
3889 #define RCC_I2SPRE_RATIO_202 (0xC8U << 1)
3890 #define RCC_I2SPRE_RATIO_203 (0xC9U << 1)
3891 #define RCC_I2SPRE_RATIO_204 (0xCAU << 1)
3892 #define RCC_I2SPRE_RATIO_205 (0xCBU << 1)
3893 #define RCC_I2SPRE_RATIO_206 (0xCCU << 1)
3894 #define RCC_I2SPRE_RATIO_207 (0xCDU << 1)
3895 #define RCC_I2SPRE_RATIO_208 (0xCEU << 1)
3896 #define RCC_I2SPRE_RATIO_209 (0xCFU << 1)
3897 #define RCC_I2SPRE_RATIO_210 (0xD0U << 1)
3898 #define RCC_I2SPRE_RATIO_211 (0xD1U << 1)
3899 #define RCC_I2SPRE_RATIO_212 (0xD2U << 1)
3900 #define RCC_I2SPRE_RATIO_213 (0xD3U << 1)
3901 #define RCC_I2SPRE_RATIO_214 (0xD4U << 1)
3902 #define RCC_I2SPRE_RATIO_215 (0xD5U << 1)
3903 #define RCC_I2SPRE_RATIO_216 (0xD6U << 1)
3904 #define RCC_I2SPRE_RATIO_217 (0xD7U << 1)
3905 #define RCC_I2SPRE_RATIO_218 (0xD8U << 1)
3906 #define RCC_I2SPRE_RATIO_219 (0xD9U << 1)
3907 #define RCC_I2SPRE_RATIO_220 (0xDAU << 1)
3908 #define RCC_I2SPRE_RATIO_221 (0xDBU << 1)
3909 #define RCC_I2SPRE_RATIO_222 (0xDCU << 1)
3910 #define RCC_I2SPRE_RATIO_223 (0xDDU << 1)
3911 #define RCC_I2SPRE_RATIO_224 (0xDEU << 1)
3912 #define RCC_I2SPRE_RATIO_225 (0xDFU << 1)
3913 #define RCC_I2SPRE_RATIO_226 (0xE0U << 1)
3914 #define RCC_I2SPRE_RATIO_227 (0xE1U << 1)
3915 #define RCC_I2SPRE_RATIO_228 (0xE2U << 1)
3916 #define RCC_I2SPRE_RATIO_229 (0xE3U << 1)
3917 #define RCC_I2SPRE_RATIO_230 (0xE4U << 1)
3918 #define RCC_I2SPRE_RATIO_231 (0xE5U << 1)
3919 #define RCC_I2SPRE_RATIO_232 (0xE6U << 1)
3920 #define RCC_I2SPRE_RATIO_233 (0xE7U << 1)
3921 #define RCC_I2SPRE_RATIO_234 (0xE8U << 1)
3922 #define RCC_I2SPRE_RATIO_235 (0xE9U << 1)
3923 #define RCC_I2SPRE_RATIO_236 (0xEAU << 1)
3924 #define RCC_I2SPRE_RATIO_237 (0xEBU << 1)
3925 #define RCC_I2SPRE_RATIO_238 (0xECU << 1)
3926 #define RCC_I2SPRE_RATIO_239 (0xEDU << 1)
3927 #define RCC_I2SPRE_RATIO_240 (0xEEU << 1)
3928 #define RCC_I2SPRE_RATIO_241 (0xEFU << 1)
3929 #define RCC_I2SPRE_RATIO_242 (0xF0U << 1)
3930 #define RCC_I2SPRE_RATIO_243 (0xF1U << 1)
3931 #define RCC_I2SPRE_RATIO_244 (0xF2U << 1)
3932 #define RCC_I2SPRE_RATIO_245 (0xF3U << 1)
3933 #define RCC_I2SPRE_RATIO_246 (0xF4U << 1)
3934 #define RCC_I2SPRE_RATIO_247 (0xF5U << 1)
3935 #define RCC_I2SPRE_RATIO_248 (0xF6U << 1)
3936 #define RCC_I2SPRE_RATIO_249 (0xF7U << 1)
3937 #define RCC_I2SPRE_RATIO_250 (0xF8U << 1)
3938 #define RCC_I2SPRE_RATIO_251 (0xF9U << 1)
3939 #define RCC_I2SPRE_RATIO_252 (0xFAU << 1)
3940 #define RCC_I2SPRE_RATIO_253 (0xFBU << 1)
3941 #define RCC_I2SPRE_RATIO_254 (0xFCU << 1)
3942 #define RCC_I2SPRE_RATIO_255 (0xFDU << 1)
3943 #define RCC_I2SPRE_RATIO_256 (0xFEU << 1)
3944 #define RCC_I2SPRE_RATIO_257 (0xFFU << 1)
3945 #define RCC_I2SPRE_RATIO_258 (0x100U << 1)
3946 #define RCC_I2SPRE_RATIO_259 (0x101U << 1)
3947 #define RCC_I2SPRE_RATIO_260 (0x102U << 1)
3948 #define RCC_I2SPRE_RATIO_261 (0x103U << 1)
3949 #define RCC_I2SPRE_RATIO_262 (0x104U << 1)
3950 #define RCC_I2SPRE_RATIO_263 (0x105U << 1)
3951 #define RCC_I2SPRE_RATIO_264 (0x106U << 1)
3952 #define RCC_I2SPRE_RATIO_265 (0x107U << 1)
3953 #define RCC_I2SPRE_RATIO_266 (0x108U << 1)
3954 #define RCC_I2SPRE_RATIO_267 (0x109U << 1)
3955 #define RCC_I2SPRE_RATIO_268 (0x10AU << 1)
3956 #define RCC_I2SPRE_RATIO_269 (0x10BU << 1)
3957 #define RCC_I2SPRE_RATIO_270 (0x10CU << 1)
3958 #define RCC_I2SPRE_RATIO_271 (0x10DU << 1)
3959 #define RCC_I2SPRE_RATIO_272 (0x10EU << 1)
3960 #define RCC_I2SPRE_RATIO_273 (0x10FU << 1)
3961 #define RCC_I2SPRE_RATIO_274 (0x110U << 1)
3962 #define RCC_I2SPRE_RATIO_275 (0x111U << 1)
3963 #define RCC_I2SPRE_RATIO_276 (0x112U << 1)
3964 #define RCC_I2SPRE_RATIO_277 (0x113U << 1)
3965 #define RCC_I2SPRE_RATIO_278 (0x114U << 1)
3966 #define RCC_I2SPRE_RATIO_279 (0x115U << 1)
3967 #define RCC_I2SPRE_RATIO_280 (0x116U << 1)
3968 #define RCC_I2SPRE_RATIO_281 (0x117U << 1)
3969 #define RCC_I2SPRE_RATIO_282 (0x118U << 1)
3970 #define RCC_I2SPRE_RATIO_283 (0x119U << 1)
3971 #define RCC_I2SPRE_RATIO_284 (0x11AU << 1)
3972 #define RCC_I2SPRE_RATIO_285 (0x11BU << 1)
3973 #define RCC_I2SPRE_RATIO_286 (0x11CU << 1)
3974 #define RCC_I2SPRE_RATIO_287 (0x11DU << 1)
3975 #define RCC_I2SPRE_RATIO_288 (0x11EU << 1)
3976 #define RCC_I2SPRE_RATIO_289 (0x11FU << 1)
3977 #define RCC_I2SPRE_RATIO_290 (0x120U << 1)
3978 #define RCC_I2SPRE_RATIO_291 (0x121U << 1)
3979 #define RCC_I2SPRE_RATIO_292 (0x122U << 1)
3980 #define RCC_I2SPRE_RATIO_293 (0x123U << 1)
3981 #define RCC_I2SPRE_RATIO_294 (0x124U << 1)
3982 #define RCC_I2SPRE_RATIO_295 (0x125U << 1)
3983 #define RCC_I2SPRE_RATIO_296 (0x126U << 1)
3984 #define RCC_I2SPRE_RATIO_297 (0x127U << 1)
3985 #define RCC_I2SPRE_RATIO_298 (0x128U << 1)
3986 #define RCC_I2SPRE_RATIO_299 (0x129U << 1)
3987 #define RCC_I2SPRE_RATIO_300 (0x12AU << 1)
3988 #define RCC_I2SPRE_RATIO_301 (0x12BU << 1)
3989 #define RCC_I2SPRE_RATIO_302 (0x12CU << 1)
3990 #define RCC_I2SPRE_RATIO_303 (0x12DU << 1)
3991 #define RCC_I2SPRE_RATIO_304 (0x12EU << 1)
3992 #define RCC_I2SPRE_RATIO_305 (0x12FU << 1)
3993 #define RCC_I2SPRE_RATIO_306 (0x130U << 1)
3994 #define RCC_I2SPRE_RATIO_307 (0x131U << 1)
3995 #define RCC_I2SPRE_RATIO_308 (0x132U << 1)
3996 #define RCC_I2SPRE_RATIO_309 (0x133U << 1)
3997 #define RCC_I2SPRE_RATIO_310 (0x134U << 1)
3998 #define RCC_I2SPRE_RATIO_311 (0x135U << 1)
3999 #define RCC_I2SPRE_RATIO_312 (0x136U << 1)
4000 #define RCC_I2SPRE_RATIO_313 (0x137U << 1)
4001 #define RCC_I2SPRE_RATIO_314 (0x138U << 1)
4002 #define RCC_I2SPRE_RATIO_315 (0x139U << 1)
4003 #define RCC_I2SPRE_RATIO_316 (0x13AU << 1)
4004 #define RCC_I2SPRE_RATIO_317 (0x13BU << 1)
4005 #define RCC_I2SPRE_RATIO_318 (0x13CU << 1)
4006 #define RCC_I2SPRE_RATIO_319 (0x13DU << 1)
4007 #define RCC_I2SPRE_RATIO_320 (0x13EU << 1)
4008 #define RCC_I2SPRE_RATIO_321 (0x13FU << 1)
4009 #define RCC_I2SPRE_RATIO_322 (0x140U << 1)
4010 #define RCC_I2SPRE_RATIO_323 (0x141U << 1)
4011 #define RCC_I2SPRE_RATIO_324 (0x142U << 1)
4012 #define RCC_I2SPRE_RATIO_325 (0x143U << 1)
4013 #define RCC_I2SPRE_RATIO_326 (0x144U << 1)
4014 #define RCC_I2SPRE_RATIO_327 (0x145U << 1)
4015 #define RCC_I2SPRE_RATIO_328 (0x146U << 1)
4016 #define RCC_I2SPRE_RATIO_329 (0x147U << 1)
4017 #define RCC_I2SPRE_RATIO_330 (0x148U << 1)
4018 #define RCC_I2SPRE_RATIO_331 (0x149U << 1)
4019 #define RCC_I2SPRE_RATIO_332 (0x14AU << 1)
4020 #define RCC_I2SPRE_RATIO_333 (0x14BU << 1)
4021 #define RCC_I2SPRE_RATIO_334 (0x14CU << 1)
4022 #define RCC_I2SPRE_RATIO_335 (0x14DU << 1)
4023 #define RCC_I2SPRE_RATIO_336 (0x14EU << 1)
4024 #define RCC_I2SPRE_RATIO_337 (0x14FU << 1)
4025 #define RCC_I2SPRE_RATIO_338 (0x150U << 1)
4026 #define RCC_I2SPRE_RATIO_339 (0x151U << 1)
4027 #define RCC_I2SPRE_RATIO_340 (0x152U << 1)
4028 #define RCC_I2SPRE_RATIO_341 (0x153U << 1)
4029 #define RCC_I2SPRE_RATIO_342 (0x154U << 1)
4030 #define RCC_I2SPRE_RATIO_343 (0x155U << 1)
4031 #define RCC_I2SPRE_RATIO_344 (0x156U << 1)
4032 #define RCC_I2SPRE_RATIO_345 (0x157U << 1)
4033 #define RCC_I2SPRE_RATIO_346 (0x158U << 1)
4034 #define RCC_I2SPRE_RATIO_347 (0x159U << 1)
4035 #define RCC_I2SPRE_RATIO_348 (0x15AU << 1)
4036 #define RCC_I2SPRE_RATIO_349 (0x15BU << 1)
4037 #define RCC_I2SPRE_RATIO_350 (0x15CU << 1)
4038 #define RCC_I2SPRE_RATIO_351 (0x15DU << 1)
4039 #define RCC_I2SPRE_RATIO_352 (0x15EU << 1)
4040 #define RCC_I2SPRE_RATIO_353 (0x15FU << 1)
4041 #define RCC_I2SPRE_RATIO_354 (0x160U << 1)
4042 #define RCC_I2SPRE_RATIO_355 (0x161U << 1)
4043 #define RCC_I2SPRE_RATIO_356 (0x162U << 1)
4044 #define RCC_I2SPRE_RATIO_357 (0x163U << 1)
4045 #define RCC_I2SPRE_RATIO_358 (0x164U << 1)
4046 #define RCC_I2SPRE_RATIO_359 (0x165U << 1)
4047 #define RCC_I2SPRE_RATIO_360 (0x166U << 1)
4048 #define RCC_I2SPRE_RATIO_361 (0x167U << 1)
4049 #define RCC_I2SPRE_RATIO_362 (0x168U << 1)
4050 #define RCC_I2SPRE_RATIO_363 (0x169U << 1)
4051 #define RCC_I2SPRE_RATIO_364 (0x16AU << 1)
4052 #define RCC_I2SPRE_RATIO_365 (0x16BU << 1)
4053 #define RCC_I2SPRE_RATIO_366 (0x16CU << 1)
4054 #define RCC_I2SPRE_RATIO_367 (0x16DU << 1)
4055 #define RCC_I2SPRE_RATIO_368 (0x16EU << 1)
4056 #define RCC_I2SPRE_RATIO_369 (0x16FU << 1)
4057 #define RCC_I2SPRE_RATIO_370 (0x170U << 1)
4058 #define RCC_I2SPRE_RATIO_371 (0x171U << 1)
4059 #define RCC_I2SPRE_RATIO_372 (0x172U << 1)
4060 #define RCC_I2SPRE_RATIO_373 (0x173U << 1)
4061 #define RCC_I2SPRE_RATIO_374 (0x174U << 1)
4062 #define RCC_I2SPRE_RATIO_375 (0x175U << 1)
4063 #define RCC_I2SPRE_RATIO_376 (0x176U << 1)
4064 #define RCC_I2SPRE_RATIO_377 (0x177U << 1)
4065 #define RCC_I2SPRE_RATIO_378 (0x178U << 1)
4066 #define RCC_I2SPRE_RATIO_379 (0x179U << 1)
4067 #define RCC_I2SPRE_RATIO_380 (0x17AU << 1)
4068 #define RCC_I2SPRE_RATIO_381 (0x17BU << 1)
4069 #define RCC_I2SPRE_RATIO_382 (0x17CU << 1)
4070 #define RCC_I2SPRE_RATIO_383 (0x17DU << 1)
4071 #define RCC_I2SPRE_RATIO_384 (0x17EU << 1)
4072 #define RCC_I2SPRE_RATIO_385 (0x17FU << 1)
4073 #define RCC_I2SPRE_RATIO_386 (0x180U << 1)
4074 #define RCC_I2SPRE_RATIO_387 (0x181U << 1)
4075 #define RCC_I2SPRE_RATIO_388 (0x182U << 1)
4076 #define RCC_I2SPRE_RATIO_389 (0x183U << 1)
4077 #define RCC_I2SPRE_RATIO_390 (0x184U << 1)
4078 #define RCC_I2SPRE_RATIO_391 (0x185U << 1)
4079 #define RCC_I2SPRE_RATIO_392 (0x186U << 1)
4080 #define RCC_I2SPRE_RATIO_393 (0x187U << 1)
4081 #define RCC_I2SPRE_RATIO_394 (0x188U << 1)
4082 #define RCC_I2SPRE_RATIO_395 (0x189U << 1)
4083 #define RCC_I2SPRE_RATIO_396 (0x18AU << 1)
4084 #define RCC_I2SPRE_RATIO_397 (0x18BU << 1)
4085 #define RCC_I2SPRE_RATIO_398 (0x18CU << 1)
4086 #define RCC_I2SPRE_RATIO_399 (0x18DU << 1)
4087 #define RCC_I2SPRE_RATIO_400 (0x18EU << 1)
4088 #define RCC_I2SPRE_RATIO_401 (0x18FU << 1)
4089 #define RCC_I2SPRE_RATIO_402 (0x190U << 1)
4090 #define RCC_I2SPRE_RATIO_403 (0x191U << 1)
4091 #define RCC_I2SPRE_RATIO_404 (0x192U << 1)
4092 #define RCC_I2SPRE_RATIO_405 (0x193U << 1)
4093 #define RCC_I2SPRE_RATIO_406 (0x194U << 1)
4094 #define RCC_I2SPRE_RATIO_407 (0x195U << 1)
4095 #define RCC_I2SPRE_RATIO_408 (0x196U << 1)
4096 #define RCC_I2SPRE_RATIO_409 (0x197U << 1)
4097 #define RCC_I2SPRE_RATIO_410 (0x198U << 1)
4098 #define RCC_I2SPRE_RATIO_411 (0x199U << 1)
4099 #define RCC_I2SPRE_RATIO_412 (0x19AU << 1)
4100 #define RCC_I2SPRE_RATIO_413 (0x19BU << 1)
4101 #define RCC_I2SPRE_RATIO_414 (0x19CU << 1)
4102 #define RCC_I2SPRE_RATIO_415 (0x19DU << 1)
4103 #define RCC_I2SPRE_RATIO_416 (0x19EU << 1)
4104 #define RCC_I2SPRE_RATIO_417 (0x19FU << 1)
4105 #define RCC_I2SPRE_RATIO_418 (0x1A0U << 1)
4106 #define RCC_I2SPRE_RATIO_419 (0x1A1U << 1)
4107 #define RCC_I2SPRE_RATIO_420 (0x1A2U << 1)
4108 #define RCC_I2SPRE_RATIO_421 (0x1A3U << 1)
4109 #define RCC_I2SPRE_RATIO_422 (0x1A4U << 1)
4110 #define RCC_I2SPRE_RATIO_423 (0x1A5U << 1)
4111 #define RCC_I2SPRE_RATIO_424 (0x1A6U << 1)
4112 #define RCC_I2SPRE_RATIO_425 (0x1A7U << 1)
4113 #define RCC_I2SPRE_RATIO_426 (0x1A8U << 1)
4114 #define RCC_I2SPRE_RATIO_427 (0x1A9U << 1)
4115 #define RCC_I2SPRE_RATIO_428 (0x1AAU << 1)
4116 #define RCC_I2SPRE_RATIO_429 (0x1ABU << 1)
4117 #define RCC_I2SPRE_RATIO_430 (0x1ACU << 1)
4118 #define RCC_I2SPRE_RATIO_431 (0x1ADU << 1)
4119 #define RCC_I2SPRE_RATIO_432 (0x1AEU << 1)
4120 #define RCC_I2SPRE_RATIO_433 (0x1AFU << 1)
4121 #define RCC_I2SPRE_RATIO_434 (0x1B0U << 1)
4122 #define RCC_I2SPRE_RATIO_435 (0x1B1U << 1)
4123 #define RCC_I2SPRE_RATIO_436 (0x1B2U << 1)
4124 #define RCC_I2SPRE_RATIO_437 (0x1B3U << 1)
4125 #define RCC_I2SPRE_RATIO_438 (0x1B4U << 1)
4126 #define RCC_I2SPRE_RATIO_439 (0x1B5U << 1)
4127 #define RCC_I2SPRE_RATIO_440 (0x1B6U << 1)
4128 #define RCC_I2SPRE_RATIO_441 (0x1B7U << 1)
4129 #define RCC_I2SPRE_RATIO_442 (0x1B8U << 1)
4130 #define RCC_I2SPRE_RATIO_443 (0x1B9U << 1)
4131 #define RCC_I2SPRE_RATIO_444 (0x1BAU << 1)
4132 #define RCC_I2SPRE_RATIO_445 (0x1BBU << 1)
4133 #define RCC_I2SPRE_RATIO_446 (0x1BCU << 1)
4134 #define RCC_I2SPRE_RATIO_447 (0x1BDU << 1)
4135 #define RCC_I2SPRE_RATIO_448 (0x1BEU << 1)
4136 #define RCC_I2SPRE_RATIO_449 (0x1BFU << 1)
4137 #define RCC_I2SPRE_RATIO_450 (0x1C0U << 1)
4138 #define RCC_I2SPRE_RATIO_451 (0x1C1U << 1)
4139 #define RCC_I2SPRE_RATIO_452 (0x1C2U << 1)
4140 #define RCC_I2SPRE_RATIO_453 (0x1C3U << 1)
4141 #define RCC_I2SPRE_RATIO_454 (0x1C4U << 1)
4142 #define RCC_I2SPRE_RATIO_455 (0x1C5U << 1)
4143 #define RCC_I2SPRE_RATIO_456 (0x1C6U << 1)
4144 #define RCC_I2SPRE_RATIO_457 (0x1C7U << 1)
4145 #define RCC_I2SPRE_RATIO_458 (0x1C8U << 1)
4146 #define RCC_I2SPRE_RATIO_459 (0x1C9U << 1)
4147 #define RCC_I2SPRE_RATIO_460 (0x1CAU << 1)
4148 #define RCC_I2SPRE_RATIO_461 (0x1CBU << 1)
4149 #define RCC_I2SPRE_RATIO_462 (0x1CCU << 1)
4150 #define RCC_I2SPRE_RATIO_463 (0x1CDU << 1)
4151 #define RCC_I2SPRE_RATIO_464 (0x1CEU << 1)
4152 #define RCC_I2SPRE_RATIO_465 (0x1CFU << 1)
4153 #define RCC_I2SPRE_RATIO_466 (0x1D0U << 1)
4154 #define RCC_I2SPRE_RATIO_467 (0x1D1U << 1)
4155 #define RCC_I2SPRE_RATIO_468 (0x1D2U << 1)
4156 #define RCC_I2SPRE_RATIO_469 (0x1D3U << 1)
4157 #define RCC_I2SPRE_RATIO_470 (0x1D4U << 1)
4158 #define RCC_I2SPRE_RATIO_471 (0x1D5U << 1)
4159 #define RCC_I2SPRE_RATIO_472 (0x1D6U << 1)
4160 #define RCC_I2SPRE_RATIO_473 (0x1D7U << 1)
4161 #define RCC_I2SPRE_RATIO_474 (0x1D8U << 1)
4162 #define RCC_I2SPRE_RATIO_475 (0x1D9U << 1)
4163 #define RCC_I2SPRE_RATIO_476 (0x1DAU << 1)
4164 #define RCC_I2SPRE_RATIO_477 (0x1DBU << 1)
4165 #define RCC_I2SPRE_RATIO_478 (0x1DCU << 1)
4166 #define RCC_I2SPRE_RATIO_479 (0x1DDU << 1)
4167 #define RCC_I2SPRE_RATIO_480 (0x1DEU << 1)
4168 #define RCC_I2SPRE_RATIO_481 (0x1DFU << 1)
4169 #define RCC_I2SPRE_RATIO_482 (0x1E0U << 1)
4170 #define RCC_I2SPRE_RATIO_483 (0x1E1U << 1)
4171 #define RCC_I2SPRE_RATIO_484 (0x1E2U << 1)
4172 #define RCC_I2SPRE_RATIO_485 (0x1E3U << 1)
4173 #define RCC_I2SPRE_RATIO_486 (0x1E4U << 1)
4174 #define RCC_I2SPRE_RATIO_487 (0x1E5U << 1)
4175 #define RCC_I2SPRE_RATIO_488 (0x1E6U << 1)
4176 #define RCC_I2SPRE_RATIO_489 (0x1E7U << 1)
4177 #define RCC_I2SPRE_RATIO_490 (0x1E8U << 1)
4178 #define RCC_I2SPRE_RATIO_491 (0x1E9U << 1)
4179 #define RCC_I2SPRE_RATIO_492 (0x1EAU << 1)
4180 #define RCC_I2SPRE_RATIO_493 (0x1EBU << 1)
4181 #define RCC_I2SPRE_RATIO_494 (0x1ECU << 1)
4182 #define RCC_I2SPRE_RATIO_495 (0x1EDU << 1)
4183 #define RCC_I2SPRE_RATIO_496 (0x1EEU << 1)
4184 #define RCC_I2SPRE_RATIO_497 (0x1EFU << 1)
4185 #define RCC_I2SPRE_RATIO_498 (0x1F0U << 1)
4186 #define RCC_I2SPRE_RATIO_499 (0x1F1U << 1)
4187 #define RCC_I2SPRE_RATIO_500 (0x1F2U << 1)
4188 #define RCC_I2SPRE_RATIO_501 (0x1F3U << 1)
4189 #define RCC_I2SPRE_RATIO_502 (0x1F4U << 1)
4190 #define RCC_I2SPRE_RATIO_503 (0x1F5U << 1)
4191 #define RCC_I2SPRE_RATIO_504 (0x1F6U << 1)
4192 #define RCC_I2SPRE_RATIO_505 (0x1F7U << 1)
4193 #define RCC_I2SPRE_RATIO_506 (0x1F8U << 1)
4194 #define RCC_I2SPRE_RATIO_507 (0x1F9U << 1)
4195 #define RCC_I2SPRE_RATIO_508 (0x1FAU << 1)
4196 #define RCC_I2SPRE_RATIO_509 (0x1FBU << 1)
4197 #define RCC_I2SPRE_RATIO_510 (0x1FCU << 1)
4198 #define RCC_I2SPRE_RATIO_511 (0x1FDU << 1)
4199 #define RCC_I2SPRE_RATIO_512 (0x1FEU << 1)
4200 
4201 #define RCC_I2SPRE_SRCEN (0x1U << 10)
4202 
4203 /******************************** Bit definition for RCC_MCLKSRC register ***************************/
4204 #define RCC_MCLKSRC_MAINCLK (0x0U)
4205 #define RCC_MCLKSRC_FHSI (0x1U)
4206 
4207 /******************************** Bit definition for RCC_USBFIFOCLKSRC register ***************************/
4208 #define RCC_USBFIFOCLKSRC_AHBCLK (0x0U)
4209 #define RCC_USBFIFOCLKSRC_USBCLK (0x1U)
4210 
4211 /******************************** Bit definition for RCC_MCOSEL register ***************************/
4212 #define RCC_MCOSEL_NOCLOCK (0x0U)
4213 #define RCC_MCOSEL_AHBCLK (0x1U << 0)
4214 #define RCC_MCOSEL_HSE (0x1U << 1)
4215 #define RCC_MCOSEL_MHSI (0x1U << 2)
4216 #define RCC_MCOSEL_PLLDIV2 (0x1U << 3)
4217 #define RCC_MCOSEL_MCLK (0x1U << 4)
4218 
4219 /******************************** Bit definition for RCC_AHBENR0 register ***************************/
4220 #define RCC_AHBENR0_IWDGEN (0x1U << 2)
4221 
4222 /******************************** Bit definition for RCC_AHBENR1 register ***************************/
4223 #define RCC_AHBENR1_USBEN (0x1U << 1)
4224 #define RCC_AHBENR1_ISOEN (0x1U << 2)
4225 #define RCC_AHBENR1_FLASHEN (0x1U << 3)
4226 #define RCC_AHBENR1_CACHEEN (0x1U << 4)
4227 #define RCC_AHBENR1_SYSEN (0x1U << 5)
4228 #define RCC_AHBENR1_DMAC1BREN (0x1U << 6)
4229 #define RCC_AHBENR1_DMAC2BREN (0x1U << 7)
4230 #define RCC_AHBENR1_CRCSFMEN (0x1U << 8)
4231 
4232 /******************************** Bit definition for RCC_AHBENR2 register ***************************/
4233 #define RCC_AHBENR2_BDIEN (0x1U << 2)
4234 
4235 /******************************** Bit definition for RCC_APB1ENR register ***************************/
4236 #define RCC_APB1ENR_DMAC1EN (0x1U << 0)
4237 #define RCC_APB1ENR_TIM1EN (0x1U << 1)
4238 #define RCC_APB1ENR_TIM2EN (0x1U << 2)
4239 #define RCC_APB1ENR_TIM3EN (0x1U << 3)
4240 #define RCC_APB1ENR_TIM4EN (0x1U << 4)
4241 #define RCC_APB1ENR_GPIOAEN (0x1U << 5)
4242 #define RCC_APB1ENR_GPIOBEN (0x1U << 6)
4243 #define RCC_APB1ENR_GPIOCEN (0x1U << 7)
4244 #define RCC_APB1ENR_GPIODEN (0x1U << 8)
4245 #define RCC_APB1ENR_EXTIEN (0x1U << 9)
4246 #define RCC_APB1ENR_AFIOEN (0x1U << 10)
4247 #define RCC_APB1ENR_ADCEN (0x1U << 11)
4248 #define RCC_APB1ENR_QSPIEN (0x1U << 12)
4249 #define RCC_APB1ENR_SPIS1EN (0x1U << 13)
4250 #define RCC_APB1ENR_UART1EN (0x1U << 14)
4251 #define RCC_APB1ENR_BMX1EN (0x1U << 15)
4252 
4253 /******************************** Bit definition for RCC_APB2ENR register ***************************/
4254 #define RCC_APB2ENR_DMAC2EN (0x1U << 0)
4255 #define RCC_APB2ENR_WWDGEN (0x1U << 1)
4256 #define RCC_APB2ENR_UART2EN (0x1U << 2)
4257 #define RCC_APB2ENR_UART3EN (0x1U << 3)
4258 #define RCC_APB2ENR_SPIM2EN (0x1U << 4)
4259 #define RCC_APB2ENR_SPIS2EN (0x1U << 5)
4260 #define RCC_APB2ENR_I2SEN (0x1U << 6)
4261 #define RCC_APB2ENR_I2C1EN (0x1U << 7)
4262 #define RCC_APB2ENR_I2C2EN (0x1U << 8)
4263 #define RCC_APB2ENR_RNGEN (0x1U << 9)
4264 #define RCC_APB2ENR_LEDEN (0x1U << 10)
4265 #define RCC_APB2ENR_BMX2EN (0x1U << 11)
4266 
4267 
4268 /******************************** Bit definition for RCC_RNGCLKENR register ***************************/
4269 #define RCC_RNGCLKENR_CLKEN (0x1U)
4270 
4271 /******************************** Bit definition for RCC_IWDGCLKENR register ***************************/
4272 #define RCC_IWDGCLKENR_IWDGCLKEN (0x1U)
4273 #define RCC_IWDGCLKENR_DCSSCLKEN (0x1U << 2)
4274 
4275 /******************************** Bit definition for RCC_USBCLKENR register ***************************/
4276 #define RCC_USBCLKENR_CLKEN (0x1U)
4277 
4278 /******************************** Bit definition for RCC_I2SCLKENR register ***************************/
4279 #define RCC_I2SCLKENR_CLKEN (0x1U)
4280 
4281 /******************************** Bit definition for RCC_SPIS1CLKENR register ***************************/
4282 #define RCC_SPIS1CLKENR_CLKEN (0x1U)
4283 
4284 /******************************** Bit definition for RCC_SPIS2CLKENR register ***************************/
4285 #define RCC_SPIS2CLKENR_CLKEN (0x1U)
4286 
4287 /******************************** Bit definition for RCC_USBFIFOCLKENR register ***************************/
4288 #define RCC_USBFIFOCLKENR_CLKEN (0x1U)
4289 
4290 /******************************** Bit definition for RCC_AHBRSTR1 register ***************************/
4291 #define RCC_AHBRSTR1_USBRST (0x1U << 1)
4292 #define RCC_AHBRSTR1_ISORST (0x1U << 2)
4293 #define RCC_AHBRSTR1_FLASHRST (0x1U << 3)
4294 #define RCC_AHBRSTR1_CACHERST (0x1U << 4)
4295 #define RCC_AHBRSTR1_SYSRST (0x1U << 5)
4296 #define RCC_AHBRSTR1_CRCSFMRST (0x1U << 8)
4297 
4298 /******************************** Bit definition for RCC_APB1RSTR register ***************************/
4299 #define RCC_APB1RSTR_DMAC1RST (0x1U << 0)
4300 #define RCC_APB1RSTR_TIM1RST (0x1U << 1)
4301 #define RCC_APB1RSTR_TIM2RST (0x1U << 2)
4302 #define RCC_APB1RSTR_TIM3RST (0x1U << 3)
4303 #define RCC_APB1RSTR_TIM4RST (0x1U << 4)
4304 #define RCC_APB1RSTR_GPIOARST (0x1U << 5)
4305 #define RCC_APB1RSTR_GPIOBRST (0x1U << 6)
4306 #define RCC_APB1RSTR_GPIOCRST (0x1U << 7)
4307 #define RCC_APB1RSTR_GPIODRST (0x1U << 8)
4308 #define RCC_APB1RSTR_EXTIRST (0x1U << 9)
4309 #define RCC_APB1RSTR_AFIORST (0x1U << 10)
4310 #define RCC_APB1RSTR_ADCRST (0x1U << 11)
4311 #define RCC_APB1RSTR_QSPIRST (0x1U << 12)
4312 #define RCC_APB1RSTR_SPIS1RST (0x1U << 13)
4313 #define RCC_APB1RSTR_UART1RST (0x1U << 14)
4314 #define RCC_APB1RSTR_BMX1RST (0x1U << 15)
4315 
4316 /******************************** Bit definition for RCC_APB2RSTR register ***************************/
4317 #define RCC_APB2RSTR_DMAC2RST (0x1U << 0)
4318 #define RCC_APB2RSTR_WWDGRST (0x1U << 1)
4319 #define RCC_APB2RSTR_UART2RST (0x1U << 2)
4320 #define RCC_APB2RSTR_UART3RST (0x1U << 3)
4321 #define RCC_APB2RSTR_SPIM2RST (0x1U << 4)
4322 #define RCC_APB2RSTR_SPIS2RST (0x1U << 5)
4323 #define RCC_APB2RSTR_I2SRST (0x1U << 6)
4324 #define RCC_APB2RSTR_I2C1RST (0x1U << 7)
4325 #define RCC_APB2RSTR_I2C2RST (0x1U << 8)
4326 #define RCC_APB2RSTR_RNGRST (0x1U << 9)
4327 #define RCC_APB2RSTR_LEDRST (0x1U << 10)
4328 #define RCC_APB2RSTR_BMX2RST (0x1U << 11)
4329 
4330 /******************************** Bit definition for RCC_I2SCLKRSTR register ***************************/
4331 #define RCC_I2SCLKRSTR_SCLKRST (0x1U)
4332 
4333 /******************************** Bit definition for RCC_CLRRSTSTAT register ***************************/
4334 #define RCC_CLRRSTSTAT_CLR (0x1U)
4335 
4336 /******************************** Bit definition for RCC_BDRSTR register ***************************/
4337 #define RCC_BDRSTR_BDRST (0x1U)
4338 
4339 /******************************** Bit definition for RCC_LSI2RTCENR register ***************************/
4340 #define RCC_LSI2RTCENR_CLKEN (0x1U)
4341 
4342 /******************************** Bit definition for RCC_HSE2RTCENR register ***************************/
4343 #define RCC_HSE2RTCENR_DIVEN (0x1U)
4344 
4345 /******************************** Bit definition for RCC_RSTSTAT register ***************************/
4346 #define RCC_RSTSTAT_LPWRRSTF (0x1U << 0)
4347 #define RCC_RSTSTAT_WWDGRSTF (0x1U << 1)
4348 #define RCC_RSTSTAT_IWDGRSTF (0x1U << 2)
4349 #define RCC_RSTSTAT_SFTRSTF (0x1U << 3)
4350 #define RCC_RSTSTAT_PORRSTF (0x1U << 4)
4351 #define RCC_RSTSTAT_PINRSTF (0x1U << 5)
4352 
4353 
4354 
4355 /*------------------------------------------------------------------------------------------------------*/
4356 /*--- Power Control (PWR) ---*/
4357 /*------------------------------------------------------------------------------------------------------*/
4358 /******************************** Bit definition for PWR_CR0 register *********************************/
4359 #define PWR_CR0_DBP (0x1U << 0)
4361 #define PWR_CR0_FCLKSD (0x1U << 3)
4362 
4363 #define PWR_CR0_PDDS_Pos (5U)
4364 #define PWR_CR0_PDDS_Msk (0x3U << PWR_CR0_PDDS_Pos)
4365 
4366 #define PWR_CR0_S32KMODE (0x1U << 18)
4367 #define PWR_CR0_S4KMODE (0x1U << 19)
4368 
4369 /******************************** Bit definition for PWR_CR1 register *********************************/
4370 #define PWR_CR1_CWUF (0x1U << 0)
4371 #define PWR_CR1_CSBF (0x1U << 1)
4372 #define PWR_CR1_CSPF (0x1U << 2)
4373 #define PWR_CR1_CCKF (0x1U << 3)
4374 
4375 /******************************** Bit definition for PWR_CR2 register *********************************/
4376 #define PWR_CR2_EWUP (0x1U << 0)
4377 
4378 /******************************** Bit definition for PWR_SR0 register *********************************/
4379 #define PWR_SR0_PVDO (0x1U << 0)
4380 
4381 /******************************** Bit definition for PWR_SR1 register *********************************/
4382 #define PWR_SR1_WUF (0x1U << 0)
4383 #define PWR_SR1_SBF (0x1U << 1)
4384 #define PWR_SR1_SPF (0x1U << 2)
4385 #define PWR_SR1_CKF (0x1U << 3)
4386 
4387 
4388 
4389 
4390 
4391 
4392 #define BIT_BAND_ADDR(addr, bitnum) ((((uint32_t)(addr)) & 0xF0000000) + 0x2000000 + ((((uint32_t)(addr)) & 0xFFFFF) << 5) + ((bitnum) << 2))
4393 
4394 
4395 #ifdef USE_STDPERIPH_DRIVER
4396  #include "mg32f10x_conf.h"
4397 #endif
4398 
4399 
4404 #define SET_BIT(REG, BIT) ((REG) |= (BIT))
4405 
4406 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
4407 
4408 #define READ_BIT(REG, BIT) ((REG) & (BIT))
4409 
4410 #define CLEAR_REG(REG) ((REG) = (0x0))
4411 
4412 #define WRITE_REG(REG, VAL) ((REG) = (VAL))
4413 
4414 #define READ_REG(REG) ((REG))
4415 
4416 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
4417 
4422 #ifdef __cplusplus
4423 }
4424 #endif
4425 
4426 #endif /* __MG32F10x_H__ */
4427 
uint32_t RESERVED1
Definition: mg32f10x.h:504
Definition: mg32f10x.h:571
uint32_t RESERVED2
Definition: mg32f10x.h:814
Definition: mg32f10x.h:250
Definition: mg32f10x.h:725
uint32_t RESERVED6
Definition: mg32f10x.h:883
uint8_t RESERVED3
Definition: mg32f10x.h:737
Definition: mg32f10x.h:460
uint32_t RESERVED0
Definition: mg32f10x.h:443
uint32_t RESERVED0
Definition: mg32f10x.h:855
uint32_t RESERVED4
Definition: mg32f10x.h:875
uint8_t RESERVED0
Definition: mg32f10x.h:730
Definition: mg32f10x.h:274
uint32_t RESERVED0
Definition: mg32f10x.h:679
uint32_t RESERVED1
Definition: mg32f10x.h:702
CMSIS Cortex-M3 Core Peripheral Access Layer Header File.
Definition: mg32f10x.h:203
uint32_t RESERVED4
Definition: mg32f10x.h:822
uint32_t RESERVED0
Definition: mg32f10x.h:924
Definition: mg32f10x.h:807
Definition: mg32f10x.h:422
Definition: mg32f10x.h:362
uint32_t RESERVED0
Definition: mg32f10x.h:302
Definition: mg32f10x.h:390
Definition: mg32f10x.h:776
uint32_t RESERVED3
Definition: mg32f10x.h:817
Definition: mg32f10x.h:264
uint8_t RESERVED4
Definition: mg32f10x.h:742
Definition: mg32f10x.h:521
uint8_t RESERVED1
Definition: mg32f10x.h:732
uint8_t RESERVED2
Definition: mg32f10x.h:735
Definition: mg32f10x.h:224
Definition: mg32f10x.h:670
Definition: mg32f10x.h:902
uint32_t RESERVED0
Definition: mg32f10x.h:907
Definition: mg32f10x.h:285
Library configuration file.
uint32_t RESERVED1
Definition: mg32f10x.h:913
Definition: mg32f10x.h:849
uint32_t RESERVED6
Definition: mg32f10x.h:830
Definition: mg32f10x.h:332
CMSIS Device System Header File for MG32F10x Device Series.
Definition: mg32f10x.h:297
Definition: mg32f10x.h:606
Definition: mg32f10x.h:715
Definition: mg32f10x.h:477
Definition: mg32f10x.h:922
uint32_t RESERVED1
Definition: mg32f10x.h:863
uint32_t RESERVED0
Definition: mg32f10x.h:654
Definition: mg32f10x.h:413
Definition: mg32f10x.h:439
Definition: mg32f10x.h:375