MG32F10x Standard Peripherals Firmware Library
Data Fields
SYS_TypeDef Struct Reference

Data Fields

__IM uint32_t ID
 
__IM uint32_t MEMSZ
 
uint32_t RESERVED0
 
__IM uint32_t BTCR
 
__IM uint32_t MEMWEN
 
__IM uint32_t SENDEV
 
__IM uint32_t RSTCR
 
__IM uint32_t IF4LCK
 
__IM uint32_t IF5LCK
 
__IM uint32_t IF6LCK
 
__IM uint32_t IF7LCK
 
uint32_t RESERVED1 [2]
 
__IM uint32_t BTSR
 

Field Documentation

◆ BTCR

__IM uint32_t BTCR

SYS BOOT Control register, Address offset: 0x00C

◆ BTSR

__IM uint32_t BTSR

SYS Boot Status register, Address offset: 0x034

◆ ID

__IM uint32_t ID

SYS ID register, Address offset: 0x000

◆ IF4LCK

__IM uint32_t IF4LCK

SYS Info4 Write Enable register, Address offset: 0x01C

◆ IF5LCK

__IM uint32_t IF5LCK

SYS Info5 Write Enable register, Address offset: 0x020

◆ IF6LCK

__IM uint32_t IF6LCK

SYS Info6 Write Enable register, Address offset: 0x024

◆ IF7LCK

__IM uint32_t IF7LCK

SYS Info7 Write Enable register, Address offset: 0x028

◆ MEMSZ

__IM uint32_t MEMSZ

SYS Memory Size register, Address offset: 0x004

◆ MEMWEN

__IM uint32_t MEMWEN

SYS Main Memory Write Enable register, Address offset: 0x010

◆ RESERVED0

uint32_t RESERVED0

Reserved, 0x008

◆ RESERVED1

uint32_t RESERVED1[2]

Reserved, 0x02C - 0x030

◆ RSTCR

__IM uint32_t RSTCR

SYS Reset Control register, Address offset: 0x018

◆ SENDEV

__IM uint32_t SENDEV

SYS Second Development Control register, Address offset: 0x014


The documentation for this struct was generated from the following file: