MG32F10x Standard Peripherals Firmware Library
Data Fields
PWR_TypeDef Struct Reference

Data Fields

__IOM uint32_t CR0
 
__OM uint32_t CR1
 
__IOM uint32_t CR2
 
uint32_t RESERVED0
 
__IM uint32_t SR0
 
__IM uint32_t SR1
 
__IOM uint32_t GPREG0
 
__IOM uint32_t GPREG1
 
__IOM uint32_t CFGR
 
uint32_t RESERVED1
 
__OM uint32_t ANAKEY1
 
__OM uint32_t ANAKEY2
 

Field Documentation

◆ ANAKEY1

__OM uint32_t ANAKEY1

ANCTL write enable key register 0, Address offset: 0x028

◆ ANAKEY2

__OM uint32_t ANAKEY2

ANCTL write enable key register 1, Address offset: 0x02C

◆ CFGR

__IOM uint32_t CFGR

PWR configuration register, Address offset: 0x020

◆ CR0

__IOM uint32_t CR0

Control register 0, Address offset: 0x000

◆ CR1

__OM uint32_t CR1

Control register 1, Address offset: 0x004

◆ CR2

__IOM uint32_t CR2

Control register 2, Address offset: 0x008

◆ GPREG0

__IOM uint32_t GPREG0

General purpose register 0, Address offset: 0x018

◆ GPREG1

__IOM uint32_t GPREG1

General purpose register 1, Address offset: 0x01C

◆ RESERVED0

uint32_t RESERVED0

Reserved, 0x00C

◆ RESERVED1

uint32_t RESERVED1

Reserved, 0x024

◆ SR0

__IM uint32_t SR0

Status register 0, Address offset: 0x010

◆ SR1

__IM uint32_t SR1

Status register 1, Address offset: 0x014


The documentation for this struct was generated from the following file: