MG32F10x Standard Peripherals Firmware Library
Data Fields

Structure type to access the System Control Block (SCB). More...

#include <core_cm3.h>

Data Fields

__IM uint32_t CPUID
 
__IOM uint32_t ICSR
 
__IOM uint32_t VTOR
 
__IOM uint32_t AIRCR
 
__IOM uint32_t SCR
 
__IOM uint32_t CCR
 
__IOM uint8_t SHP [12U]
 
__IOM uint32_t SHCSR
 
__IOM uint32_t CFSR
 
__IOM uint32_t HFSR
 
__IOM uint32_t DFSR
 
__IOM uint32_t MMFAR
 
__IOM uint32_t BFAR
 
__IOM uint32_t AFSR
 
__IM uint32_t PFR [2U]
 
__IM uint32_t DFR
 
__IM uint32_t ADR
 
__IM uint32_t MMFR [4U]
 
__IM uint32_t ISAR [5U]
 
uint32_t RESERVED0 [5U]
 
__IOM uint32_t CPACR
 

Detailed Description

Structure type to access the System Control Block (SCB).

Field Documentation

◆ ADR

__IM uint32_t ADR

Offset: 0x04C (R/ ) Auxiliary Feature Register

◆ AFSR

__IOM uint32_t AFSR

Offset: 0x03C (R/W) Auxiliary Fault Status Register

◆ AIRCR

__IOM uint32_t AIRCR

Offset: 0x00C (R/W) Application Interrupt and Reset Control Register

◆ BFAR

__IOM uint32_t BFAR

Offset: 0x038 (R/W) BusFault Address Register

◆ CCR

__IOM uint32_t CCR

Offset: 0x014 (R/W) Configuration Control Register

◆ CFSR

__IOM uint32_t CFSR

Offset: 0x028 (R/W) Configurable Fault Status Register

◆ CPACR

__IOM uint32_t CPACR

Offset: 0x088 (R/W) Coprocessor Access Control Register

◆ CPUID

__IM uint32_t CPUID

Offset: 0x000 (R/ ) CPUID Base Register

◆ DFR

__IM uint32_t DFR

Offset: 0x048 (R/ ) Debug Feature Register

◆ DFSR

__IOM uint32_t DFSR

Offset: 0x030 (R/W) Debug Fault Status Register

◆ HFSR

__IOM uint32_t HFSR

Offset: 0x02C (R/W) HardFault Status Register

◆ ICSR

__IOM uint32_t ICSR

Offset: 0x004 (R/W) Interrupt Control and State Register

◆ ISAR

__IM uint32_t ISAR[5U]

Offset: 0x060 (R/ ) Instruction Set Attributes Register

◆ MMFAR

__IOM uint32_t MMFAR

Offset: 0x034 (R/W) MemManage Fault Address Register

◆ MMFR

__IM uint32_t MMFR[4U]

Offset: 0x050 (R/ ) Memory Model Feature Register

◆ PFR

__IM uint32_t PFR[2U]

Offset: 0x040 (R/ ) Processor Feature Register

◆ SCR

__IOM uint32_t SCR

Offset: 0x010 (R/W) System Control Register

◆ SHCSR

__IOM uint32_t SHCSR

Offset: 0x024 (R/W) System Handler Control and State Register

◆ SHP

__IOM uint8_t SHP[12U]

Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)

◆ VTOR

__IOM uint32_t VTOR

Offset: 0x008 (R/W) Vector Table Offset Register


The documentation for this struct was generated from the following file: