MG32F10x Standard Peripherals Firmware Library
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*************** (C) COPYRIGHT 2020 - 2023 megawin Technology *************** * @file IWDG/IWDG_Reset/readme.txt * @author megawin Application Team * @version V0.1.10 * @date 05-January-2023 * @brief Description of the IWDG IWDG_Reset example. ****************************************************************************** * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, MEGAWIN SHALL NOT BE HELD LIABLE FOR ANY DIRECT, * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM * THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. ******************************************************************************
This example describes how to use the IWDG.
In this example, Main clock is from PLL clock and it is configured at 96MHz. The PLL clock is based on 8MHz HSE. APB1 and APB2 clock is from Main clock.
Note that there is any problem with IWDG: 1, Once IWDG is enabled, it cannot be disabled even if a reset occurs.
Solution: Configure the IWDG timeout setting to maximum before the program runs, and continuously reload the IWDG counter after that.
2, If IWDG is enabled, Once a reset occurs, the IWDG domain needs three LSI clock cycles to be ready.
Solution: After the LSI is ready, wait about 1ms before configuring the IWDG.
3, Continuously performing IWDG reload counter operations may not reload IWDG counter
Solution: It is best to reload IWDG counter when the RVU bit is 0. (RVU bit indicate the reload counter operation is finish)
In order to make the program work, you must do the following :
Run the example